* [PATCH linux-evl 0/2] Add RISC-V support to EVL
@ 2025-10-10 10:10 Tobias Schaffner
2025-10-10 10:10 ` [PATCH 1/2] riscv: Add EVL core Tobias Schaffner
` (2 more replies)
0 siblings, 3 replies; 14+ messages in thread
From: Tobias Schaffner @ 2025-10-10 10:10 UTC (permalink / raw)
To: xenomai; +Cc: rpm, Tobias Schaffner
Hi all,
this series introduces an initial EVL port for RISC-V.
While some tests are still failing, I’d like to share this early
version with the community to gather feedback, reviews, and hopefully
some assistance in refining the port.
The patches have been tested in combination with the Dovetail RISC-V
port on top of v6.12-evl1-rebase.
Looking forward to your feedback and suggestions.
Best,
Tobias
Tobias Schaffner (1):
riscv: Add EVL core
shannmu (1):
riscv: Add FPU register test support
arch/riscv/Kconfig | 2 +
arch/riscv/include/asm/evl/calibration.h | 12 ++
arch/riscv/include/asm/evl/fptest.h | 31 +++++
arch/riscv/include/asm/evl/syscall.h | 25 ++++
arch/riscv/include/asm/evl/thread.h | 12 ++
arch/riscv/include/dovetail/irq.h | 11 ++
arch/riscv/include/dovetail/mm_info.h | 7 ++
arch/riscv/include/dovetail/netdevice.h | 7 ++
arch/riscv/include/dovetail/poll.h | 7 ++
arch/riscv/include/dovetail/thread_info.h | 7 ++
arch/riscv/include/uapi/asm/evl/fptest.h | 138 ++++++++++++++++++++++
11 files changed, 259 insertions(+)
create mode 100644 arch/riscv/include/asm/evl/calibration.h
create mode 100644 arch/riscv/include/asm/evl/fptest.h
create mode 100644 arch/riscv/include/asm/evl/syscall.h
create mode 100644 arch/riscv/include/asm/evl/thread.h
create mode 100644 arch/riscv/include/dovetail/irq.h
create mode 100644 arch/riscv/include/dovetail/mm_info.h
create mode 100644 arch/riscv/include/dovetail/netdevice.h
create mode 100644 arch/riscv/include/dovetail/poll.h
create mode 100644 arch/riscv/include/dovetail/thread_info.h
create mode 100644 arch/riscv/include/uapi/asm/evl/fptest.h
--
2.43.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/2] riscv: Add EVL core
2025-10-10 10:10 [PATCH linux-evl 0/2] Add RISC-V support to EVL Tobias Schaffner
@ 2025-10-10 10:10 ` Tobias Schaffner
2025-10-10 10:10 ` [PATCH 2/2] riscv: Add FPU register test support Tobias Schaffner
2026-07-07 22:30 ` [PATCH linux-evl 0/2] Add RISC-V support to EVL Florian Bezdeka
2 siblings, 0 replies; 14+ messages in thread
From: Tobias Schaffner @ 2025-10-10 10:10 UTC (permalink / raw)
To: xenomai; +Cc: rpm, Tobias Schaffner
Signed-off-by: Tobias Schaffner <tobias.schaffner@siemens.com>
---
arch/riscv/Kconfig | 2 ++
arch/riscv/include/asm/evl/calibration.h | 12 +++++++++++
arch/riscv/include/asm/evl/fptest.h | 24 ++++++++++++++++++++++
arch/riscv/include/asm/evl/syscall.h | 25 +++++++++++++++++++++++
arch/riscv/include/asm/evl/thread.h | 12 +++++++++++
arch/riscv/include/dovetail/irq.h | 11 ++++++++++
arch/riscv/include/dovetail/mm_info.h | 7 +++++++
arch/riscv/include/dovetail/netdevice.h | 7 +++++++
arch/riscv/include/dovetail/poll.h | 7 +++++++
arch/riscv/include/dovetail/thread_info.h | 7 +++++++
arch/riscv/include/uapi/asm/evl/fptest.h | 17 +++++++++++++++
11 files changed, 131 insertions(+)
create mode 100644 arch/riscv/include/asm/evl/calibration.h
create mode 100644 arch/riscv/include/asm/evl/fptest.h
create mode 100644 arch/riscv/include/asm/evl/syscall.h
create mode 100644 arch/riscv/include/asm/evl/thread.h
create mode 100644 arch/riscv/include/dovetail/irq.h
create mode 100644 arch/riscv/include/dovetail/mm_info.h
create mode 100644 arch/riscv/include/dovetail/netdevice.h
create mode 100644 arch/riscv/include/dovetail/poll.h
create mode 100644 arch/riscv/include/dovetail/thread_info.h
create mode 100644 arch/riscv/include/uapi/asm/evl/fptest.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 11c1f93e6f9d..48468abae599 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -137,6 +137,7 @@ config RISCV
select HAVE_ARCH_VMAP_STACK if MMU && 64BIT
select HAVE_IRQ_PIPELINE
select HAVE_DOVETAIL
+ select HAVE_ARCH_EVL
select HAVE_ASM_MODVERSIONS
select HAVE_CONTEXT_TRACKING_USER
select HAVE_DEBUG_KMEMLEAK
@@ -373,6 +374,7 @@ config AS_HAS_OPTION_ARCH
source "arch/riscv/Kconfig.socs"
source "arch/riscv/Kconfig.errata"
source "kernel/Kconfig.dovetail"
+source "kernel/Kconfig.evl"
menu "Platform type"
diff --git a/arch/riscv/include/asm/evl/calibration.h b/arch/riscv/include/asm/evl/calibration.h
new file mode 100644
index 000000000000..4da81f33ce3c
--- /dev/null
+++ b/arch/riscv/include/asm/evl/calibration.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _EVL_RISCV_ASM_CALIBRATION_H
+#define _EVL_RISCV_ASM_CALIBRATION_H
+
+#include <linux/kconfig.h>
+
+static inline unsigned int evl_get_default_clock_gravity(void)
+{
+ return IS_ENABLED(CONFIG_SMP) ? 6000 : 3000;
+}
+
+#endif /* !_EVL_RISCV_ASM_CALIBRATION_H */
diff --git a/arch/riscv/include/asm/evl/fptest.h b/arch/riscv/include/asm/evl/fptest.h
new file mode 100644
index 000000000000..987246edac69
--- /dev/null
+++ b/arch/riscv/include/asm/evl/fptest.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _EVL_RISCV_ASM_FPTEST_H
+#define _EVL_RISCV_ASM_FPTEST_H
+
+#include <linux/cpufeature.h>
+#include <uapi/asm/evl/fptest.h>
+
+static inline bool evl_begin_fpu(void)
+{
+ return false;
+}
+
+static inline void evl_end_fpu(void) { }
+
+static inline u32 evl_detect_fpu(void)
+{
+ u32 features = 0;
+
+ /* TODO: Check if we have any FPU features. Not using any for now. */
+
+ return features;
+}
+
+#endif /* _EVL_RISCV_ASM_FPTEST_H */
diff --git a/arch/riscv/include/asm/evl/syscall.h b/arch/riscv/include/asm/evl/syscall.h
new file mode 100644
index 000000000000..0a4f8e55ff51
--- /dev/null
+++ b/arch/riscv/include/asm/evl/syscall.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _EVL_RISC_ASM_SYSCALL_H
+#define _EVL_RISC_ASM_SYSCALL_H
+
+#include <linux/uaccess.h>
+#include <asm/unistd.h>
+#include <asm/ptrace.h>
+#include <asm/syscall.h>
+#include <uapi/asm-generic/dovetail.h>
+
+#define raw_put_user(src, dst) __put_user(src, dst)
+#define raw_get_user(dst, src) __get_user(dst, src)
+
+static inline bool
+is_valid_inband_syscall(unsigned int nr)
+{
+ return nr < NR_syscalls;
+}
+
+static inline bool is_compat_oob_call(void)
+{
+ return false;
+}
+
+#endif /* !_EVL_RISC_ASM_SYSCALL_H */
\ No newline at end of file
diff --git a/arch/riscv/include/asm/evl/thread.h b/arch/riscv/include/asm/evl/thread.h
new file mode 100644
index 000000000000..70a07d5bfdbb
--- /dev/null
+++ b/arch/riscv/include/asm/evl/thread.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _EVL_RISCV_ASM_THREAD_H
+#define _EVL_RISCV_ASM_THREAD_H
+
+#include <asm/csr.h>
+
+static inline bool evl_is_breakpoint(int trapnr)
+{
+ return trapnr == EXC_BREAKPOINT;
+}
+
+#endif /* !_EVL_RISCV_ASM_THREAD_H */
diff --git a/arch/riscv/include/dovetail/irq.h b/arch/riscv/include/dovetail/irq.h
new file mode 100644
index 000000000000..f214e2f6ee2b
--- /dev/null
+++ b/arch/riscv/include/dovetail/irq.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _EVL_DOVETAIL_IRQ_H
+#define _EVL_DOVETAIL_IRQ_H
+
+#ifdef CONFIG_EVL
+#include <asm-generic/evl/irq.h>
+#else
+#include_next <dovetail/irq.h>
+#endif
+
+#endif /* !_EVL_DOVETAIL_IRQ_H */
diff --git a/arch/riscv/include/dovetail/mm_info.h b/arch/riscv/include/dovetail/mm_info.h
new file mode 100644
index 000000000000..13087687d61a
--- /dev/null
+++ b/arch/riscv/include/dovetail/mm_info.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _EVL_DOVETAIL_MM_INFO_H
+#define _EVL_DOVETAIL_MM_INFO_H
+
+#include <asm-generic/evl/mm_info.h>
+
+#endif /* !_EVL_DOVETAIL_MM_INFO_H */
diff --git a/arch/riscv/include/dovetail/netdevice.h b/arch/riscv/include/dovetail/netdevice.h
new file mode 100644
index 000000000000..bc7ac6769530
--- /dev/null
+++ b/arch/riscv/include/dovetail/netdevice.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _EVL_DOVETAIL_NETDEVICE_H
+#define _EVL_DOVETAIL_NETDEVICE_H
+
+#include <asm-generic/evl/netdevice.h>
+
+#endif /* !_EVL_DOVETAIL_NETDEVICE_H */
diff --git a/arch/riscv/include/dovetail/poll.h b/arch/riscv/include/dovetail/poll.h
new file mode 100644
index 000000000000..76e51be38a40
--- /dev/null
+++ b/arch/riscv/include/dovetail/poll.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _EVL_DOVETAIL_POLL_H
+#define _EVL_DOVETAIL_POLL_H
+
+#include <asm-generic/evl/poll.h>
+
+#endif /* !_EVL_DOVETAIL_POLL_H */
diff --git a/arch/riscv/include/dovetail/thread_info.h b/arch/riscv/include/dovetail/thread_info.h
new file mode 100644
index 000000000000..4253b13fe47f
--- /dev/null
+++ b/arch/riscv/include/dovetail/thread_info.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _EVL_DOVETAIL_THREAD_INFO_H
+#define _EVL_DOVETAIL_THREAD_INFO_H
+
+#include <asm-generic/evl/thread_info.h>
+
+#endif /* !_EVL_DOVETAIL_THREAD_INFO_H */
diff --git a/arch/riscv/include/uapi/asm/evl/fptest.h b/arch/riscv/include/uapi/asm/evl/fptest.h
new file mode 100644
index 000000000000..9169fc5c1b50
--- /dev/null
+++ b/arch/riscv/include/uapi/asm/evl/fptest.h
@@ -0,0 +1,17 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2024 Tobias Schaffner <tobias.schaffner@siemens.com>.
+ */
+#ifndef _EVL_RISCV_ASM_UAPI_FPTEST_H
+#define _EVL_RISCV_ASM_UAPI_FPTEST_H
+
+#include <linux/types.h>
+
+#define evl_riscv_fp 0x1
+
+/* TODO: Implement fptest */
+#define evl_set_fpregs(__features, __val)
+#define evl_check_fpregs(__features, __val, __bad) 0
+
+#endif /* !_EVL_RISCV_ASM_UAPI_FPTEST_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/2] riscv: Add FPU register test support
2025-10-10 10:10 [PATCH linux-evl 0/2] Add RISC-V support to EVL Tobias Schaffner
2025-10-10 10:10 ` [PATCH 1/2] riscv: Add EVL core Tobias Schaffner
@ 2025-10-10 10:10 ` Tobias Schaffner
2026-07-07 22:30 ` [PATCH linux-evl 0/2] Add RISC-V support to EVL Florian Bezdeka
2 siblings, 0 replies; 14+ messages in thread
From: Tobias Schaffner @ 2025-10-10 10:10 UTC (permalink / raw)
To: xenomai; +Cc: rpm, shannmu, Tobias Schaffner
From: shannmu <shanmu1901@gmail.com>
Define evl_set_fpregs() and evl_check_fpregs(), allowing low-level
manipulation and validation of FPU register state.
Signed-off-by: Tobias Schaffner <tobias.schaffner@siemens.com>
---
arch/riscv/include/asm/evl/fptest.h | 13 ++-
arch/riscv/include/uapi/asm/evl/fptest.h | 133 ++++++++++++++++++++++-
2 files changed, 137 insertions(+), 9 deletions(-)
diff --git a/arch/riscv/include/asm/evl/fptest.h b/arch/riscv/include/asm/evl/fptest.h
index 987246edac69..82394f733c4f 100644
--- a/arch/riscv/include/asm/evl/fptest.h
+++ b/arch/riscv/include/asm/evl/fptest.h
@@ -3,20 +3,27 @@
#define _EVL_RISCV_ASM_FPTEST_H
#include <linux/cpufeature.h>
+#include <asm/fpu.h>
#include <uapi/asm/evl/fptest.h>
static inline bool evl_begin_fpu(void)
{
- return false;
+ kernel_fpu_begin();
+
+ return true;
}
-static inline void evl_end_fpu(void) { }
+static inline void evl_end_fpu(void)
+{
+ kernel_fpu_end();
+}
static inline u32 evl_detect_fpu(void)
{
u32 features = 0;
- /* TODO: Check if we have any FPU features. Not using any for now. */
+ if (has_fpu())
+ return features |= evl_riscv_fpsimd;
return features;
}
diff --git a/arch/riscv/include/uapi/asm/evl/fptest.h b/arch/riscv/include/uapi/asm/evl/fptest.h
index 9169fc5c1b50..7be41bc4e453 100644
--- a/arch/riscv/include/uapi/asm/evl/fptest.h
+++ b/arch/riscv/include/uapi/asm/evl/fptest.h
@@ -1,17 +1,138 @@
/*
- * SPDX-License-Identifier: GPL-2.0
+ * SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
*
- * Copyright (C) 2024 Tobias Schaffner <tobias.schaffner@siemens.com>.
+ * Derived from Xenomai Cobalt, https://xenomai.org/
+ * Copyright (C) 2006 Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org>.
*/
#ifndef _EVL_RISCV_ASM_UAPI_FPTEST_H
#define _EVL_RISCV_ASM_UAPI_FPTEST_H
#include <linux/types.h>
-#define evl_riscv_fp 0x1
+#define evl_riscv_fpsimd 0x1
+#define evl_riscv_sve 0x2
-/* TODO: Implement fptest */
-#define evl_set_fpregs(__features, __val)
-#define evl_check_fpregs(__features, __val, __bad) 0
+/*
+ * CAUTION: keep this code strictly inlined in macros: we don't want
+ * GCC to apply any callee-saved logic to fpsimd registers in
+ * evl_set_fpregs() before evl_check_fpregs() can verify their
+ * contents, but we still want GCC to know about the registers we have
+ * clobbered.
+ */
+
+#define evl_set_fpregs(__features, __val) \
+ do { \
+ unsigned int __i; \
+ __u64 __e[32]; \
+ \
+ if (__features & evl_riscv_fpsimd) { \
+ for (__i = 0; __i < 32; __i++) \
+ __e[__i] = (__val); \
+ __asm__ __volatile__( \
+ ".option push\n" \
+ ".option arch, +d\n" \
+ "fld f0, 0(%0) \n" \
+ "fld f1, 8(%0) \n" \
+ "fld f2, 16(%0) \n" \
+ "fld f3, 24(%0) \n" \
+ "fld f4, 32(%0) \n" \
+ "fld f5, 40(%0) \n" \
+ "fld f6, 48(%0) \n" \
+ "fld f7, 56(%0) \n" \
+ "fld f8, 64(%0) \n" \
+ "fld f9, 72(%0) \n" \
+ "fld f10, 80(%0) \n" \
+ "fld f11, 88(%0) \n" \
+ "fld f12, 96(%0) \n" \
+ "fld f13, 104(%0) \n" \
+ "fld f14, 112(%0) \n" \
+ "fld f15, 120(%0) \n" \
+ "fld f16, 128(%0) \n" \
+ "fld f17, 136(%0) \n" \
+ "fld f18, 144(%0) \n" \
+ "fld f19, 152(%0) \n" \
+ "fld f20, 160(%0) \n" \
+ "fld f21, 168(%0) \n" \
+ "fld f22, 176(%0) \n" \
+ "fld f23, 184(%0) \n" \
+ "fld f24, 192(%0) \n" \
+ "fld f25, 200(%0) \n" \
+ "fld f26, 208(%0) \n" \
+ "fld f27, 216(%0) \n" \
+ "fld f28, 224(%0) \n" \
+ "fld f29, 232(%0) \n" \
+ "fld f30, 240(%0) \n" \
+ "fld f31, 248(%0) \n" \
+ : /* No outputs. */ \
+ : "r"(&__e[0]) \
+ : "f0", "f1", "f2", "f3", "f4", "f5", \
+ "f6", "f7", "f8", "f9", "f10", "f11", \
+ "f12", "f13", "f14", "f15", "f16", \
+ "f17", "f18", "f19", "f20", "f21", \
+ "f22", "f23", "f24", "f25", "f26", \
+ "f27", "f28", "f29", "f30", "f31", \
+ "memory"); \
+ } \
+ } while (0)
+
+
+#define evl_check_fpregs(__features, __val, __bad) \
+ ({ \
+ unsigned int __result = (__val), __i; \
+ __u64 __e[32]; \
+ \
+ if (__features & evl_riscv_fpsimd) { \
+ for (__i = 0; __i < 32; __i++) \
+ __e[__i] = __val; \
+ \
+ __asm__ __volatile__( \
+ ".option push\n" \
+ ".option arch, +d\n" \
+ "fsd f0, 0(%0) \n" \
+ "fsd f1, 8(%0) \n" \
+ "fsd f2, 16(%0) \n" \
+ "fsd f3, 24(%0) \n" \
+ "fsd f4, 32(%0) \n" \
+ "fsd f5, 40(%0) \n" \
+ "fsd f6, 48(%0) \n" \
+ "fsd f7, 56(%0) \n" \
+ "fsd f8, 64(%0) \n" \
+ "fsd f9, 72(%0) \n" \
+ "fsd f10, 80(%0) \n" \
+ "fsd f11, 88(%0) \n" \
+ "fsd f12, 96(%0) \n" \
+ "fsd f13, 104(%0)\n" \
+ "fsd f14, 112(%0)\n" \
+ "fsd f15, 120(%0)\n" \
+ "fsd f16, 128(%0)\n" \
+ "fsd f17, 136(%0)\n" \
+ "fsd f18, 144(%0)\n" \
+ "fsd f19, 152(%0)\n" \
+ "fsd f20, 160(%0)\n" \
+ "fsd f21, 168(%0)\n" \
+ "fsd f22, 176(%0)\n" \
+ "fsd f23, 184(%0)\n" \
+ "fsd f24, 192(%0)\n" \
+ "fsd f25, 200(%0)\n" \
+ "fsd f26, 208(%0)\n" \
+ "fsd f27, 216(%0)\n" \
+ "fsd f28, 224(%0)\n" \
+ "fsd f29, 232(%0)\n" \
+ "fsd f30, 240(%0)\n" \
+ "fsd f31, 248(%0)\n" \
+ : /* No outputs */ \
+ : "r"(&__e[0]) \
+ : "memory"); \
+ \
+ for (__i = 0; __i < 32; __i++) { \
+ if (__e[__i] != __val) { \
+ __result = __e[__i]; \
+ (__bad) = __i; \
+ break; \
+ } \
+ } \
+ } \
+ __result; \
+ })
#endif /* !_EVL_RISCV_ASM_UAPI_FPTEST_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH linux-evl 0/2] Add RISC-V support to EVL
2025-10-10 10:10 [PATCH linux-evl 0/2] Add RISC-V support to EVL Tobias Schaffner
2025-10-10 10:10 ` [PATCH 1/2] riscv: Add EVL core Tobias Schaffner
2025-10-10 10:10 ` [PATCH 2/2] riscv: Add FPU register test support Tobias Schaffner
@ 2026-07-07 22:30 ` Florian Bezdeka
2026-07-08 5:17 ` Tobias Schaffner
2 siblings, 1 reply; 14+ messages in thread
From: Florian Bezdeka @ 2026-07-07 22:30 UTC (permalink / raw)
To: Tobias Schaffner, Philippe Gerum; +Cc: xenomai
On Fri, 2025-10-10 at 12:10 +0200, Tobias Schaffner wrote:
> Hi all,
>
> this series introduces an initial EVL port for RISC-V.
>
> While some tests are still failing, I’d like to share this early
> version with the community to gather feedback, reviews, and hopefully
> some assistance in refining the port.
>
> The patches have been tested in combination with the Dovetail RISC-V
> port on top of v6.12-evl1-rebase.
>
> Looking forward to your feedback and suggestions.
>
I tried to apply this series today, and run into the following issues
reported by my tooling.
Patch 1 is fine, patch 2 has some checkpatch findings.
A couple of debatable warnings like:
WARNING: Misplaced SPDX-License-Identifier tag - use line 1 instead
#58: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:2:
+ * SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
WARNING: unnecessary whitespace before a quoted newline
#95: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:34:
+
In addition to a serious one:
ERROR: Missing Signed-off-by: line by nominal patch author 'shannmu
<shanmu1901@gmail.com>'
My perspective: We definitely need that.
Best regards,
Florian
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH linux-evl 0/2] Add RISC-V support to EVL
2026-07-07 22:30 ` [PATCH linux-evl 0/2] Add RISC-V support to EVL Florian Bezdeka
@ 2026-07-08 5:17 ` Tobias Schaffner
2026-07-08 6:07 ` Jan Kiszka
0 siblings, 1 reply; 14+ messages in thread
From: Tobias Schaffner @ 2026-07-08 5:17 UTC (permalink / raw)
To: Florian Bezdeka, Philippe Gerum; +Cc: xenomai
On 7/8/26 00:30, Florian Bezdeka wrote:
> On Fri, 2025-10-10 at 12:10 +0200, Tobias Schaffner wrote:
>> Hi all,
>>
>> this series introduces an initial EVL port for RISC-V.
>>
>> While some tests are still failing, I’d like to share this early
>> version with the community to gather feedback, reviews, and hopefully
>> some assistance in refining the port.
>>
>> The patches have been tested in combination with the Dovetail RISC-V
>> port on top of v6.12-evl1-rebase.
>>
>> Looking forward to your feedback and suggestions.
>>
>
> I tried to apply this series today, and run into the following issues
> reported by my tooling.
>
> Patch 1 is fine, patch 2 has some checkpatch findings.
>
> A couple of debatable warnings like:
>
> WARNING: Misplaced SPDX-License-Identifier tag - use line 1 instead
> #58: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:2:
> + * SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
>
> WARNING: unnecessary whitespace before a quoted newline
> #95: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:34:
> +
>
> In addition to a serious one:
>
> ERROR: Missing Signed-off-by: line by nominal patch author 'shannmu
> <shanmu1901@gmail.com>'
I did not get any responses from this email anymore. I can try to reach
out to him one last time, but what do we do about it if he will not
reply?
> My perspective: We definitely need that.
>
> Best regards,
> Florian
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH linux-evl 0/2] Add RISC-V support to EVL
2026-07-08 5:17 ` Tobias Schaffner
@ 2026-07-08 6:07 ` Jan Kiszka
2026-07-08 6:26 ` Tobias Schaffner
0 siblings, 1 reply; 14+ messages in thread
From: Jan Kiszka @ 2026-07-08 6:07 UTC (permalink / raw)
To: Tobias Schaffner, Florian Bezdeka, Philippe Gerum; +Cc: xenomai
On 08.07.26 07:17, Tobias Schaffner wrote:
> On 7/8/26 00:30, Florian Bezdeka wrote:
>> On Fri, 2025-10-10 at 12:10 +0200, Tobias Schaffner wrote:
>>> Hi all,
>>>
>>> this series introduces an initial EVL port for RISC-V.
>>>
>>> While some tests are still failing, I’d like to share this early
>>> version with the community to gather feedback, reviews, and hopefully
>>> some assistance in refining the port.
>>>
>>> The patches have been tested in combination with the Dovetail RISC-V
>>> port on top of v6.12-evl1-rebase.
>>>
>>> Looking forward to your feedback and suggestions.
>>>
>>
>> I tried to apply this series today, and run into the following issues
>> reported by my tooling.
>>
>> Patch 1 is fine, patch 2 has some checkpatch findings.
>>
>> A couple of debatable warnings like:
>>
>> WARNING: Misplaced SPDX-License-Identifier tag - use line 1 instead
>> #58: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:2:
>> + * SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
>>
>> WARNING: unnecessary whitespace before a quoted newline
>> #95: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:34:
>> +
>>
>> In addition to a serious one:
>>
>> ERROR: Missing Signed-off-by: line by nominal patch author 'shannmu
>> <shanmu1901@gmail.com>'
>
> I did not get any responses from this email anymore. I can try to reach
> out to him one last time, but what do we do about it if he will not
> reply?
>
If I read that patch correctly, it's majority is taken from the
corresponding Xenomai 3 logic. How much is unique contribution, how much
was your work, Tobias?
Jan
>> My perspective: We definitely need that.
>>
>> Best regards,
>> Florian
>
>
--
Siemens AG, Foundational Technologies
Linux Expert Center
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH linux-evl 0/2] Add RISC-V support to EVL
2026-07-08 6:07 ` Jan Kiszka
@ 2026-07-08 6:26 ` Tobias Schaffner
2026-07-08 6:33 ` Tobias Schaffner
2026-07-08 7:23 ` Jan Kiszka
0 siblings, 2 replies; 14+ messages in thread
From: Tobias Schaffner @ 2026-07-08 6:26 UTC (permalink / raw)
To: Jan Kiszka, Florian Bezdeka, Philippe Gerum; +Cc: xenomai
On 7/8/26 08:07, Jan Kiszka wrote:
> On 08.07.26 07:17, Tobias Schaffner wrote:
>> On 7/8/26 00:30, Florian Bezdeka wrote:
>>> On Fri, 2025-10-10 at 12:10 +0200, Tobias Schaffner wrote:
>>>> Hi all,
>>>>
>>>> this series introduces an initial EVL port for RISC-V.
>>>>
>>>> While some tests are still failing, I’d like to share this early
>>>> version with the community to gather feedback, reviews, and hopefully
>>>> some assistance in refining the port.
>>>>
>>>> The patches have been tested in combination with the Dovetail RISC-V
>>>> port on top of v6.12-evl1-rebase.
>>>>
>>>> Looking forward to your feedback and suggestions.
>>>>
>>>
>>> I tried to apply this series today, and run into the following issues
>>> reported by my tooling.
>>>
>>> Patch 1 is fine, patch 2 has some checkpatch findings.
>>>
>>> A couple of debatable warnings like:
>>>
>>> WARNING: Misplaced SPDX-License-Identifier tag - use line 1 instead
>>> #58: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:2:
>>> + * SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
>>>
>>> WARNING: unnecessary whitespace before a quoted newline
>>> #95: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:34:
>>> +
>>>
>>> In addition to a serious one:
>>>
>>> ERROR: Missing Signed-off-by: line by nominal patch author 'shannmu
>>> <shanmu1901@gmail.com>'
>>
>> I did not get any responses from this email anymore. I can try to reach
>> out to him one last time, but what do we do about it if he will not
>> reply?
>>
>
> If I read that patch correctly, it's majority is taken from the
> corresponding Xenomai 3 logic. How much is unique contribution, how much
> was your work, Tobias?
I added the evl_set_fpregs/evl_check_fpregs content which is a
translation from what Gilles Chanteperdrix
<gilles.chanteperdrix@xenomai.org> did for the x86 and arm architectures
with some isa enablement bits added.
This should be the initial version by shanmu where I added this on top:
https://github.com/shannmu/linux/blob/xenomai4/wip/dovetail-riscv/evl_port/arch/riscv/include/asm/evl/fptest.h
Best,
Tobias
> Jan
>
>>> My perspective: We definitely need that.
>>>
>>> Best regards,
>>> Florian
>>
>>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH linux-evl 0/2] Add RISC-V support to EVL
2026-07-08 6:26 ` Tobias Schaffner
@ 2026-07-08 6:33 ` Tobias Schaffner
2026-07-08 7:23 ` Jan Kiszka
1 sibling, 0 replies; 14+ messages in thread
From: Tobias Schaffner @ 2026-07-08 6:33 UTC (permalink / raw)
To: Jan Kiszka, Florian Bezdeka, Philippe Gerum; +Cc: xenomai
On 7/8/26 08:26, Tobias Schaffner wrote:
>
>
> On 7/8/26 08:07, Jan Kiszka wrote:
>> On 08.07.26 07:17, Tobias Schaffner wrote:
>>> On 7/8/26 00:30, Florian Bezdeka wrote:
>>>> On Fri, 2025-10-10 at 12:10 +0200, Tobias Schaffner wrote:
>>>>> Hi all,
>>>>>
>>>>> this series introduces an initial EVL port for RISC-V.
>>>>>
>>>>> While some tests are still failing, I’d like to share this early
>>>>> version with the community to gather feedback, reviews, and hopefully
>>>>> some assistance in refining the port.
>>>>>
>>>>> The patches have been tested in combination with the Dovetail RISC-V
>>>>> port on top of v6.12-evl1-rebase.
>>>>>
>>>>> Looking forward to your feedback and suggestions.
>>>>>
>>>>
>>>> I tried to apply this series today, and run into the following issues
>>>> reported by my tooling.
>>>>
>>>> Patch 1 is fine, patch 2 has some checkpatch findings.
>>>>
>>>> A couple of debatable warnings like:
>>>>
>>>> WARNING: Misplaced SPDX-License-Identifier tag - use line 1 instead
>>>> #58: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:2:
>>>> + * SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
>>>>
>>>> WARNING: unnecessary whitespace before a quoted newline
>>>> #95: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:34:
>>>> +
>>>>
>>>> In addition to a serious one:
>>>>
>>>> ERROR: Missing Signed-off-by: line by nominal patch author 'shannmu
>>>> <shanmu1901@gmail.com>'
>>>
>>> I did not get any responses from this email anymore. I can try to reach
>>> out to him one last time, but what do we do about it if he will not
>>> reply?
>>>
>>
>> If I read that patch correctly, it's majority is taken from the
>> corresponding Xenomai 3 logic. How much is unique contribution, how much
>> was your work, Tobias?
>
> I added the evl_set_fpregs/evl_check_fpregs content which is a
> translation from what Gilles Chanteperdrix
> <gilles.chanteperdrix@xenomai.org> did for the x86 and arm architectures
> with some isa enablement bits added.
>
> This should be the initial version by shanmu where I added this on top:
> https://github.com/shannmu/linux/blob/xenomai4/wip/dovetail-riscv/
> evl_port/arch/riscv/include/asm/evl/fptest.h
>
> Best,
> Tobias
PS: We have the same issue for:
https://lore.kernel.org/xenomai/20251009125736.3520623-1-tobias.schaffner@siemens.com/
>
>> Jan
>>
>>>> My perspective: We definitely need that.
>>>>
>>>> Best regards,
>>>> Florian
>>>
>>>
>>
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH linux-evl 0/2] Add RISC-V support to EVL
2026-07-08 6:26 ` Tobias Schaffner
2026-07-08 6:33 ` Tobias Schaffner
@ 2026-07-08 7:23 ` Jan Kiszka
2026-07-08 8:55 ` Philippe Gerum
1 sibling, 1 reply; 14+ messages in thread
From: Jan Kiszka @ 2026-07-08 7:23 UTC (permalink / raw)
To: Tobias Schaffner, Florian Bezdeka, Philippe Gerum; +Cc: xenomai
On 08.07.26 08:26, Tobias Schaffner wrote:
>
>
> On 7/8/26 08:07, Jan Kiszka wrote:
>> On 08.07.26 07:17, Tobias Schaffner wrote:
>>> On 7/8/26 00:30, Florian Bezdeka wrote:
>>>> On Fri, 2025-10-10 at 12:10 +0200, Tobias Schaffner wrote:
>>>>> Hi all,
>>>>>
>>>>> this series introduces an initial EVL port for RISC-V.
>>>>>
>>>>> While some tests are still failing, I’d like to share this early
>>>>> version with the community to gather feedback, reviews, and hopefully
>>>>> some assistance in refining the port.
>>>>>
>>>>> The patches have been tested in combination with the Dovetail RISC-V
>>>>> port on top of v6.12-evl1-rebase.
>>>>>
>>>>> Looking forward to your feedback and suggestions.
>>>>>
>>>>
>>>> I tried to apply this series today, and run into the following issues
>>>> reported by my tooling.
>>>>
>>>> Patch 1 is fine, patch 2 has some checkpatch findings.
>>>>
>>>> A couple of debatable warnings like:
>>>>
>>>> WARNING: Misplaced SPDX-License-Identifier tag - use line 1 instead
>>>> #58: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:2:
>>>> + * SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
>>>>
>>>> WARNING: unnecessary whitespace before a quoted newline
>>>> #95: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:34:
>>>> +
>>>>
>>>> In addition to a serious one:
>>>>
>>>> ERROR: Missing Signed-off-by: line by nominal patch author 'shannmu
>>>> <shanmu1901@gmail.com>'
>>>
>>> I did not get any responses from this email anymore. I can try to reach
>>> out to him one last time, but what do we do about it if he will not
>>> reply?
>>>
>>
>> If I read that patch correctly, it's majority is taken from the
>> corresponding Xenomai 3 logic. How much is unique contribution, how much
>> was your work, Tobias?
>
> I added the evl_set_fpregs/evl_check_fpregs content which is a
> translation from what Gilles Chanteperdrix
> <gilles.chanteperdrix@xenomai.org> did for the x86 and arm architectures
> with some isa enablement bits added.
>
> This should be the initial version by shanmu where I added this on top:
> https://github.com/shannmu/linux/blob/xenomai4/wip/dovetail-riscv/
> evl_port/arch/riscv/include/asm/evl/fptest.h
>
At least for this patch, I think it would be fair to claim authorship
for the final one and only refer to shanmu as provider of a baseline.
Jan
--
Siemens AG, Foundational Technologies
Linux Expert Center
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH linux-evl 0/2] Add RISC-V support to EVL
2026-07-08 7:23 ` Jan Kiszka
@ 2026-07-08 8:55 ` Philippe Gerum
2026-07-08 9:51 ` Florian Bezdeka
0 siblings, 1 reply; 14+ messages in thread
From: Philippe Gerum @ 2026-07-08 8:55 UTC (permalink / raw)
To: Jan Kiszka; +Cc: Tobias Schaffner, Florian Bezdeka, xenomai
Jan Kiszka <jan.kiszka@siemens.com> writes:
> On 08.07.26 08:26, Tobias Schaffner wrote:
>>
>>
>> On 7/8/26 08:07, Jan Kiszka wrote:
>>> On 08.07.26 07:17, Tobias Schaffner wrote:
>>>> On 7/8/26 00:30, Florian Bezdeka wrote:
>>>>> On Fri, 2025-10-10 at 12:10 +0200, Tobias Schaffner wrote:
>>>>>> Hi all,
>>>>>>
>>>>>> this series introduces an initial EVL port for RISC-V.
>>>>>>
>>>>>> While some tests are still failing, I’d like to share this early
>>>>>> version with the community to gather feedback, reviews, and hopefully
>>>>>> some assistance in refining the port.
>>>>>>
>>>>>> The patches have been tested in combination with the Dovetail RISC-V
>>>>>> port on top of v6.12-evl1-rebase.
>>>>>>
>>>>>> Looking forward to your feedback and suggestions.
>>>>>>
>>>>>
>>>>> I tried to apply this series today, and run into the following issues
>>>>> reported by my tooling.
>>>>>
>>>>> Patch 1 is fine, patch 2 has some checkpatch findings.
>>>>>
>>>>> A couple of debatable warnings like:
>>>>>
>>>>> WARNING: Misplaced SPDX-License-Identifier tag - use line 1 instead
>>>>> #58: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:2:
>>>>> + * SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
>>>>>
>>>>> WARNING: unnecessary whitespace before a quoted newline
>>>>> #95: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:34:
>>>>> +
>>>>>
>>>>> In addition to a serious one:
>>>>>
>>>>> ERROR: Missing Signed-off-by: line by nominal patch author 'shannmu
>>>>> <shanmu1901@gmail.com>'
>>>>
>>>> I did not get any responses from this email anymore. I can try to reach
>>>> out to him one last time, but what do we do about it if he will not
>>>> reply?
>>>>
>>>
>>> If I read that patch correctly, it's majority is taken from the
>>> corresponding Xenomai 3 logic. How much is unique contribution, how much
>>> was your work, Tobias?
>>
>> I added the evl_set_fpregs/evl_check_fpregs content which is a
>> translation from what Gilles Chanteperdrix
>> <gilles.chanteperdrix@xenomai.org> did for the x86 and arm architectures
>> with some isa enablement bits added.
>>
>> This should be the initial version by shanmu where I added this on top:
>> https://github.com/shannmu/linux/blob/xenomai4/wip/dovetail-riscv/
>> evl_port/arch/riscv/include/asm/evl/fptest.h
>>
>
> At least for this patch, I think it would be fair to claim authorship
> for the final one and only refer to shanmu as provider of a baseline.
>
Agreed. This is a trivial adaptation of the pre-existing
arch/arm*/include/asm/evl/fptest.h, which is in and of itself
boilerplate code.
--
Philippe.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH linux-evl 0/2] Add RISC-V support to EVL
2026-07-08 8:55 ` Philippe Gerum
@ 2026-07-08 9:51 ` Florian Bezdeka
2026-07-08 15:32 ` Jan Kiszka
0 siblings, 1 reply; 14+ messages in thread
From: Florian Bezdeka @ 2026-07-08 9:51 UTC (permalink / raw)
To: Philippe Gerum; +Cc: Tobias Schaffner, xenomai, Jan Kiszka
On Wed, 2026-07-08 at 10:55 +0200, Philippe Gerum wrote:
> Jan Kiszka <jan.kiszka@siemens.com> writes:
>
> > On 08.07.26 08:26, Tobias Schaffner wrote:
> > >
> > >
> > > On 7/8/26 08:07, Jan Kiszka wrote:
> > > > On 08.07.26 07:17, Tobias Schaffner wrote:
> > > > > On 7/8/26 00:30, Florian Bezdeka wrote:
> > > > > > On Fri, 2025-10-10 at 12:10 +0200, Tobias Schaffner wrote:
> > > > > > > Hi all,
> > > > > > >
> > > > > > > this series introduces an initial EVL port for RISC-V.
> > > > > > >
> > > > > > > While some tests are still failing, I’d like to share this early
> > > > > > > version with the community to gather feedback, reviews, and hopefully
> > > > > > > some assistance in refining the port.
> > > > > > >
> > > > > > > The patches have been tested in combination with the Dovetail RISC-V
> > > > > > > port on top of v6.12-evl1-rebase.
> > > > > > >
> > > > > > > Looking forward to your feedback and suggestions.
> > > > > > >
> > > > > >
> > > > > > I tried to apply this series today, and run into the following issues
> > > > > > reported by my tooling.
> > > > > >
> > > > > > Patch 1 is fine, patch 2 has some checkpatch findings.
> > > > > >
> > > > > > A couple of debatable warnings like:
> > > > > >
> > > > > > WARNING: Misplaced SPDX-License-Identifier tag - use line 1 instead
> > > > > > #58: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:2:
> > > > > > + * SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
> > > > > >
> > > > > > WARNING: unnecessary whitespace before a quoted newline
> > > > > > #95: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:34:
> > > > > > +
> > > > > >
> > > > > > In addition to a serious one:
> > > > > >
> > > > > > ERROR: Missing Signed-off-by: line by nominal patch author 'shannmu
> > > > > > <shanmu1901@gmail.com>'
> > > > >
> > > > > I did not get any responses from this email anymore. I can try to reach
> > > > > out to him one last time, but what do we do about it if he will not
> > > > > reply?
> > > > >
> > > >
> > > > If I read that patch correctly, it's majority is taken from the
> > > > corresponding Xenomai 3 logic. How much is unique contribution, how much
> > > > was your work, Tobias?
> > >
> > > I added the evl_set_fpregs/evl_check_fpregs content which is a
> > > translation from what Gilles Chanteperdrix
> > > <gilles.chanteperdrix@xenomai.org> did for the x86 and arm architectures
> > > with some isa enablement bits added.
> > >
> > > This should be the initial version by shanmu where I added this on top:
> > > https://github.com/shannmu/linux/blob/xenomai4/wip/dovetail-riscv/
> > > evl_port/arch/riscv/include/asm/evl/fptest.h
> > >
> >
> > At least for this patch, I think it would be fair to claim authorship
> > for the final one and only refer to shanmu as provider of a baseline.
> >
>
> Agreed. This is a trivial adaptation of the pre-existing
> arch/arm*/include/asm/evl/fptest.h, which is in and of itself
> boilerplate code.
>
We had a short chat about this topic in the Xenomai community call
today. To avoid further delay of the dovetail 7.1 release we decided
that we will move out the risc-v series again.
Tobias will use the time to clarify a couple of those co-author and
signed-off topics. Each series (dovetail, evl, libevl) seems to have
those issues.
We will have to wait for a reply for some time, but we hope to address
those issues within the 7.2 cycle.
Evl and Dovetail v7.1-rebase branches should be up to date now.
Florian
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH linux-evl 0/2] Add RISC-V support to EVL
2026-07-08 9:51 ` Florian Bezdeka
@ 2026-07-08 15:32 ` Jan Kiszka
2026-07-08 15:54 ` Florian Bezdeka
2026-07-08 15:58 ` Tobias Schaffner
0 siblings, 2 replies; 14+ messages in thread
From: Jan Kiszka @ 2026-07-08 15:32 UTC (permalink / raw)
To: Florian Bezdeka, Philippe Gerum; +Cc: Tobias Schaffner, xenomai
On 08.07.26 11:51, Florian Bezdeka wrote:
> On Wed, 2026-07-08 at 10:55 +0200, Philippe Gerum wrote:
>> Jan Kiszka <jan.kiszka@siemens.com> writes:
>>
>>> On 08.07.26 08:26, Tobias Schaffner wrote:
>>>>
>>>>
>>>> On 7/8/26 08:07, Jan Kiszka wrote:
>>>>> On 08.07.26 07:17, Tobias Schaffner wrote:
>>>>>> On 7/8/26 00:30, Florian Bezdeka wrote:
>>>>>>> On Fri, 2025-10-10 at 12:10 +0200, Tobias Schaffner wrote:
>>>>>>>> Hi all,
>>>>>>>>
>>>>>>>> this series introduces an initial EVL port for RISC-V.
>>>>>>>>
>>>>>>>> While some tests are still failing, I’d like to share this early
>>>>>>>> version with the community to gather feedback, reviews, and hopefully
>>>>>>>> some assistance in refining the port.
>>>>>>>>
>>>>>>>> The patches have been tested in combination with the Dovetail RISC-V
>>>>>>>> port on top of v6.12-evl1-rebase.
>>>>>>>>
>>>>>>>> Looking forward to your feedback and suggestions.
>>>>>>>>
>>>>>>>
>>>>>>> I tried to apply this series today, and run into the following issues
>>>>>>> reported by my tooling.
>>>>>>>
>>>>>>> Patch 1 is fine, patch 2 has some checkpatch findings.
>>>>>>>
>>>>>>> A couple of debatable warnings like:
>>>>>>>
>>>>>>> WARNING: Misplaced SPDX-License-Identifier tag - use line 1 instead
>>>>>>> #58: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:2:
>>>>>>> + * SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
>>>>>>>
>>>>>>> WARNING: unnecessary whitespace before a quoted newline
>>>>>>> #95: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:34:
>>>>>>> +
>>>>>>>
>>>>>>> In addition to a serious one:
>>>>>>>
>>>>>>> ERROR: Missing Signed-off-by: line by nominal patch author 'shannmu
>>>>>>> <shanmu1901@gmail.com>'
>>>>>>
>>>>>> I did not get any responses from this email anymore. I can try to reach
>>>>>> out to him one last time, but what do we do about it if he will not
>>>>>> reply?
>>>>>>
>>>>>
>>>>> If I read that patch correctly, it's majority is taken from the
>>>>> corresponding Xenomai 3 logic. How much is unique contribution, how much
>>>>> was your work, Tobias?
>>>>
>>>> I added the evl_set_fpregs/evl_check_fpregs content which is a
>>>> translation from what Gilles Chanteperdrix
>>>> <gilles.chanteperdrix@xenomai.org> did for the x86 and arm architectures
>>>> with some isa enablement bits added.
>>>>
>>>> This should be the initial version by shanmu where I added this on top:
>>>> https://github.com/shannmu/linux/blob/xenomai4/wip/dovetail-riscv/
>>>> evl_port/arch/riscv/include/asm/evl/fptest.h
>>>>
>>>
>>> At least for this patch, I think it would be fair to claim authorship
>>> for the final one and only refer to shanmu as provider of a baseline.
>>>
>>
>> Agreed. This is a trivial adaptation of the pre-existing
>> arch/arm*/include/asm/evl/fptest.h, which is in and of itself
>> boilerplate code.
>>
>
> We had a short chat about this topic in the Xenomai community call
> today. To avoid further delay of the dovetail 7.1 release we decided
> that we will move out the risc-v series again.
>
As you already removed wip/flo/v7.1-evl-rebase+riscv (which broke
xenomai-images CI, unfortunately), where will be the new transitional
branch in the meantime?
Jan
> Tobias will use the time to clarify a couple of those co-author and
> signed-off topics. Each series (dovetail, evl, libevl) seems to have
> those issues.
>
> We will have to wait for a reply for some time, but we hope to address
> those issues within the 7.2 cycle.
>
> Evl and Dovetail v7.1-rebase branches should be up to date now.
>
> Florian
--
Siemens AG, Foundational Technologies
Linux Expert Center
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH linux-evl 0/2] Add RISC-V support to EVL
2026-07-08 15:32 ` Jan Kiszka
@ 2026-07-08 15:54 ` Florian Bezdeka
2026-07-08 15:58 ` Tobias Schaffner
1 sibling, 0 replies; 14+ messages in thread
From: Florian Bezdeka @ 2026-07-08 15:54 UTC (permalink / raw)
To: Jan Kiszka, Philippe Gerum; +Cc: Tobias Schaffner, xenomai
On Wed, 2026-07-08 at 17:32 +0200, Jan Kiszka wrote:
> On 08.07.26 11:51, Florian Bezdeka wrote:
> > On Wed, 2026-07-08 at 10:55 +0200, Philippe Gerum wrote:
> > > Jan Kiszka <jan.kiszka@siemens.com> writes:
> > >
> > > > On 08.07.26 08:26, Tobias Schaffner wrote:
> > > > >
> > > > >
> > > > > On 7/8/26 08:07, Jan Kiszka wrote:
> > > > > > On 08.07.26 07:17, Tobias Schaffner wrote:
> > > > > > > On 7/8/26 00:30, Florian Bezdeka wrote:
> > > > > > > > On Fri, 2025-10-10 at 12:10 +0200, Tobias Schaffner wrote:
> > > > > > > > > Hi all,
> > > > > > > > >
> > > > > > > > > this series introduces an initial EVL port for RISC-V.
> > > > > > > > >
> > > > > > > > > While some tests are still failing, I’d like to share this early
> > > > > > > > > version with the community to gather feedback, reviews, and hopefully
> > > > > > > > > some assistance in refining the port.
> > > > > > > > >
> > > > > > > > > The patches have been tested in combination with the Dovetail RISC-V
> > > > > > > > > port on top of v6.12-evl1-rebase.
> > > > > > > > >
> > > > > > > > > Looking forward to your feedback and suggestions.
> > > > > > > > >
> > > > > > > >
> > > > > > > > I tried to apply this series today, and run into the following issues
> > > > > > > > reported by my tooling.
> > > > > > > >
> > > > > > > > Patch 1 is fine, patch 2 has some checkpatch findings.
> > > > > > > >
> > > > > > > > A couple of debatable warnings like:
> > > > > > > >
> > > > > > > > WARNING: Misplaced SPDX-License-Identifier tag - use line 1 instead
> > > > > > > > #58: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:2:
> > > > > > > > + * SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
> > > > > > > >
> > > > > > > > WARNING: unnecessary whitespace before a quoted newline
> > > > > > > > #95: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:34:
> > > > > > > > +
> > > > > > > >
> > > > > > > > In addition to a serious one:
> > > > > > > >
> > > > > > > > ERROR: Missing Signed-off-by: line by nominal patch author 'shannmu
> > > > > > > > <shanmu1901@gmail.com>'
> > > > > > >
> > > > > > > I did not get any responses from this email anymore. I can try to reach
> > > > > > > out to him one last time, but what do we do about it if he will not
> > > > > > > reply?
> > > > > > >
> > > > > >
> > > > > > If I read that patch correctly, it's majority is taken from the
> > > > > > corresponding Xenomai 3 logic. How much is unique contribution, how much
> > > > > > was your work, Tobias?
> > > > >
> > > > > I added the evl_set_fpregs/evl_check_fpregs content which is a
> > > > > translation from what Gilles Chanteperdrix
> > > > > <gilles.chanteperdrix@xenomai.org> did for the x86 and arm architectures
> > > > > with some isa enablement bits added.
> > > > >
> > > > > This should be the initial version by shanmu where I added this on top:
> > > > > https://github.com/shannmu/linux/blob/xenomai4/wip/dovetail-riscv/
> > > > > evl_port/arch/riscv/include/asm/evl/fptest.h
> > > > >
> > > >
> > > > At least for this patch, I think it would be fair to claim authorship
> > > > for the final one and only refer to shanmu as provider of a baseline.
> > > >
> > >
> > > Agreed. This is a trivial adaptation of the pre-existing
> > > arch/arm*/include/asm/evl/fptest.h, which is in and of itself
> > > boilerplate code.
> > >
> >
> > We had a short chat about this topic in the Xenomai community call
> > today. To avoid further delay of the dovetail 7.1 release we decided
> > that we will move out the risc-v series again.
> >
>
> As you already removed wip/flo/v7.1-evl-rebase+riscv (which broke
> xenomai-images CI, unfortunately), where will be the new transitional
> branch in the meantime?
>
Oh, those temporary branches shouldn't be referenced in public CI
things. If necessary we can bring it back.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH linux-evl 0/2] Add RISC-V support to EVL
2026-07-08 15:32 ` Jan Kiszka
2026-07-08 15:54 ` Florian Bezdeka
@ 2026-07-08 15:58 ` Tobias Schaffner
1 sibling, 0 replies; 14+ messages in thread
From: Tobias Schaffner @ 2026-07-08 15:58 UTC (permalink / raw)
To: Jan Kiszka, Florian Bezdeka, Philippe Gerum; +Cc: xenomai
Hi Jan,
On 7/8/26 17:32, Jan Kiszka wrote:
> On 08.07.26 11:51, Florian Bezdeka wrote:
>> On Wed, 2026-07-08 at 10:55 +0200, Philippe Gerum wrote:
>>> Jan Kiszka <jan.kiszka@siemens.com> writes:
>>>
>>>> On 08.07.26 08:26, Tobias Schaffner wrote:
>>>>>
>>>>>
>>>>> On 7/8/26 08:07, Jan Kiszka wrote:
>>>>>> On 08.07.26 07:17, Tobias Schaffner wrote:
>>>>>>> On 7/8/26 00:30, Florian Bezdeka wrote:
>>>>>>>> On Fri, 2025-10-10 at 12:10 +0200, Tobias Schaffner wrote:
>>>>>>>>> Hi all,
>>>>>>>>>
>>>>>>>>> this series introduces an initial EVL port for RISC-V.
>>>>>>>>>
>>>>>>>>> While some tests are still failing, I’d like to share this early
>>>>>>>>> version with the community to gather feedback, reviews, and hopefully
>>>>>>>>> some assistance in refining the port.
>>>>>>>>>
>>>>>>>>> The patches have been tested in combination with the Dovetail RISC-V
>>>>>>>>> port on top of v6.12-evl1-rebase.
>>>>>>>>>
>>>>>>>>> Looking forward to your feedback and suggestions.
>>>>>>>>>
>>>>>>>>
>>>>>>>> I tried to apply this series today, and run into the following issues
>>>>>>>> reported by my tooling.
>>>>>>>>
>>>>>>>> Patch 1 is fine, patch 2 has some checkpatch findings.
>>>>>>>>
>>>>>>>> A couple of debatable warnings like:
>>>>>>>>
>>>>>>>> WARNING: Misplaced SPDX-License-Identifier tag - use line 1 instead
>>>>>>>> #58: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:2:
>>>>>>>> + * SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
>>>>>>>>
>>>>>>>> WARNING: unnecessary whitespace before a quoted newline
>>>>>>>> #95: FILE: arch/riscv/include/uapi/asm/evl/fptest.h:34:
>>>>>>>> +
>>>>>>>>
>>>>>>>> In addition to a serious one:
>>>>>>>>
>>>>>>>> ERROR: Missing Signed-off-by: line by nominal patch author 'shannmu
>>>>>>>> <shanmu1901@gmail.com>'
>>>>>>>
>>>>>>> I did not get any responses from this email anymore. I can try to reach
>>>>>>> out to him one last time, but what do we do about it if he will not
>>>>>>> reply?
>>>>>>>
>>>>>>
>>>>>> If I read that patch correctly, it's majority is taken from the
>>>>>> corresponding Xenomai 3 logic. How much is unique contribution, how much
>>>>>> was your work, Tobias?
>>>>>
>>>>> I added the evl_set_fpregs/evl_check_fpregs content which is a
>>>>> translation from what Gilles Chanteperdrix
>>>>> <gilles.chanteperdrix@xenomai.org> did for the x86 and arm architectures
>>>>> with some isa enablement bits added.
>>>>>
>>>>> This should be the initial version by shanmu where I added this on top:
>>>>> https://github.com/shannmu/linux/blob/xenomai4/wip/dovetail-riscv/
>>>>> evl_port/arch/riscv/include/asm/evl/fptest.h
>>>>>
>>>>
>>>> At least for this patch, I think it would be fair to claim authorship
>>>> for the final one and only refer to shanmu as provider of a baseline.
>>>>
>>>
>>> Agreed. This is a trivial adaptation of the pre-existing
>>> arch/arm*/include/asm/evl/fptest.h, which is in and of itself
>>> boilerplate code.
>>>
>>
>> We had a short chat about this topic in the Xenomai community call
>> today. To avoid further delay of the dovetail 7.1 release we decided
>> that we will move out the risc-v series again.
>>
>
> As you already removed wip/flo/v7.1-evl-rebase+riscv (which broke
> xenomai-images CI, unfortunately), where will be the new transitional
> branch in the meantime?
This should still stay at wip/evl-riscv imo. That's where I push new
versions as soon as I rebased the evl branch. I will send a patch.
Best,
Tobias
> Jan
>
>> Tobias will use the time to clarify a couple of those co-author and
>> signed-off topics. Each series (dovetail, evl, libevl) seems to have
>> those issues.
>>
>> We will have to wait for a reply for some time, but we hope to address
>> those issues within the 7.2 cycle.
>>
>> Evl and Dovetail v7.1-rebase branches should be up to date now.
>>
>> Florian
>
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2026-07-08 15:58 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-10-10 10:10 [PATCH linux-evl 0/2] Add RISC-V support to EVL Tobias Schaffner
2025-10-10 10:10 ` [PATCH 1/2] riscv: Add EVL core Tobias Schaffner
2025-10-10 10:10 ` [PATCH 2/2] riscv: Add FPU register test support Tobias Schaffner
2026-07-07 22:30 ` [PATCH linux-evl 0/2] Add RISC-V support to EVL Florian Bezdeka
2026-07-08 5:17 ` Tobias Schaffner
2026-07-08 6:07 ` Jan Kiszka
2026-07-08 6:26 ` Tobias Schaffner
2026-07-08 6:33 ` Tobias Schaffner
2026-07-08 7:23 ` Jan Kiszka
2026-07-08 8:55 ` Philippe Gerum
2026-07-08 9:51 ` Florian Bezdeka
2026-07-08 15:32 ` Jan Kiszka
2026-07-08 15:54 ` Florian Bezdeka
2026-07-08 15:58 ` Tobias Schaffner
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