[PATCH v3 00/12] Add explicit clock vote and enable power-domain for QCOM-ICE

[PATCH v3 00/12] Add explicit clock vote and enable power-domain for QCOM-ICE

[Harshal Dev]

When the kernel is booted without the 'clk_ignore_unused' and
'pd_ignore_unused' command‑line flags, votes for unused clocks and power
domains are dropped by the kernel post late_init and deferred probe
timeout. Depending on the relative timing between the ICE probe and the
kernel disabling the unused clocks and power domains occasional unclocked
register accesses or 'stuck' clocks are observed during QCOM‑ICE probe.
When the 'iface' clock is not voted on, unclocked register access would
be observed. On the other hand, if the associated power-domain for ICE
is not enabled, a 'stuck' clock is observed.

This patch series resolves both of these problems by adding explicit
power‑domain enablement and 'iface' clock‑vote handling to the QCOM‑ICE
driver.

The clock 'stuck' issue was first reported on Qualcomm RideSX4 (sa8775p)
platform: https://lore.kernel.org/all/ZZYTYsaNUuWQg3tR@x1/

Issue with unclocked ICE register access is easily reproducible on
on Qualcomm RB3Gen2 (kodiak) platform when 'clk_ignore_unused' is
not passed on the kernel command-line.

This patch series has been validated on: SM8650-MTP, RB3Gen2 and
Lemans-EVK.

Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
---
Changes in v3:
- Dropped "_clk" suffix from clock names in DT binding and sources and ensure
  ICE driver looks for these updated clock names.
- Updated commit message of DT binding change (Patch 1) to explicitly state
  that the change is preserving backward compatibility.
- Introduced new DT binding commit to ensure eliza and milos require the iface
  clock and power-domain.
- Check for IS_ERR() on devm_clk_get_optional_enabled(dev, "iface") return
  value.
- Minor beautification of dev_err() prints as suggested by Konrad.
- Rebased onto latest linux-next tag next-20260316.
- Link to v2: https://lore.kernel.org/r/20260310-qcom_ice_power_and_clk_vote-v2-0-b9c2a5471d9e@oss.qualcomm.com

Changes in v2:
- Updated the DT bindings and ICE driver source to ensure no ABI breaks are
  made in this patch series. A follow-up patch series will mark the clocks
  and power-domain as required to preserve bisectability.
- Added list of allowed clock-names to the DT-binding.
- Added Fixes tag to mark the original regressions and ensure back-porting
  for stable trees.
- Updated the commit messages to explicitly mention the problem of
  potential unclocked register access and stuck clocks during probe.
- Dropped explicit calls to pm_runtime_* APIs from ICE probe, suspend and
  resume.
- Link to v1: https://lore.kernel.org/r/20260123-qcom_ice_power_and_clk_vote-v1-0-e9059776f85c@qti.qualcomm.com

---
Harshal Dev (12):
      dt-bindings: crypto: qcom,ice: Allow power-domain and iface clk
      dt-bindings: crypto: qcom,ice: Require power-domain and iface clk
      arm64: dts: qcom: kaanapali: Add power-domain and iface clk for ice node
      arm64: dts: qcom: lemans: Add power-domain and iface clk for ice node
      arm64: dts: qcom: monaco: Add power-domain and iface clk for ice node
      arm64: dts: qcom: sc7180: Add power-domain and iface clk for ice node
      arm64: dts: qcom: kodiak: Add power-domain and iface clk for ice node
      arm64: dts: qcom: sm8450: Add power-domain and iface clk for ice node
      arm64: dts: qcom: sm8550: Add power-domain and iface clk for ice node
      arm64: dts: qcom: sm8650: Add power-domain and iface clk for ice node
      arm64: dts: qcom: sm8750: Add power-domain and iface clk for ice node
      soc: qcom: ice: Allow explicit votes on 'iface' clock for ICE

 .../bindings/crypto/qcom,inline-crypto-engine.yaml | 35 +++++++++++++++++++++-
 arch/arm64/boot/dts/qcom/kaanapali.dtsi            |  6 +++-
 arch/arm64/boot/dts/qcom/kodiak.dtsi               |  6 +++-
 arch/arm64/boot/dts/qcom/lemans.dtsi               |  6 +++-
 arch/arm64/boot/dts/qcom/monaco.dtsi               |  6 +++-
 arch/arm64/boot/dts/qcom/sc7180.dtsi               |  6 +++-
 arch/arm64/boot/dts/qcom/sm8450.dtsi               |  6 +++-
 arch/arm64/boot/dts/qcom/sm8550.dtsi               |  6 +++-
 arch/arm64/boot/dts/qcom/sm8650.dtsi               |  6 +++-
 arch/arm64/boot/dts/qcom/sm8750.dtsi               |  6 +++-
 drivers/soc/qcom/ice.c                             | 17 +++++++++--
 11 files changed, 94 insertions(+), 12 deletions(-)
---
base-commit: 95c541ddfb0815a0ea8477af778bb13bb075079a
change-id: 20260120-qcom_ice_power_and_clk_vote-769704f5036a

Best regards,
-- 
Harshal Dev <harshal.dev@oss.qualcomm.com>

[PATCH v3 01/12] dt-bindings: crypto: qcom,ice: Allow power-domain and iface clk

[Harshal Dev]

Update the inline-crypto engine DT binding in a backward compatible manner
to allow specifying up to two clocks along with their names and associated
power-domain.

When the 'clk_ignore_unused' flag is not passed on the kernel command line
occasional unclocked ICE hardware register access are observed when the
kernel disables the unused 'iface' clock before ICE can probe. On the other
hand, when the 'pd_ignore_unused' flag is not passed on the command line,
clock 'stuck' issues are observed if the power-domain required by ICE
hardware is unused and thus disabled before ICE probe could happen.

To avoid these scenarios, the 'iface' clock and the associated power-domain
should be specified in the ICE device tree node and enabled by ICE.

Fixes: f6ff91a47ac57 ("dt-bindings: crypto: Add Qualcomm Inline Crypto Engine")
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
---
 .../bindings/crypto/qcom,inline-crypto-engine.yaml       | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
index 876bf90ed96e..99c541e7fa8c 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
@@ -30,6 +30,16 @@ properties:
     maxItems: 1
 
   clocks:
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    minItems: 1
+    items:
+      - const: core
+      - const: iface
+
+  power-domains:
     maxItems: 1
 
   operating-points-v2: true
@@ -52,7 +62,11 @@ examples:
       compatible = "qcom,sm8550-inline-crypto-engine",
                    "qcom,inline-crypto-engine";
       reg = <0x01d88000 0x8000>;
-      clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+      clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+               <&gcc GCC_UFS_PHY_AHB_CLK>;
+      clock-names = "core",
+                    "iface";
+      power-domains = <&gcc UFS_PHY_GDSC>;
 
       operating-points-v2 = <&ice_opp_table>;
 

-- 
2.34.1

Re: [PATCH v3 01/12] dt-bindings: crypto: qcom,ice: Allow power-domain and iface clk

[Dmitry Baryshkov]

On Tue, Mar 17, 2026 at 02:50:40PM +0530, Harshal Dev wrote:
> Update the inline-crypto engine DT binding in a backward compatible manner
> to allow specifying up to two clocks along with their names and associated
> power-domain.

This should come after the "why" part.

> 
> When the 'clk_ignore_unused' flag is not passed on the kernel command line
> occasional unclocked ICE hardware register access are observed when the
> kernel disables the unused 'iface' clock before ICE can probe. On the other
> hand, when the 'pd_ignore_unused' flag is not passed on the command line,
> clock 'stuck' issues are observed if the power-domain required by ICE
> hardware is unused and thus disabled before ICE probe could happen.

You can simply say that ICE requires these clocks and these power
domains to function. Accessing the hardware can fail if they are
disabled by the kernel for whater reasons.

> 
> To avoid these scenarios, the 'iface' clock and the associated power-domain
> should be specified in the ICE device tree node and enabled by ICE.
> 
> Fixes: f6ff91a47ac57 ("dt-bindings: crypto: Add Qualcomm Inline Crypto Engine")
> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
> ---
>  .../bindings/crypto/qcom,inline-crypto-engine.yaml       | 16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
> index 876bf90ed96e..99c541e7fa8c 100644
> --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
> +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
> @@ -30,6 +30,16 @@ properties:
>      maxItems: 1
>  
>    clocks:
> +    minItems: 1
> +    maxItems: 2
> +
> +  clock-names:
> +    minItems: 1
> +    items:
> +      - const: core
> +      - const: iface
> +
> +  power-domains:
>      maxItems: 1
>  
>    operating-points-v2: true
> @@ -52,7 +62,11 @@ examples:
>        compatible = "qcom,sm8550-inline-crypto-engine",
>                     "qcom,inline-crypto-engine";
>        reg = <0x01d88000 0x8000>;
> -      clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
> +      clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
> +               <&gcc GCC_UFS_PHY_AHB_CLK>;
> +      clock-names = "core",
> +                    "iface";

We don't actually need names here. You can use indices instead, making
the change completely backwards-compatible.

> +      power-domains = <&gcc UFS_PHY_GDSC>;
>  
>        operating-points-v2 = <&ice_opp_table>;
>  
> 
> -- 
> 2.34.1
> 

-- 
With best wishes
Dmitry

Re: [PATCH v3 01/12] dt-bindings: crypto: qcom,ice: Allow power-domain and iface clk

[Harshal Dev]

Hi Dmitry ,

On 3/17/2026 8:42 PM, Dmitry Baryshkov wrote:
> On Tue, Mar 17, 2026 at 02:50:40PM +0530, Harshal Dev wrote:
>> Update the inline-crypto engine DT binding in a backward compatible manner
>> to allow specifying up to two clocks along with their names and associated
>> power-domain.
> 
> This should come after the "why" part.

Ack.

> 
>>
>> When the 'clk_ignore_unused' flag is not passed on the kernel command line
>> occasional unclocked ICE hardware register access are observed when the
>> kernel disables the unused 'iface' clock before ICE can probe. On the other
>> hand, when the 'pd_ignore_unused' flag is not passed on the command line,
>> clock 'stuck' issues are observed if the power-domain required by ICE
>> hardware is unused and thus disabled before ICE probe could happen.
> 
> You can simply say that ICE requires these clocks and these power
> domains to function. Accessing the hardware can fail if they are
> disabled by the kernel for whater reasons.
>

Ack.

>>
>> To avoid these scenarios, the 'iface' clock and the associated power-domain
>> should be specified in the ICE device tree node and enabled by ICE.
>>
>> Fixes: f6ff91a47ac57 ("dt-bindings: crypto: Add Qualcomm Inline Crypto Engine")
>> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
>> ---
>>  .../bindings/crypto/qcom,inline-crypto-engine.yaml       | 16 +++++++++++++++-
>>  1 file changed, 15 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
>> index 876bf90ed96e..99c541e7fa8c 100644
>> --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
>> +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
>> @@ -30,6 +30,16 @@ properties:
>>      maxItems: 1
>>  
>>    clocks:
>> +    minItems: 1
>> +    maxItems: 2
>> +
>> +  clock-names:
>> +    minItems: 1
>> +    items:
>> +      - const: core
>> +      - const: iface
>> +
>> +  power-domains:
>>      maxItems: 1
>>  
>>    operating-points-v2: true
>> @@ -52,7 +62,11 @@ examples:
>>        compatible = "qcom,sm8550-inline-crypto-engine",
>>                     "qcom,inline-crypto-engine";
>>        reg = <0x01d88000 0x8000>;
>> -      clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
>> +      clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
>> +               <&gcc GCC_UFS_PHY_AHB_CLK>;
>> +      clock-names = "core",
>> +                    "iface";
> 
> We don't actually need names here. You can use indices instead, making
> the change completely backwards-compatible.
>

I do not have very concrete objections to this. But introducing the clock
names isn't breaking backward compatibility either. I wanted to continue
using the names since the ICE driver has been following the tradition of
referring these clocks via names since it was part of the UFS/EMMC driver.

This also helps me avoid touching the ICE driver source code for specifying
the index of the clocks.

Let me know if continuing to use the names is a no-go from you for some
other reason.

Thanks,
Harshal

 
>> +      power-domains = <&gcc UFS_PHY_GDSC>;
>>  
>>        operating-points-v2 = <&ice_opp_table>;
>>  
>>
>> -- 
>> 2.34.1
>>
> 

Re: [PATCH v3 01/12] dt-bindings: crypto: qcom,ice: Allow power-domain and iface clk

[Krzysztof Kozlowski]

On Tue, Mar 17, 2026 at 05:12:36PM +0200, Dmitry Baryshkov wrote:
> On Tue, Mar 17, 2026 at 02:50:40PM +0530, Harshal Dev wrote:
> > Update the inline-crypto engine DT binding in a backward compatible manner
> > to allow specifying up to two clocks along with their names and associated
> > power-domain.
> 
> This should come after the "why" part.
> 
> > 
> > When the 'clk_ignore_unused' flag is not passed on the kernel command line
> > occasional unclocked ICE hardware register access are observed when the
> > kernel disables the unused 'iface' clock before ICE can probe. On the other
> > hand, when the 'pd_ignore_unused' flag is not passed on the command line,
> > clock 'stuck' issues are observed if the power-domain required by ICE
> > hardware is unused and thus disabled before ICE probe could happen.
> 
> You can simply say that ICE requires these clocks and these power
> domains to function. Accessing the hardware can fail if they are
> disabled by the kernel for whater reasons.

Yeah, mentioning clk_ignore_unused/pd is redundant here.

> 
> > 
> > To avoid these scenarios, the 'iface' clock and the associated power-domain
> > should be specified in the ICE device tree node and enabled by ICE.

And this repeats the first paragraph.

> > 
> > Fixes: f6ff91a47ac57 ("dt-bindings: crypto: Add Qualcomm Inline Crypto Engine")
> > Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
> > ---
> >  .../bindings/crypto/qcom,inline-crypto-engine.yaml       | 16 +++++++++++++++-
> >  1 file changed, 15 insertions(+), 1 deletion(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
> > index 876bf90ed96e..99c541e7fa8c 100644
> > --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
> > +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
> > @@ -30,6 +30,16 @@ properties:
> >      maxItems: 1
> >  
> >    clocks:
> > +    minItems: 1
> > +    maxItems: 2
> > +
> > +  clock-names:
> > +    minItems: 1
> > +    items:
> > +      - const: core
> > +      - const: iface
> > +
> > +  power-domains:
> >      maxItems: 1

I do not see how you implemented my feedback, at all. Nothing from it.

I even provided you final clarifications. What is the point of asking me
for the third time, again, what should you do, if you just ignore it?

1. What the DTS is doing here?
2. How did you address "with explanation why this is a fix thus why this
should go to current cycle." - where is this part?
3. Where is Eliza and Milos?

I was repeating the last 2 points multiple times already.

Best regards,
Krzysztof

Re: [PATCH v3 01/12] dt-bindings: crypto: qcom,ice: Allow power-domain and iface clk

[Harshal Dev]

On 3/18/2026 12:52 PM, Krzysztof Kozlowski wrote:
> On Tue, Mar 17, 2026 at 05:12:36PM +0200, Dmitry Baryshkov wrote:
>> On Tue, Mar 17, 2026 at 02:50:40PM +0530, Harshal Dev wrote:
>>> Update the inline-crypto engine DT binding in a backward compatible manner
>>> to allow specifying up to two clocks along with their names and associated
>>> power-domain.
>>
>> This should come after the "why" part.
>>
>>>
>>> When the 'clk_ignore_unused' flag is not passed on the kernel command line
>>> occasional unclocked ICE hardware register access are observed when the
>>> kernel disables the unused 'iface' clock before ICE can probe. On the other
>>> hand, when the 'pd_ignore_unused' flag is not passed on the command line,
>>> clock 'stuck' issues are observed if the power-domain required by ICE
>>> hardware is unused and thus disabled before ICE probe could happen.
>>
>> You can simply say that ICE requires these clocks and these power
>> domains to function. Accessing the hardware can fail if they are
>> disabled by the kernel for whater reasons.
> 
> Yeah, mentioning clk_ignore_unused/pd is redundant here.

Ack.

> 
>>
>>>
>>> To avoid these scenarios, the 'iface' clock and the associated power-domain
>>> should be specified in the ICE device tree node and enabled by ICE.
> 
> And this repeats the first paragraph.

Ack.

> 
>>>
>>> Fixes: f6ff91a47ac57 ("dt-bindings: crypto: Add Qualcomm Inline Crypto Engine")
>>> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
>>> ---
>>>  .../bindings/crypto/qcom,inline-crypto-engine.yaml       | 16 +++++++++++++++-
>>>  1 file changed, 15 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
>>> index 876bf90ed96e..99c541e7fa8c 100644
>>> --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
>>> +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
>>> @@ -30,6 +30,16 @@ properties:
>>>      maxItems: 1
>>>  
>>>    clocks:
>>> +    minItems: 1
>>> +    maxItems: 2
>>> +
>>> +  clock-names:
>>> +    minItems: 1
>>> +    items:
>>> +      - const: core
>>> +      - const: iface
>>> +
>>> +  power-domains:
>>>      maxItems: 1
> 
> 
> 1. What the DTS is doing here?

Okay. I will add a description of the expectation imposed by this binding on
the DTS in the commit message of this patch.

> 2. How did you address "with explanation why this is a fix thus why this
> should go to current cycle." - where is this part?

My mistake, I will explicitly write in the commit message that this change
is fixing the issues caused by missing power-domain and clocks in the DTS
by preserving backward-compatibility for old devices and constraining these
resources for new ones, i.e, Eliza and Milos.

> 3. Where is Eliza and Milos?

I will merge the unnecessary commit I introduced as Patch 2 into this commit
and explain that we are making the clock and power-domain 'required' for
Eliza and Milos since they constitute unreleased ABI and can carry this
new constraint.

Regards,
Harshal

> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v3 01/12] dt-bindings: crypto: qcom,ice: Allow power-domain and iface clk

[Krzysztof Kozlowski]

On 18/03/2026 11:30, Harshal Dev wrote:
> 
> 
> On 3/18/2026 12:52 PM, Krzysztof Kozlowski wrote:
>> On Tue, Mar 17, 2026 at 05:12:36PM +0200, Dmitry Baryshkov wrote:
>>> On Tue, Mar 17, 2026 at 02:50:40PM +0530, Harshal Dev wrote:
>>>> Update the inline-crypto engine DT binding in a backward compatible manner
>>>> to allow specifying up to two clocks along with their names and associated
>>>> power-domain.
>>>
>>> This should come after the "why" part.
>>>
>>>>
>>>> When the 'clk_ignore_unused' flag is not passed on the kernel command line
>>>> occasional unclocked ICE hardware register access are observed when the
>>>> kernel disables the unused 'iface' clock before ICE can probe. On the other
>>>> hand, when the 'pd_ignore_unused' flag is not passed on the command line,
>>>> clock 'stuck' issues are observed if the power-domain required by ICE
>>>> hardware is unused and thus disabled before ICE probe could happen.
>>>
>>> You can simply say that ICE requires these clocks and these power
>>> domains to function. Accessing the hardware can fail if they are
>>> disabled by the kernel for whater reasons.
>>
>> Yeah, mentioning clk_ignore_unused/pd is redundant here.
> 
> Ack.
> 
>>
>>>
>>>>
>>>> To avoid these scenarios, the 'iface' clock and the associated power-domain
>>>> should be specified in the ICE device tree node and enabled by ICE.
>>
>> And this repeats the first paragraph.
> 
> Ack.
> 
>>
>>>>
>>>> Fixes: f6ff91a47ac57 ("dt-bindings: crypto: Add Qualcomm Inline Crypto Engine")
>>>> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
>>>> ---
>>>>  .../bindings/crypto/qcom,inline-crypto-engine.yaml       | 16 +++++++++++++++-
>>>>  1 file changed, 15 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
>>>> index 876bf90ed96e..99c541e7fa8c 100644
>>>> --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
>>>> +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
>>>> @@ -30,6 +30,16 @@ properties:
>>>>      maxItems: 1
>>>>  
>>>>    clocks:
>>>> +    minItems: 1
>>>> +    maxItems: 2
>>>> +
>>>> +  clock-names:
>>>> +    minItems: 1
>>>> +    items:
>>>> +      - const: core
>>>> +      - const: iface
>>>> +
>>>> +  power-domains:
>>>>      maxItems: 1
>>
>>
>> 1. What the DTS is doing here?
> 
> Okay. I will add a description of the expectation imposed by this binding on
> the DTS in the commit message of this patch.

You target this to fixes. Your subject and PATCH prefix should state
that. DTS is irrelevant in the git history in this context.

I stated previous the reason why this must go to the fixes.


Best regards,
Krzysztof

[PATCH v3 02/12] dt-bindings: crypto: qcom,ice: Require power-domain and iface clk

[Harshal Dev]

Update the DT bindings for inline-crypto engine to require the power-domain
and iface clock for Eliza and Milos.

If the 'clk_ignore_unused' flag is not passed on the kernel command line,
the unused 'iface' clock could be disabled by the kernel before ICE can
probe. This leads to unclocked ICE hardware register accces being observed
during ICE driver probe. On the other hand, If the 'pd_ignore_unused' flag
is not passed on the kernel command line, the unused UFS_PHY_GDSC power
domain could be disabled by the kernel before ICE probes. This results in
a 'stuck' clock issue being observed when ICE attempts to enable the
'core' clock.

Therefore, both the 'iface' clock and the UFS_PHY_GDSC power domain are
mandatory resources for ICE which must be specified in the device tree
node.

Fixes: 618195a7ac3df ("dt-bindings: crypto: qcom,inline-crypto-engine: Document the Eliza ICE")
Fixes: 85faec1e85555 ("dt-bindings: crypto: qcom,inline-crypto-engine: document the Milos ICE")
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
---
 .../bindings/crypto/qcom,inline-crypto-engine.yaml    | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
index 99c541e7fa8c..ccb6b8dd8e11 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
@@ -54,6 +54,25 @@ required:
 
 additionalProperties: false
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,eliza-inline-crypto-engine
+              - qcom,milos-inline-crypto-engine
+
+    then:
+      required:
+        - power-domains
+        - clock-names
+      properties:
+        clocks:
+          minItems: 2
+        clock-names:
+          minItems: 2
+
 examples:
   - |
     #include <dt-bindings/clock/qcom,sm8550-gcc.h>

-- 
2.34.1

Re: [PATCH v3 02/12] dt-bindings: crypto: qcom,ice: Require power-domain and iface clk

[Dmitry Baryshkov]

On Tue, Mar 17, 2026 at 02:50:41PM +0530, Harshal Dev wrote:
> Update the DT bindings for inline-crypto engine to require the power-domain
> and iface clock for Eliza and Milos.

Again, this mostly duplicates the subject (and your last paragraph).
Either drop it or move it there.

> 
> If the 'clk_ignore_unused' flag is not passed on the kernel command line,
> the unused 'iface' clock could be disabled by the kernel before ICE can
> probe. This leads to unclocked ICE hardware register accces being observed
> during ICE driver probe. On the other hand, If the 'pd_ignore_unused' flag
> is not passed on the kernel command line, the unused UFS_PHY_GDSC power
> domain could be disabled by the kernel before ICE probes. This results in
> a 'stuck' clock issue being observed when ICE attempts to enable the
> 'core' clock.

What's the difference from the previous patch?

> 
> Therefore, both the 'iface' clock and the UFS_PHY_GDSC power domain are
> mandatory resources for ICE which must be specified in the device tree
> node.
> 
> Fixes: 618195a7ac3df ("dt-bindings: crypto: qcom,inline-crypto-engine: Document the Eliza ICE")
> Fixes: 85faec1e85555 ("dt-bindings: crypto: qcom,inline-crypto-engine: document the Milos ICE")
> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
> ---
>  .../bindings/crypto/qcom,inline-crypto-engine.yaml    | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 

-- 
With best wishes
Dmitry

Re: [PATCH v3 02/12] dt-bindings: crypto: qcom,ice: Require power-domain and iface clk

[Krzysztof Kozlowski]

On 17/03/2026 16:13, Dmitry Baryshkov wrote:
> On Tue, Mar 17, 2026 at 02:50:41PM +0530, Harshal Dev wrote:
>> Update the DT bindings for inline-crypto engine to require the power-domain
>> and iface clock for Eliza and Milos.
> 
> Again, this mostly duplicates the subject (and your last paragraph).
> Either drop it or move it there.
> 
>>
>> If the 'clk_ignore_unused' flag is not passed on the kernel command line,
>> the unused 'iface' clock could be disabled by the kernel before ICE can
>> probe. This leads to unclocked ICE hardware register accces being observed
>> during ICE driver probe. On the other hand, If the 'pd_ignore_unused' flag
>> is not passed on the kernel command line, the unused UFS_PHY_GDSC power
>> domain could be disabled by the kernel before ICE probes. This results in
>> a 'stuck' clock issue being observed when ICE attempts to enable the
>> 'core' clock.
> 
> What's the difference from the previous patch?

There is no, it's just completely missing the point of development cycle
and ignoring multiple of my feedbacks.

I asked to POST A PATCH targeting current RC. One patch. Current RC, not
next.

How is this supposed to be merged without the first one? How do anyone
here imagine this is supposed to work when applying to the tree?

Best regards,
Krzysztof

Re: [PATCH v3 02/12] dt-bindings: crypto: qcom,ice: Require power-domain and iface clk

[Harshal Dev]

On 3/18/2026 12:57 PM, Krzysztof Kozlowski wrote:
> On 17/03/2026 16:13, Dmitry Baryshkov wrote:
>> On Tue, Mar 17, 2026 at 02:50:41PM +0530, Harshal Dev wrote:
>>> Update the DT bindings for inline-crypto engine to require the power-domain
>>> and iface clock for Eliza and Milos.
>>
>> Again, this mostly duplicates the subject (and your last paragraph).
>> Either drop it or move it there.
>>
>>>
>>> If the 'clk_ignore_unused' flag is not passed on the kernel command line,
>>> the unused 'iface' clock could be disabled by the kernel before ICE can
>>> probe. This leads to unclocked ICE hardware register accces being observed
>>> during ICE driver probe. On the other hand, If the 'pd_ignore_unused' flag
>>> is not passed on the kernel command line, the unused UFS_PHY_GDSC power
>>> domain could be disabled by the kernel before ICE probes. This results in
>>> a 'stuck' clock issue being observed when ICE attempts to enable the
>>> 'core' clock.
>>
>> What's the difference from the previous patch?
> 
> 
> I asked to POST A PATCH targeting current RC. One patch. Current RC, not
> next.

Ack, I will merge the changes in this patch into the previous patch to ensure we
have one consolidated fix for the current RC.

Regards,
Harshal

> 
> 
> Best regards,
> Krzysztof

Re: [PATCH v3 02/12] dt-bindings: crypto: qcom,ice: Require power-domain and iface clk

[Krzysztof Kozlowski]

On Tue, Mar 17, 2026 at 02:50:41PM +0530, Harshal Dev wrote:
> Update the DT bindings for inline-crypto engine to require the power-domain
> and iface clock for Eliza and Milos.
> 

NAK, pointless patch. It makes no sense on its own and it cannot be a
fix for earlier issues, because as a fix standalone is simply WRONG.

Where did you emphasize this is the fix for current RC?

Best regards,
Krzysztof

Re: [PATCH v3 02/12] dt-bindings: crypto: qcom,ice: Require power-domain and iface clk

[Harshal Dev]

On 3/18/2026 12:53 PM, Krzysztof Kozlowski wrote:
> On Tue, Mar 17, 2026 at 02:50:41PM +0530, Harshal Dev wrote:
>> Update the DT bindings for inline-crypto engine to require the power-domain
>> and iface clock for Eliza and Milos.
>>
> 
> NAK, pointless patch. It makes no sense on its own and it cannot be a
> fix for earlier issues, because as a fix standalone is simply WRONG.
> 
> Where did you emphasize this is the fix for current RC?

Ack, I will add explicit emphasis that this is a fix for the current RC in
the commit message after merging this patch into the previous one.

Regards,
Harshal

> 
> Best regards,
> Krzysztof
> 
> 

[PATCH v3 03/12] arm64: dts: qcom: kaanapali: Add power-domain and iface clk for ice node

[Harshal Dev]

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for its own resources. Before accessing ICE hardware during probe, to
avoid potential unclocked register access issues (when clk_ignore_unused
is not passed on the kernel command line), in addition to the 'core' clock
the 'iface' clock should also be turned on by the driver. This can only be
done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the
GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for
kaanapali.

Fixes: 2eeb5767d53f4 ("arm64: dts: qcom: Introduce Kaanapali SoC")
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kaanapali.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 9ef57ad0ca71..52af56e09168 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -868,7 +868,11 @@ ice: crypto@1d88000 {
 				     "qcom,inline-crypto-engine";
 			reg = <0x0 0x01d88000 0x0 0x18000>;
 
-			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>;
+			clock-names = "core",
+				      "iface";
+			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
 		};
 
 		tcsr_mutex: hwlock@1f40000 {

-- 
2.34.1

[PATCH v3 04/12] arm64: dts: qcom: lemans: Add power-domain and iface clk for ice node

[Harshal Dev]

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for its own resources. Before accessing ICE hardware during probe, to
avoid potential unclocked register access issues (when clk_ignore_unused
is not passed on the kernel command line), in addition to the 'core' clock
the 'iface' clock should also be turned on by the driver. This can only be
done if the UFS_PHY_GDSC power domain is enabled. Specify both the
UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for lemans.

Fixes: 96272ba7103d4 ("arm64: dts: qcom: sa8775p: enable the inline crypto engine")
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/lemans.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 67b2c7e819ad..cdfa42293022 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -2758,7 +2758,11 @@ ice: crypto@1d88000 {
 			compatible = "qcom,sa8775p-inline-crypto-engine",
 				     "qcom,inline-crypto-engine";
 			reg = <0x0 0x01d88000 0x0 0x18000>;
-			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>;
+			clock-names = "core",
+				      "iface";
+			power-domains = <&gcc UFS_PHY_GDSC>;
 		};
 
 		cryptobam: dma-controller@1dc4000 {

-- 
2.34.1

[PATCH v3 05/12] arm64: dts: qcom: monaco: Add power-domain and iface clk for ice node

[Harshal Dev]

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for its own resources. Before accessing ICE hardware during probe, to
avoid potential unclocked register access issues (when clk_ignore_unused
is not passed on the kernel command line), in addition to the 'core' clock
the 'iface' clock should also be turned on by the driver. This can only be
done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the
GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for
monaco.

Fixes: cc9d29aad876d ("arm64: dts: qcom: qcs8300: enable the inline crypto engine")
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/monaco.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index f92fdb1cefa0..e408f102a8b3 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -2725,7 +2725,11 @@ ice: crypto@1d88000 {
 			compatible = "qcom,qcs8300-inline-crypto-engine",
 				     "qcom,inline-crypto-engine";
 			reg = <0x0 0x01d88000 0x0 0x18000>;
-			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>;
+			clock-names = "core",
+				      "iface";
+			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
 		};
 
 		crypto: crypto@1dfa000 {

-- 
2.34.1

[PATCH v3 06/12] arm64: dts: qcom: sc7180: Add power-domain and iface clk for ice node

[Harshal Dev]

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for its own resources. Before accessing ICE hardware during probe, to
avoid potential unclocked register access issues (when clk_ignore_unused
is not passed on the kernel command line), in addition to the 'core' clock
the 'iface' clock should also be turned on by the driver. This can only be
done if the UFS_PHY_GDSC power domain is enabled. Specify both the
UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sc7180.

Fixes: 858536d9dc946 ("arm64: dts: qcom: sc7180: Add UFS nodes")
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 8d69225a4271..9eaee5dc824c 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1605,7 +1605,11 @@ ice: crypto@1d90000 {
 			compatible = "qcom,sc7180-inline-crypto-engine",
 				     "qcom,inline-crypto-engine";
 			reg = <0 0x01d90000 0 0x8000>;
-			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>;
+			clock-names = "core",
+				      "iface";
+			power-domains = <&gcc UFS_PHY_GDSC>;
 		};
 
 		ipa: ipa@1e40000 {

-- 
2.34.1

[PATCH v3 07/12] arm64: dts: qcom: kodiak: Add power-domain and iface clk for ice node

[Harshal Dev]

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for its own resources. Before accessing ICE hardware during probe, to
avoid potential unclocked register access issues (when clk_ignore_unused
is not passed on the kernel command line), in addition to the 'core' clock
the 'iface' clock should also be turned on by the driver. This can only be
done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the
GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for
kodiak.

Fixes: dfd5ee7b34bb7 ("arm64: dts: qcom: sc7280: Add inline crypto engine")
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kodiak.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 149954a3eb7c..9765bf361db4 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -2579,7 +2579,11 @@ ice: crypto@1d88000 {
 			compatible = "qcom,sc7280-inline-crypto-engine",
 				     "qcom,inline-crypto-engine";
 			reg = <0 0x01d88000 0 0x8000>;
-			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>;
+			clock-names = "core",
+				      "iface";
+			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
 		};
 
 		cryptobam: dma-controller@1dc4000 {

-- 
2.34.1

[PATCH v3 08/12] arm64: dts: qcom: sm8450: Add power-domain and iface clk for ice node

[Harshal Dev]

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for its own resources. Before accessing ICE hardware during probe, to
avoid potential unclocked register access issues (when clk_ignore_unused
is not passed on the kernel command line), in addition to the 'core' clock
the 'iface' clock should also be turned on by the driver. This can only be
done if the UFS_PHY_GDSC power domain is enabled. Specify both the
UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8450.

Fixes: 86b0aef435851 ("arm64: dts: qcom: sm8450: Use standalone ICE node for UFS")
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index fd2d5648b92a..0dba282d644d 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -5374,7 +5374,11 @@ ice: crypto@1d88000 {
 			compatible = "qcom,sm8450-inline-crypto-engine",
 				     "qcom,inline-crypto-engine";
 			reg = <0 0x01d88000 0 0x8000>;
-			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>;
+			clock-names = "core",
+				      "iface";
+			power-domains = <&gcc UFS_PHY_GDSC>;
 		};
 
 		cryptobam: dma-controller@1dc4000 {

-- 
2.34.1

[PATCH v3 09/12] arm64: dts: qcom: sm8550: Add power-domain and iface clk for ice node

[Harshal Dev]

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for its own resources. Before accessing ICE hardware during probe, to
avoid potential unclocked register access issues (when clk_ignore_unused
is not passed on the kernel command line), in addition to the 'core' clock
the 'iface' clock should also be turned on by the driver. This can only be
done if the UFS_PHY_GDSC power domain is enabled. Specify both the
UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8550.

Fixes: b8630c48b43fc ("arm64: dts: qcom: sm8550: Add the Inline Crypto Engine node")
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index e3f93f4f412d..473fb4748036 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2449,7 +2449,11 @@ ice: crypto@1d88000 {
 				     "qcom,inline-crypto-engine";
 			reg = <0 0x01d88000 0 0x18000>;
 
-			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>;
+			clock-names = "core",
+				      "iface";
+			power-domains = <&gcc UFS_PHY_GDSC>;
 		};
 
 		tcsr_mutex: hwlock@1f40000 {

-- 
2.34.1

[PATCH v3 10/12] arm64: dts: qcom: sm8650: Add power-domain and iface clk for ice node

[Harshal Dev]

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for its own resources. Before accessing ICE hardware during probe, to
avoid potential unclocked register access issues (when clk_ignore_unused
is not passed on the kernel command line), in addition to the 'core' clock
the 'iface' clock should also be turned on by the driver. This can only be
done if the UFS_PHY_GDSC power domain is enabled. Specify both the
UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8650.

Fixes: 10e0246712951 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes")
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 357e43b90740..d211bd94fb41 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -4081,7 +4081,11 @@ ice: crypto@1d88000 {
 				     "qcom,inline-crypto-engine";
 			reg = <0 0x01d88000 0 0x18000>;
 
-			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>;
+			clock-names = "core",
+				      "iface";
+			power-domains = <&gcc UFS_PHY_GDSC>;
 		};
 
 		cryptobam: dma-controller@1dc4000 {

-- 
2.34.1

[PATCH v3 11/12] arm64: dts: qcom: sm8750: Add power-domain and iface clk for ice node

[Harshal Dev]

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for its own resources. Before accessing ICE hardware during probe, to
avoid potential unclocked register access issues (when clk_ignore_unused
is not passed on the kernel command line), in addition to the 'core' clock
the 'iface' clock should also be turned on by the driver. This can only be
done if the GCC_UFS_PHY_GDSC power domain is enabled. Specify both the
GCC_UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for
sm8750.

Fixes: b1dac789c650a ("arm64: dts: qcom: sm8750: Add ICE nodes")
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8750.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index f56b1f889b85..8c33bc3620ef 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -2083,7 +2083,11 @@ ice: crypto@1d88000 {
 				     "qcom,inline-crypto-engine";
 			reg = <0x0 0x01d88000 0x0 0x18000>;
 
-			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>;
+			clock-names = "core",
+				      "iface";
+			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
 		};
 
 		cryptobam: dma-controller@1dc4000 {

-- 
2.34.1

[PATCH v3 12/12] soc: qcom: ice: Allow explicit votes on 'iface' clock for ICE

[Harshal Dev]

Since Qualcomm inline-crypto engine (ICE) is now a dedicated driver
de-coupled from the QCOM UFS driver, it explicitly votes for its required
clocks during probe. For scenarios where the 'clk_ignore_unused' flag is
not passed on the kernel command line, to avoid potential unclocked ICE
hardware register access during probe the ICE driver should additionally
vote on the 'iface' clock.
Also update the suspend and resume callbacks to handle un-voting and voting
on the 'iface' clock.

Fixes: 2afbf43a4aec6 ("soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver")
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
---
 drivers/soc/qcom/ice.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c
index b203bc685cad..bf4ab2d9e5c0 100644
--- a/drivers/soc/qcom/ice.c
+++ b/drivers/soc/qcom/ice.c
@@ -108,6 +108,7 @@ struct qcom_ice {
 	void __iomem *base;
 
 	struct clk *core_clk;
+	struct clk *iface_clk;
 	bool use_hwkm;
 	bool hwkm_init_complete;
 	u8 hwkm_version;
@@ -312,8 +313,13 @@ int qcom_ice_resume(struct qcom_ice *ice)
 
 	err = clk_prepare_enable(ice->core_clk);
 	if (err) {
-		dev_err(dev, "failed to enable core clock (%d)\n",
-			err);
+		dev_err(dev, "Failed to enable core clock: %d\n", err);
+		return err;
+	}
+
+	err = clk_prepare_enable(ice->iface_clk);
+	if (err) {
+		dev_err(dev, "Failed to enable iface clock: %d\n", err);
 		return err;
 	}
 	qcom_ice_hwkm_init(ice);
@@ -323,6 +329,7 @@ EXPORT_SYMBOL_GPL(qcom_ice_resume);
 
 int qcom_ice_suspend(struct qcom_ice *ice)
 {
+	clk_disable_unprepare(ice->iface_clk);
 	clk_disable_unprepare(ice->core_clk);
 	ice->hwkm_init_complete = false;
 
@@ -579,11 +586,17 @@ static struct qcom_ice *qcom_ice_create(struct device *dev,
 	engine->core_clk = devm_clk_get_optional_enabled(dev, "ice_core_clk");
 	if (!engine->core_clk)
 		engine->core_clk = devm_clk_get_optional_enabled(dev, "ice");
+	if (!engine->core_clk)
+		engine->core_clk = devm_clk_get_optional_enabled(dev, "core");
 	if (!engine->core_clk)
 		engine->core_clk = devm_clk_get_enabled(dev, NULL);
 	if (IS_ERR(engine->core_clk))
 		return ERR_CAST(engine->core_clk);
 
+	engine->iface_clk = devm_clk_get_optional_enabled(dev, "iface");
+	if (IS_ERR(engine->iface_clk))
+		return ERR_CAST(engine->iface_clk);
+
 	if (!qcom_ice_check_supported(engine))
 		return ERR_PTR(-EOPNOTSUPP);
 

-- 
2.34.1

Re: [PATCH v3 12/12] soc: qcom: ice: Allow explicit votes on 'iface' clock for ICE

[Krzysztof Kozlowski]

On 17/03/2026 10:20, Harshal Dev wrote:
> Since Qualcomm inline-crypto engine (ICE) is now a dedicated driver
> de-coupled from the QCOM UFS driver, it explicitly votes for its required
> clocks during probe. For scenarios where the 'clk_ignore_unused' flag is
> not passed on the kernel command line, to avoid potential unclocked ICE
> hardware register access during probe the ICE driver should additionally
> vote on the 'iface' clock.
> Also update the suspend and resume callbacks to handle un-voting and voting
> on the 'iface' clock.
> 
> Fixes: 2afbf43a4aec6 ("soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver")
> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
> ---
>  drivers/soc/qcom/ice.c | 17 +++++++++++++++--

Why the driver patch is after the DTS patches? It is explicitly
documented as no-go.

You do not understand how patches are being applied and you think you
can fix inherent problems in bisectability by creating incorrect order
of patches. No, you cannot. Read maintainer soc profile and entire
development-process document, so you understand how patches are applied,
what are branches, what is current RC and how kernel is effectively
released.

Best regards,
Krzysztof

Re: [PATCH v3 12/12] soc: qcom: ice: Allow explicit votes on 'iface' clock for ICE

[Harshal Dev]

On 3/18/2026 1:03 PM, Krzysztof Kozlowski wrote:
> On 17/03/2026 10:20, Harshal Dev wrote:
>> Since Qualcomm inline-crypto engine (ICE) is now a dedicated driver
>> de-coupled from the QCOM UFS driver, it explicitly votes for its required
>> clocks during probe. For scenarios where the 'clk_ignore_unused' flag is
>> not passed on the kernel command line, to avoid potential unclocked ICE
>> hardware register access during probe the ICE driver should additionally
>> vote on the 'iface' clock.
>> Also update the suspend and resume callbacks to handle un-voting and voting
>> on the 'iface' clock.
>>
>> Fixes: 2afbf43a4aec6 ("soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver")
>> Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
>> ---
>>  drivers/soc/qcom/ice.c | 17 +++++++++++++++--
> 
> Why the driver patch is after the DTS patches? It is explicitly
> documented as no-go.

I will re-order this patch to come after the DT-binding patch and before
the DTS patches.

Regards,
Harshal

> 
> You do not understand how patches are being applied and you think you
> can fix inherent problems in bisectability by creating incorrect order
> of patches. No, you cannot. Read maintainer soc profile and entire
> development-process document, so you understand how patches are applied,
> what are branches, what is current RC and how kernel is effectively
> released.
> 
> Best regards,
> Krzysztof