From: Dan Magenheimer <dan.magenheimer@oracle.com>
To: "Xen-Devel (E-mail)" <xen-devel@lists.xensource.com>
Subject: [PATCH] pvcpuid: mask TSC invariant bit for various circumstances
Date: Mon, 26 Oct 2009 16:12:37 -0700 (PDT) [thread overview]
Message-ID: <8a95a56e-c387-46c7-a7d2-5a84bdfd1485@default> (raw)
[-- Attachment #1: Type: text/plain, Size: 1647 bytes --]
pvcpuid: mask TSC invariant bit for PV domains if migration
is not disabled and TSC is not emulated
(Need similar patch for HVM domain)
Signed-off-by: Dan Magenheimer <dan.magenheimer@oracle.com>
diff -r d7d7f978d704 xen/arch/x86/domain.c
--- a/xen/arch/x86/domain.c Tue Oct 20 14:36:01 2009 +0100
+++ b/xen/arch/x86/domain.c Mon Oct 26 16:13:43 2009 -0600
@@ -51,6 +51,7 @@
#include <asm/nmi.h>
#include <xen/numa.h>
#include <xen/iommu.h>
+#include <public/arch-x86/cpuid.h>
#ifdef CONFIG_COMPAT
#include <compat/vcpu.h>
#endif
@@ -2044,6 +2045,13 @@ void domain_cpuid(
*ebx = cpuid->ebx;
*ecx = cpuid->ecx;
*edx = cpuid->edx;
+ if ( input == XEN_CPUID_APM_FUNCTION )
+ {
+ /* mask TSC invariant bit if migration is not disabled
+ and TSC is not emulated */
+ if ( !d->disable_migrate && !d->arch.vtsc )
+ *edx &= ~XEN_CPUID_APM_EDX_TSC_INVARIANT;
+ }
return;
}
}
diff -r d7d7f978d704 xen/include/public/arch-x86/cpuid.h
--- a/xen/include/public/arch-x86/cpuid.h Tue Oct 20 14:36:01 2009 +0100
+++ b/xen/include/public/arch-x86/cpuid.h Mon Oct 26 16:13:43 2009 -0600
@@ -65,4 +65,8 @@
#define _XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD 0
#define XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD (1u<<0)
+/* Does the host support TSC Invariance (in Advanced Power Management)? */
+#define XEN_CPUID_APM_FUNCTION 0x80000007
+#define XEN_CPUID_APM_EDX_TSC_INVARIANT (1u<<8)
+
#endif /* __XEN_PUBLIC_ARCH_X86_CPUID_H__ */
[-- Attachment #2: cpuid-invariant.patch --]
[-- Type: application/octet-stream, Size: 1404 bytes --]
diff -r d7d7f978d704 xen/arch/x86/domain.c
--- a/xen/arch/x86/domain.c Tue Oct 20 14:36:01 2009 +0100
+++ b/xen/arch/x86/domain.c Mon Oct 26 16:13:43 2009 -0600
@@ -51,6 +51,7 @@
#include <asm/nmi.h>
#include <xen/numa.h>
#include <xen/iommu.h>
+#include <public/arch-x86/cpuid.h>
#ifdef CONFIG_COMPAT
#include <compat/vcpu.h>
#endif
@@ -2044,6 +2045,13 @@ void domain_cpuid(
*ebx = cpuid->ebx;
*ecx = cpuid->ecx;
*edx = cpuid->edx;
+ if ( input == XEN_CPUID_APM_FUNCTION )
+ {
+ /* mask TSC invariant bit if migration is not disabled
+ and TSC is not emulated */
+ if ( !d->disable_migrate && !d->arch.vtsc )
+ *edx &= ~XEN_CPUID_APM_EDX_TSC_INVARIANT;
+ }
return;
}
}
diff -r d7d7f978d704 xen/include/public/arch-x86/cpuid.h
--- a/xen/include/public/arch-x86/cpuid.h Tue Oct 20 14:36:01 2009 +0100
+++ b/xen/include/public/arch-x86/cpuid.h Mon Oct 26 16:13:43 2009 -0600
@@ -65,4 +65,8 @@
#define _XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD 0
#define XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD (1u<<0)
+/* Does the host support TSC Invariance (in Advanced Power Management)? */
+#define XEN_CPUID_APM_FUNCTION 0x80000007
+#define XEN_CPUID_APM_EDX_TSC_INVARIANT (1u<<8)
+
#endif /* __XEN_PUBLIC_ARCH_X86_CPUID_H__ */
[-- Attachment #3: Type: text/plain, Size: 138 bytes --]
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next reply other threads:[~2009-10-26 23:12 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-10-26 23:12 Dan Magenheimer [this message]
2009-10-27 0:22 ` [PATCH] pvcpuid: mask TSC invariant bit for various circumstances Keir Fraser
2009-10-27 1:09 ` Dan Magenheimer
2009-10-27 7:31 ` Keir Fraser
2009-10-27 17:03 ` Dan Magenheimer
2009-10-27 17:16 ` Keir Fraser
2009-10-27 20:40 ` Dan Magenheimer
2009-10-27 20:58 ` Keir Fraser
2009-10-27 22:03 ` Dan Magenheimer
2009-10-28 7:16 ` Keir Fraser
2009-10-28 16:27 ` Dan Magenheimer
2009-10-28 16:38 ` Jan Beulich
2009-10-28 16:50 ` Dan Magenheimer
2009-10-28 17:29 ` Keir Fraser
2009-10-29 22:07 ` Jeremy Fitzhardinge
2009-10-29 22:17 ` Dan Magenheimer
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