From: Xiaoyao Li <xiaoyao.li@intel.com>
To: "Edgecombe, Rick P" <rick.p.edgecombe@intel.com>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"binbin.wu@linux.intel.com" <binbin.wu@linux.intel.com>
Cc: "nik.borisov@suse.com" <nik.borisov@suse.com>,
"pbonzini@redhat.com" <pbonzini@redhat.com>,
"kas@kernel.org" <kas@kernel.org>,
"seanjc@google.com" <seanjc@google.com>,
"Gao, Chao" <chao.gao@intel.com>,
"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
"andrew.cooper3@citrix.com" <andrew.cooper3@citrix.com>
Subject: Re: [PATCH v3 0/4] KVM: TDX: Validate directly configurable CPUID bits
Date: Wed, 2 Sep 2026 18:29:40 +0800 [thread overview]
Message-ID: <91c9e314-6b92-4f90-a2df-ed21104f84bc@intel.com> (raw)
In-Reply-To: <69c42183261acb4150961cabf6318b92765b6562.camel@intel.com>
On 9/2/2026 1:41 AM, Edgecombe, Rick P wrote:
> On Tue, 2026-09-01 at 17:38 +0800, Xiaoyao Li wrote:
>>>> Ideally the TDX save/restore would share code with normal VMs. On the
>>>> other hand if we don't share enter/exit paths sufficiently, we may need to
>>>> duplicate some save/restore in tdx code.
>>
>> (Copy the FRED example here for reference)
>>
>> >>>
>> >>> FRED is a useful concrete example. Under VMX, the FRED host state in
>> >>> IA32_FRED_CONFIG, IA32_FRED_STKLVLS, IA32_FRED_RSP1-3 and
>> >>> IA32_FRED_SSP1-3 is covered by the VMCS host-state area, so the TDX
>> module
>> >>> is expected to restore these MSRs on TDH.VP.ENTER return.
>> IA32_FRED_RSP0
>> >>> and IA32_PL0_SSP (a.k.a. IA32_FRED_SSP0) are handled by software,
>> so the
>> >>> TDX module is expected to clobber them on TDH.VP.ENTER return.
>>
>> What I get, is not matching VMX behavior but matching the behavior KVM
>> will perform for VMX. They are based on the assumption that KVM will
>> always enable the save/restore VMCS fields for a new feature. But I
>> don't think we can guarantee it.
>>
>> To me, "have TDX simply match VMX behavior" means:
>>
>> 1. if the VMX unconditionally save/restore a state, then TDX will do so.
>>
>> 2. if there are vm-entry/vm-exit load/save VMCS fields for a state, then
>> provide the equivalent per-TD configurable interfaces which matches the
>> VMCS fields.
>
> What do you mean by this? Expose a TDX module interface to configure the clobber
> behavior for each feature with load/save configuration? That was similar to what
> we originally discussed, before pivoting to this solution.
yeah. This is what I meant. I was trying to show my literal
understanding on "The proposal is to have TDX simply match VMX
behavior". i.e., I don't think "have TDX simply match VMX behavior" is a
good name/summary for what Binbin has proposed.
> I was thinking if you configured a feature (for example shadow stack), it would
> automatically set the VMCS save/restore settings associated with that feature.
> (VM_EXIT_LOAD_CET_STATE/VM_ENTRY_LOAD_CET_STATE)
>
> This won't necessarily match KVM's behavior, because it could decide to not use
> the features. But we can probably get close with a simple rule that can make
> sense for all the VMMs.
So the proposal is making TDX behave as if the relevant VMCS save/load
controls (if any) are set around TDH.VP.ENTER.
In fact, what matters for host vmm is just the VM_EXIT_LOAD_XXX control.
So the proposal becomes "If there is VM_EXIT_LOAD_XXX control for a
state, TDX needs to restore the host state after TDH.VP.ENTER. If no
such contorl, TDX sets the state to INIT state after TDH.VP.ENTER".
It's a fancy idea. And it provides a clear rule of how TDX handles
states of a feature so that host VMM developers don't need to read the
TDX module API to figure out what's the value of a state after TDH.VP.ENTER.
It's helpful for host VMM developers, though I'm not sure on TDX module
developers.
> If later we want a host clobber interface on top of the bit filtering, in order
> to minimize TDX special handling, we can probably add it later for features we
> care about. I'd think we don't need it right now.
next prev parent reply other threads:[~2026-09-02 10:29 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-27 3:18 [PATCH v3 0/4] KVM: TDX: Validate directly configurable CPUID bits Binbin Wu
2026-08-27 3:18 ` [PATCH v3 1/4] KVM: TDX: Track configurable CPUID bits allowed by KVM Binbin Wu
2026-09-01 6:29 ` Tony Lindgren
2026-09-01 8:23 ` Binbin Wu
2026-09-01 8:27 ` Tony Lindgren
2026-09-01 14:35 ` Xiaoyao Li
2026-09-02 0:33 ` Binbin Wu
2026-09-02 15:09 ` Xiaoyao Li
2026-09-02 16:19 ` Binbin Wu
2026-09-02 16:22 ` Edgecombe, Rick P
2026-09-02 16:25 ` Binbin Wu
2026-09-03 7:28 ` Xiaoyao Li
2026-09-03 8:57 ` Binbin Wu
2026-09-08 21:13 ` Edgecombe, Rick P
2026-09-09 16:39 ` Xiaoyao Li
2026-09-09 22:29 ` Sean Christopherson
2026-09-09 23:18 ` Edgecombe, Rick P
2026-09-10 2:39 ` Binbin Wu
2026-09-10 2:53 ` Xiaoyao Li
2026-09-08 21:15 ` Edgecombe, Rick P
2026-08-27 3:18 ` [PATCH v3 2/4] KVM: TDX: Report CORE_CAPABILITIES as configurable Binbin Wu
2026-09-01 6:45 ` Tony Lindgren
2026-09-02 17:43 ` Kishen Maloor
2026-09-03 2:22 ` Binbin Wu
2026-09-03 6:10 ` Kishen Maloor
2026-09-03 8:12 ` Binbin Wu
2026-08-27 3:18 ` [PATCH v3 3/4] KVM: TDX: Filter configurable CPUID bits Binbin Wu
2026-09-01 6:44 ` Tony Lindgren
2026-09-01 8:42 ` Binbin Wu
2026-09-01 9:09 ` Tony Lindgren
2026-09-03 8:04 ` Xiaoyao Li
2026-09-03 8:23 ` Binbin Wu
2026-08-27 3:18 ` [PATCH v3 4/4] KVM: TDX: Validate userspace CPUID input for KVM_TDX_INIT_VM Binbin Wu
2026-08-27 3:24 ` sashiko-bot
2026-08-27 7:25 ` Binbin Wu
2026-09-01 6:47 ` Tony Lindgren
2026-08-27 19:33 ` [PATCH v3 0/4] KVM: TDX: Validate directly configurable CPUID bits Edgecombe, Rick P
2026-08-28 3:19 ` Binbin Wu
2026-08-28 16:58 ` Edgecombe, Rick P
2026-08-31 5:01 ` Binbin Wu
2026-09-01 9:42 ` Xiaoyao Li
2026-09-01 10:21 ` Xiaoyao Li
2026-09-02 16:09 ` Edgecombe, Rick P
2026-09-02 16:21 ` Binbin Wu
2026-09-09 1:46 ` Binbin Wu
2026-09-01 9:38 ` Xiaoyao Li
2026-09-01 17:41 ` Edgecombe, Rick P
2026-09-02 10:29 ` Xiaoyao Li [this message]
2026-09-02 13:13 ` Edgecombe, Rick P
2026-09-02 13:39 ` Xiaoyao Li
2026-09-02 13:53 ` Edgecombe, Rick P
2026-09-02 14:21 ` Xiaoyao Li
2026-09-02 16:26 ` Binbin Wu
2026-09-08 9:42 ` Artem Bityutskiy
2026-09-09 0:04 ` Binbin Wu
2026-09-08 20:30 ` Artem Bityutskiy
2026-09-08 22:31 ` Edgecombe, Rick P
2026-09-09 6:52 ` Artem Bityutskiy
2026-09-09 8:48 ` Binbin Wu
2026-09-09 11:20 ` Artem Bityutskiy
2026-09-10 2:54 ` Binbin Wu
2026-09-08 23:54 ` Binbin Wu
2026-09-09 5:37 ` Binbin Wu
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