Re: [PATCH v7 19/22] riscv: dts: starfive: Add initial StarFive JH7110 device tree

[Hal Feng <hal.feng@starfivetech.com>]

On Sun, 7 May 2023 18:03:19 +0800, Shengyu Qu wrote:
> Hi Hal,
>> From: Emil Renner Berthing <kernel@esmil.dk>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> new file mode 100644
>> index 000000000000..d484ecdf93f7
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> @@ -0,0 +1,509 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
>> + */
>> +
>> +/dts-v1/;
>> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
>> +#include <dt-bindings/reset/starfive,jh7110-crg.h>
>> +
>> +/ {
[...]
>> +
>> +    soc {
>> +        compatible = "simple-bus";
>> +        interrupt-parent = <&plic>;
> 
> Do we really need this interrupt-parent? Seems it is causing a dependency cycle:
> 
> platform soc: Fixed dependency cycle(s) with /soc/interrupt-controller@c000000
> 
> And seems fu740 dts doesn't have this.

Sorry to reply too late. If we drop this line, we need to add 'interrupt-parent'
to every node which uses interrupt. And I found some other platform did the same
such as 

arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
arch/riscv/boot/dts/canaan/k210.dtsi
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi

Best regards,
Hal

> 
>> +        #address-cells = <2>;
>> +        #size-cells = <2>;
>> +        ranges;
>> +
>> +        clint: timer@2000000 {
>> +            compatible = "starfive,jh7110-clint", "sifive,clint0";
>> +            reg = <0x0 0x2000000 0x0 0x10000>;
>> +            interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
>> +                          <&cpu1_intc 3>, <&cpu1_intc 7>,
>> +                          <&cpu2_intc 3>, <&cpu2_intc 7>,
>> +                          <&cpu3_intc 3>, <&cpu3_intc 7>,
>> +                          <&cpu4_intc 3>, <&cpu4_intc 7>;
>> +        };
>> +
>> +        ccache: cache-controller@2010000 {
>> +            compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
>> +            reg = <0x0 0x2010000 0x0 0x4000>;
>> +            interrupts = <1>, <3>, <4>, <2>;
>> +            cache-block-size = <64>;
>> +            cache-level = <2>;
>> +            cache-sets = <2048>;
>> +            cache-size = <2097152>;
>> +            cache-unified;
>> +        };
>> +
>> +        plic: interrupt-controller@c000000 {
>> +            compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
>> +            reg = <0x0 0xc000000 0x0 0x4000000>;
>> +            interrupts-extended = <&cpu0_intc 11>,
>> +                          <&cpu1_intc 11>, <&cpu1_intc 9>,
>> +                          <&cpu2_intc 11>, <&cpu2_intc 9>,
>> +                          <&cpu3_intc 11>, <&cpu3_intc 9>,
>> +                          <&cpu4_intc 11>, <&cpu4_intc 9>;
>> +            interrupt-controller;
>> +            #interrupt-cells = <1>;
>> +            #address-cells = <0>;
>> +            riscv,ndev = <136>;
>> +        };
>> +
>> +        uart0: serial@10000000 {
>> +            compatible = "snps,dw-apb-uart";
>> +            reg = <0x0 0x10000000 0x0 0x10000>;
>> +            clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
>> +                 <&syscrg JH7110_SYSCLK_UART0_APB>;
>> +            clock-names = "baudclk", "apb_pclk";
>> +            resets = <&syscrg JH7110_SYSRST_UART0_APB>;
>> +            interrupts = <32>;
>> +            reg-io-width = <4>;
>> +            reg-shift = <2>;
>> +            status = "disabled";
>> +        };
>> +
[...]