From: Alexandre Mergnat <amergnat@baylibre.com>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
mturquette@baylibre.com
Cc: sboyd@kernel.org, matthias.bgg@gmail.com, wenst@chromium.org,
chun-jie.chen@mediatek.com, mandyjh.liu@mediatek.com,
miles.chen@mediatek.com, zhaojh329@gmail.com,
daniel@makrotopia.org, nfraprado@collabora.com,
rex-bc.chen@mediatek.com, Garmin.Chang@mediatek.com,
msp@baylibre.com, yangyingliang@huawei.com,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, kernel@collabora.com
Subject: Re: [PATCH v2 0/2] clk/mediatek: Adjustments for MSDC rate accuracy
Date: Wed, 17 May 2023 18:52:56 +0200 [thread overview]
Message-ID: <94f8af4a-2555-052d-d04a-a0e54e0e2d13@baylibre.com> (raw)
In-Reply-To: <20230516135205.372951-1-angelogioacchino.delregno@collabora.com>
On 16/05/2023 15:52, AngeloGioacchino Del Regno wrote:
> Changes in v2:
> - Extended the changes in this series to MT8365 clocks
>
> This series stops unconditionally forcing CLK_SET_RATE_PARENT on
> MediaTek muxes, as that should be set in the clock driver for each
> clock requiring it, and removes CLK_SET_PARENT from all MSDC core
> clocks to allow mtk-sd to select the right clock parent when doing
> mclk setting, improving the rate accuracy and avoiding both under
> and overclocks of the eMMC/SD/SDIO card, both improving performance
> and stability of the attached storage.
>
> This series was successfully tested on MT8173, MT8192, MT8195.
>
> AngeloGioacchino Del Regno (2):
> clk: mediatek: mux: Stop forcing CLK_SET_RATE_PARENT flag
> clk: mediatek: Remove CLK_SET_PARENT from all MSDC core clocks
>
> drivers/clk/mediatek/clk-mt6765.c | 20 +++++-----
> drivers/clk/mediatek/clk-mt6779.c | 24 +++++------
> drivers/clk/mediatek/clk-mt7981-topckgen.c | 12 +++---
> drivers/clk/mediatek/clk-mt7986-topckgen.c | 12 +++---
> drivers/clk/mediatek/clk-mt8173-topckgen.c | 24 +++++------
> drivers/clk/mediatek/clk-mt8183.c | 22 ++++++-----
> drivers/clk/mediatek/clk-mt8186-topckgen.c | 24 +++++------
> drivers/clk/mediatek/clk-mt8188-topckgen.c | 40 +++++++++++--------
> drivers/clk/mediatek/clk-mt8192.c | 23 +++++------
> drivers/clk/mediatek/clk-mt8195-topckgen.c | 46 +++++++++++++---------
> drivers/clk/mediatek/clk-mt8365.c | 38 +++++++++---------
> drivers/clk/mediatek/clk-mux.c | 2 +-
> 12 files changed, 155 insertions(+), 132 deletions(-)
>
I will try to test it next week on MT8365 SoC.
--
Regards,
Alexandre
WARNING: multiple messages have this Message-ID (diff)
From: Alexandre Mergnat <amergnat@baylibre.com>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
mturquette@baylibre.com
Cc: sboyd@kernel.org, matthias.bgg@gmail.com, wenst@chromium.org,
chun-jie.chen@mediatek.com, mandyjh.liu@mediatek.com,
miles.chen@mediatek.com, zhaojh329@gmail.com,
daniel@makrotopia.org, nfraprado@collabora.com,
rex-bc.chen@mediatek.com, Garmin.Chang@mediatek.com,
msp@baylibre.com, yangyingliang@huawei.com,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, kernel@collabora.com
Subject: Re: [PATCH v2 0/2] clk/mediatek: Adjustments for MSDC rate accuracy
Date: Wed, 17 May 2023 18:52:56 +0200 [thread overview]
Message-ID: <94f8af4a-2555-052d-d04a-a0e54e0e2d13@baylibre.com> (raw)
In-Reply-To: <20230516135205.372951-1-angelogioacchino.delregno@collabora.com>
On 16/05/2023 15:52, AngeloGioacchino Del Regno wrote:
> Changes in v2:
> - Extended the changes in this series to MT8365 clocks
>
> This series stops unconditionally forcing CLK_SET_RATE_PARENT on
> MediaTek muxes, as that should be set in the clock driver for each
> clock requiring it, and removes CLK_SET_PARENT from all MSDC core
> clocks to allow mtk-sd to select the right clock parent when doing
> mclk setting, improving the rate accuracy and avoiding both under
> and overclocks of the eMMC/SD/SDIO card, both improving performance
> and stability of the attached storage.
>
> This series was successfully tested on MT8173, MT8192, MT8195.
>
> AngeloGioacchino Del Regno (2):
> clk: mediatek: mux: Stop forcing CLK_SET_RATE_PARENT flag
> clk: mediatek: Remove CLK_SET_PARENT from all MSDC core clocks
>
> drivers/clk/mediatek/clk-mt6765.c | 20 +++++-----
> drivers/clk/mediatek/clk-mt6779.c | 24 +++++------
> drivers/clk/mediatek/clk-mt7981-topckgen.c | 12 +++---
> drivers/clk/mediatek/clk-mt7986-topckgen.c | 12 +++---
> drivers/clk/mediatek/clk-mt8173-topckgen.c | 24 +++++------
> drivers/clk/mediatek/clk-mt8183.c | 22 ++++++-----
> drivers/clk/mediatek/clk-mt8186-topckgen.c | 24 +++++------
> drivers/clk/mediatek/clk-mt8188-topckgen.c | 40 +++++++++++--------
> drivers/clk/mediatek/clk-mt8192.c | 23 +++++------
> drivers/clk/mediatek/clk-mt8195-topckgen.c | 46 +++++++++++++---------
> drivers/clk/mediatek/clk-mt8365.c | 38 +++++++++---------
> drivers/clk/mediatek/clk-mux.c | 2 +-
> 12 files changed, 155 insertions(+), 132 deletions(-)
>
I will try to test it next week on MT8365 SoC.
--
Regards,
Alexandre
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next prev parent reply other threads:[~2023-05-17 16:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-16 13:52 [PATCH v2 0/2] clk/mediatek: Adjustments for MSDC rate accuracy AngeloGioacchino Del Regno
2023-05-16 13:52 ` AngeloGioacchino Del Regno
2023-05-16 13:52 ` [PATCH v2 1/2] clk: mediatek: mux: Stop forcing CLK_SET_RATE_PARENT flag AngeloGioacchino Del Regno
2023-05-16 13:52 ` AngeloGioacchino Del Regno
2023-05-23 10:54 ` Alexandre Mergnat
2023-05-23 10:54 ` Alexandre Mergnat
2023-06-13 1:20 ` Stephen Boyd
2023-06-13 1:20 ` Stephen Boyd
2023-05-16 13:52 ` [PATCH v2 2/2] clk: mediatek: Remove CLK_SET_PARENT from all MSDC core clocks AngeloGioacchino Del Regno
2023-05-16 13:52 ` AngeloGioacchino Del Regno
2023-05-23 10:58 ` Alexandre Mergnat
2023-05-23 10:58 ` Alexandre Mergnat
2023-06-13 1:20 ` Stephen Boyd
2023-06-13 1:20 ` Stephen Boyd
2023-05-17 16:52 ` Alexandre Mergnat [this message]
2023-05-17 16:52 ` [PATCH v2 0/2] clk/mediatek: Adjustments for MSDC rate accuracy Alexandre Mergnat
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