From: "Duan, Zhenzhong" <zhenzhong.duan@intel.com>
To: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "alex.williamson@redhat.com" <alex.williamson@redhat.com>,
"clg@redhat.com" <clg@redhat.com>,
"eric.auger@redhat.com" <eric.auger@redhat.com>,
"mst@redhat.com" <mst@redhat.com>,
"peterx@redhat.com" <peterx@redhat.com>,
"jasowang@redhat.com" <jasowang@redhat.com>,
"jgg@nvidia.com" <jgg@nvidia.com>,
"nicolinc@nvidia.com" <nicolinc@nvidia.com>,
"joao.m.martins@oracle.com" <joao.m.martins@oracle.com>,
"kevin.tian@intel.com" <kevin.tian@intel.com>,
"yi.l.liu@intel.com" <yi.l.liu@intel.com>,
"chao.p.peng@intel.com" <chao.p.peng@intel.com>,
Paolo Bonzini <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Subject: Re: [PATCH v2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode
Date: Thu, 8 Aug 2024 20:31:59 +0800 [thread overview]
Message-ID: <9ae22a85-9bf5-3d45-2d19-c3371aecf42e@intel.com> (raw)
In-Reply-To: <cba7ec79-e2db-4919-a1ea-553ed20e0e2b@eviden.com>
On 8/6/2024 2:35 PM, CLEMENT MATHIEU--DRIF wrote:
>
> On 05/08/2024 08:27, Zhenzhong Duan wrote:
>> Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe.
>>
>>
>> Add an new element scalable_mode in IntelIOMMUState to mark scalable
>> modern mode, this element will be exposed as an intel_iommu property
>> finally.
>>
>> For now, it's only a placehholder and used for address width
>> compatibility check and block host device passthrough until nesting
>> is supported.
>>
>> Signed-off-by: Yi Liu <yi.l.liu@intel.com>
>> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
>> ---
>> include/hw/i386/intel_iommu.h | 1 +
>> hw/i386/intel_iommu.c | 12 +++++++++---
>> 2 files changed, 10 insertions(+), 3 deletions(-)
>>
>> diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
>> index 1eb05c29fc..788ed42477 100644
>> --- a/include/hw/i386/intel_iommu.h
>> +++ b/include/hw/i386/intel_iommu.h
>> @@ -262,6 +262,7 @@ struct IntelIOMMUState {
>>
>> bool caching_mode; /* RO - is cap CM enabled? */
>> bool scalable_mode; /* RO - is Scalable Mode supported? */
>> + bool scalable_modern; /* RO - is modern SM supported? */
>> bool snoop_control; /* RO - is SNP filed supported? */
>>
>> dma_addr_t root; /* Current root table pointer */
>> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
>> index e3465fc27d..c1382a5651 100644
>> --- a/hw/i386/intel_iommu.c
>> +++ b/hw/i386/intel_iommu.c
>> @@ -3872,7 +3872,13 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIOMMUDevice *hiod,
>> return false;
>> }
>>
>> - return true;
>> + if (!s->scalable_modern) {
>> + /* All checks requested by VTD non-modern mode pass */
>> + return true;
>> + }
>> +
>> + error_setg(errp, "host device is unsupported in scalable modern mode yet");
>> + return false;
>> }
>>
>> static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn,
>> @@ -4262,9 +4268,9 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)
>> }
>> }
>>
>> - /* Currently only address widths supported are 39 and 48 bits */
>> if ((s->aw_bits != VTD_HOST_AW_39BIT) &&
>> - (s->aw_bits != VTD_HOST_AW_48BIT)) {
>> + (s->aw_bits != VTD_HOST_AW_48BIT) &&
>> + !s->scalable_modern) {
> Why does scalable_modern allow to use a value other than 39 or 48?
> Is it safe?
The check for scalable_modern is in patch14:
if ((s->aw_bits != VTD_HOST_AW_48BIT) && s->scalable_modern) {
error_setg(errp, "Supported values for aw-bits are: %d", VTD_HOST_AW_48BIT);
return false;
}
Let me know if you prefer to move it in this patch.
Thanks
Zhenzhong
next prev parent reply other threads:[~2024-08-08 12:32 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-05 6:27 [PATCH v2 00/17] intel_iommu: Enable stage-1 translation for emulated device Zhenzhong Duan
2024-08-05 6:27 ` [PATCH v2 01/17] intel_iommu: Use the latest fault reasons defined by spec Zhenzhong Duan
2024-08-13 10:57 ` Yi Liu
2024-08-14 2:30 ` Duan, Zhenzhong
2024-08-05 6:27 ` [PATCH v2 02/17] intel_iommu: Make pasid entry type check accurate Zhenzhong Duan
2024-08-13 12:10 ` Yi Liu
2024-08-05 6:27 ` [PATCH v2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode Zhenzhong Duan
2024-08-06 6:35 ` CLEMENT MATHIEU--DRIF
2024-08-08 12:31 ` Duan, Zhenzhong [this message]
2024-08-08 15:04 ` CLEMENT MATHIEU--DRIF
2024-08-13 2:20 ` Duan, Zhenzhong
2024-08-13 5:22 ` CLEMENT MATHIEU--DRIF
2024-08-13 6:26 ` Duan, Zhenzhong
2024-08-13 6:58 ` CLEMENT MATHIEU--DRIF
2024-08-05 6:27 ` [PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation Zhenzhong Duan
2024-08-06 6:35 ` CLEMENT MATHIEU--DRIF
2024-08-08 12:40 ` Duan, Zhenzhong
2024-08-08 14:56 ` CLEMENT MATHIEU--DRIF
2024-08-13 2:12 ` Duan, Zhenzhong
2024-08-13 7:13 ` CLEMENT MATHIEU--DRIF
2024-08-13 7:18 ` CLEMENT MATHIEU--DRIF
2024-08-14 12:36 ` Yi Liu
2024-08-15 5:48 ` Duan, Zhenzhong
2024-08-19 9:03 ` Yi Liu
2024-08-05 6:27 ` [PATCH v2 05/17] intel_iommu: Rename slpte to pte Zhenzhong Duan
2024-08-05 6:27 ` [PATCH v2 06/17] intel_iommu: Implement stage-1 translation Zhenzhong Duan
2024-08-05 6:27 ` [PATCH v2 07/17] intel_iommu: Check if the input address is canonical Zhenzhong Duan
2024-08-14 12:02 ` Yi Liu
2024-08-16 2:19 ` Duan, Zhenzhong
2024-08-05 6:27 ` [PATCH v2 08/17] intel_iommu: Set accessed and dirty bits during first stage translation Zhenzhong Duan
2024-08-14 11:45 ` Yi Liu
2024-08-16 2:37 ` Duan, Zhenzhong
2024-08-16 4:29 ` CLEMENT MATHIEU--DRIF
2024-08-16 4:22 ` CLEMENT MATHIEU--DRIF
2024-08-05 6:27 ` [PATCH v2 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation Zhenzhong Duan
2024-08-05 6:27 ` [PATCH v2 10/17] intel_iommu: Process PASID-based " Zhenzhong Duan
2024-08-05 6:27 ` [PATCH v2 11/17] intel_iommu: Add an internal API to find an address space with PASID Zhenzhong Duan
2024-08-05 6:27 ` [PATCH v2 12/17] intel_iommu: Add support for PASID-based device IOTLB invalidation Zhenzhong Duan
2024-08-05 6:27 ` [PATCH v2 13/17] intel_iommu: piotlb invalidation should notify unmap Zhenzhong Duan
2024-08-19 9:35 ` Yi Liu
2024-08-19 9:57 ` Duan, Zhenzhong
2024-08-20 2:43 ` Yi Liu
2024-08-20 2:54 ` Duan, Zhenzhong
2024-08-05 6:27 ` [PATCH v2 14/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode Zhenzhong Duan
2024-08-06 6:35 ` CLEMENT MATHIEU--DRIF
2024-08-14 12:26 ` Yi Liu
2024-08-15 3:39 ` Duan, Zhenzhong
2024-08-05 6:27 ` [PATCH v2 15/17] intel_iommu: Modify x-scalable-mode to be string option to expose scalable modern mode Zhenzhong Duan
2024-08-06 6:34 ` CLEMENT MATHIEU--DRIF
2024-08-08 12:28 ` Duan, Zhenzhong
2024-08-05 6:27 ` [PATCH v2 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting Zhenzhong Duan
2024-08-06 6:33 ` CLEMENT MATHIEU--DRIF
2024-08-14 12:22 ` Yi Liu
2024-08-15 3:46 ` Duan, Zhenzhong
2024-08-19 9:30 ` Yi Liu
2024-08-19 9:41 ` Duan, Zhenzhong
2024-08-19 12:16 ` Yi Liu
2024-08-05 6:27 ` [PATCH v2 17/17] tests/qtest: Add intel-iommu test Zhenzhong Duan
2024-08-12 7:29 ` Thomas Huth
2024-09-10 11:29 ` [PATCH v2 00/17] intel_iommu: Enable stage-1 translation for emulated device CLEMENT MATHIEU--DRIF
2024-09-11 2:29 ` Duan, Zhenzhong
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