All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Michał Grzelak" <michal.grzelak@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH 1/6] drm/i915/gmbus: Rename GPIO pins
Date: Tue, 23 Jun 2026 16:43:31 +0200 (CEST)	[thread overview]
Message-ID: <9be069dc-e1f0-bf15-7506-b40fa867c71e@intel.com> (raw)
In-Reply-To: <20260623125111.6632-2-ville.syrjala@linux.intel.com>

[-- Attachment #1: Type: text/plain, Size: 6241 bytes --]

On Tue, 23 Jun 2026, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Replace the alphabetical GPIOA,GPIOB,... with numeric
> GPIO_0,GPIO_1,... This makes the naming scheme agree with
> BSpec. No idea why the alphabetical naming was originally
> chosen as BSpec never used that convention for the GPIO pins.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

How do you see in general adding BSpec no. into trailers, here eg.
49306, 49311 or 68971? Does it make sense, or not really?

Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>

BR,
Michał

> ---
> drivers/gpu/drm/i915/display/intel_gmbus.c | 124 ++++++++++-----------
> 1 file changed, 62 insertions(+), 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index 049157c41fe2..9990e6391b03 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -54,21 +54,21 @@ struct intel_gmbus {
> };
>
> enum gmbus_gpio {
> -	GPIOA,
> -	GPIOB,
> -	GPIOC,
> -	GPIOD,
> -	GPIOE,
> -	GPIOF,
> -	GPIOG,
> -	GPIOH,
> -	__GPIOI_UNUSED,
> -	GPIOJ,
> -	GPIOK,
> -	GPIOL,
> -	GPIOM,
> -	GPION,
> -	GPIOO,
> +	GPIO_0,
> +	GPIO_1,
> +	GPIO_2,
> +	GPIO_3,
> +	GPIO_4,
> +	GPIO_5,
> +	GPIO_6,
> +	GPIO_7,
> +	GPIO_8,
> +	GPIO_9,
> +	GPIO_10,
> +	GPIO_11,
> +	GPIO_12,
> +	GPIO_13,
> +	GPIO_14,
> };
>
> struct gmbus_pin {
> @@ -78,77 +78,77 @@ struct gmbus_pin {
>
> /* Map gmbus pin pairs to names and registers. */
> static const struct gmbus_pin gmbus_pins[] = {
> -	[GMBUS_PIN_SSC] = { "ssc", GPIOB },
> -	[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
> -	[GMBUS_PIN_PANEL] = { "panel", GPIOC },
> -	[GMBUS_PIN_DPC] = { "dpc", GPIOD },
> -	[GMBUS_PIN_DPB] = { "dpb", GPIOE },
> -	[GMBUS_PIN_DPD] = { "dpd", GPIOF },
> +	[GMBUS_PIN_SSC] = { "ssc", GPIO_1 },
> +	[GMBUS_PIN_VGADDC] = { "vga", GPIO_0 },
> +	[GMBUS_PIN_PANEL] = { "panel", GPIO_2 },
> +	[GMBUS_PIN_DPC] = { "dpc", GPIO_3 },
> +	[GMBUS_PIN_DPB] = { "dpb", GPIO_4 },
> +	[GMBUS_PIN_DPD] = { "dpd", GPIO_5 },
> };
>
> static const struct gmbus_pin gmbus_pins_bdw[] = {
> -	[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
> -	[GMBUS_PIN_DPC] = { "dpc", GPIOD },
> -	[GMBUS_PIN_DPB] = { "dpb", GPIOE },
> -	[GMBUS_PIN_DPD] = { "dpd", GPIOF },
> +	[GMBUS_PIN_VGADDC] = { "vga", GPIO_0 },
> +	[GMBUS_PIN_DPC] = { "dpc", GPIO_3 },
> +	[GMBUS_PIN_DPB] = { "dpb", GPIO_4 },
> +	[GMBUS_PIN_DPD] = { "dpd", GPIO_5 },
> };
>
> static const struct gmbus_pin gmbus_pins_skl[] = {
> -	[GMBUS_PIN_DPC] = { "dpc", GPIOD },
> -	[GMBUS_PIN_DPB] = { "dpb", GPIOE },
> -	[GMBUS_PIN_DPD] = { "dpd", GPIOF },
> +	[GMBUS_PIN_DPC] = { "dpc", GPIO_3 },
> +	[GMBUS_PIN_DPB] = { "dpb", GPIO_4 },
> +	[GMBUS_PIN_DPD] = { "dpd", GPIO_5 },
> };
>
> static const struct gmbus_pin gmbus_pins_bxt[] = {
> -	[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
> -	[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
> -	[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
> +	[GMBUS_PIN_1_BXT] = { "dpb", GPIO_1 },
> +	[GMBUS_PIN_2_BXT] = { "dpc", GPIO_2 },
> +	[GMBUS_PIN_3_BXT] = { "misc", GPIO_3 },
> };
>
> static const struct gmbus_pin gmbus_pins_cnp[] = {
> -	[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
> -	[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
> -	[GMBUS_PIN_3_BXT] = { "misc", GPIOD },
> -	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> +	[GMBUS_PIN_1_BXT] = { "dpb", GPIO_1 },
> +	[GMBUS_PIN_2_BXT] = { "dpc", GPIO_2 },
> +	[GMBUS_PIN_3_BXT] = { "misc", GPIO_3 },
> +	[GMBUS_PIN_4_CNP] = { "dpd", GPIO_4 },
> };
>
> static const struct gmbus_pin gmbus_pins_icp[] = {
> -	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> -	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> -	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> -	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> -	[GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> -	[GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> -	[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> -	[GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
> -	[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
> +	[GMBUS_PIN_1_BXT] = { "dpa", GPIO_1 },
> +	[GMBUS_PIN_2_BXT] = { "dpb", GPIO_2 },
> +	[GMBUS_PIN_3_BXT] = { "dpc", GPIO_3 },
> +	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIO_9 },
> +	[GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIO_10 },
> +	[GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIO_11 },
> +	[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIO_12 },
> +	[GMBUS_PIN_13_TC5_TGP] = { "tc5", GPIO_13 },
> +	[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIO_14 },
> };
>
> static const struct gmbus_pin gmbus_pins_dg1[] = {
> -	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> -	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> -	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> -	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> +	[GMBUS_PIN_1_BXT] = { "dpa", GPIO_1 },
> +	[GMBUS_PIN_2_BXT] = { "dpb", GPIO_2 },
> +	[GMBUS_PIN_3_BXT] = { "dpc", GPIO_3 },
> +	[GMBUS_PIN_4_CNP] = { "dpd", GPIO_4 },
> };
>
> static const struct gmbus_pin gmbus_pins_dg2[] = {
> -	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> -	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> -	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> -	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> -	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> +	[GMBUS_PIN_1_BXT] = { "dpa", GPIO_1 },
> +	[GMBUS_PIN_2_BXT] = { "dpb", GPIO_2 },
> +	[GMBUS_PIN_3_BXT] = { "dpc", GPIO_3 },
> +	[GMBUS_PIN_4_CNP] = { "dpd", GPIO_4 },
> +	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIO_9 },
> };
>
> static const struct gmbus_pin gmbus_pins_mtp[] = {
> -	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> -	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> -	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> -	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
> -	[GMBUS_PIN_5_MTP] = { "dpe", GPIOF },
> -	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> -	[GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> -	[GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> -	[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> +	[GMBUS_PIN_1_BXT] = { "dpa", GPIO_1 },
> +	[GMBUS_PIN_2_BXT] = { "dpb", GPIO_2 },
> +	[GMBUS_PIN_3_BXT] = { "dpc", GPIO_3 },
> +	[GMBUS_PIN_4_CNP] = { "dpd", GPIO_4 },
> +	[GMBUS_PIN_5_MTP] = { "dpe", GPIO_5 },
> +	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIO_9 },
> +	[GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIO_10 },
> +	[GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIO_11 },
> +	[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIO_12 },
> };
>
> static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display,
> -- 
> 2.53.0
>
>

  reply	other threads:[~2026-06-23 14:43 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-23 12:51 [PATCH 0/6] drm/i915: Clean up GPIO pin stuff Ville Syrjala
2026-06-23 12:51 ` [PATCH 1/6] drm/i915/gmbus: Rename GPIO pins Ville Syrjala
2026-06-23 14:43   ` Michał Grzelak [this message]
2026-06-23 12:51 ` [PATCH 2/6] drm/i915/gmbus: s/gmbus_pins_bdw/gmbus_pins_lpt/ Ville Syrjala
2026-06-23 14:43   ` Michał Grzelak
2026-06-23 12:51 ` [PATCH 3/6] drm/i915/gmbus: Add gmbus_pins_lpt_lp[] Ville Syrjala
2026-06-23 14:45   ` Michał Grzelak
2026-06-23 12:51 ` [PATCH 4/6] drm/i915/gmbus: s/gmbus_pins_skl/gmbus_pins_spt/ Ville Syrjala
2026-06-23 14:45   ` Michał Grzelak
2026-06-23 12:51 ` [PATCH 5/6] drm/i915/gmbus: Drop the platform suffixes from GMBUS pins Ville Syrjala
2026-06-23 14:11   ` [PATCH v2 " Ville Syrjala
2026-06-23 14:45     ` Michał Grzelak
2026-06-23 12:51 ` [PATCH 6/6] drm/i915/hdmi: Remove CNP port F leftovers Ville Syrjala
2026-06-23 14:45   ` Michał Grzelak
2026-06-23 13:30 ` ✓ CI.KUnit: success for drm/i915: Clean up GPIO pin stuff Patchwork
2026-06-23 13:50 ` ✗ Fi.CI.BUILD: failure " Patchwork
2026-06-23 14:18 ` ✓ CI.KUnit: success for drm/i915: Clean up GPIO pin stuff (rev2) Patchwork
2026-06-23 15:04 ` ✓ i915.CI.BAT: " Patchwork
2026-06-23 15:14 ` ✓ Xe.CI.BAT: " Patchwork
2026-06-23 20:12 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-06-23 22:38 ` ✗ i915.CI.Full: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=9be069dc-e1f0-bf15-7506-b40fa867c71e@intel.com \
    --to=michal.grzelak@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=ville.syrjala@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.