From: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
To: Brian Cain <brian.cain@oss.qualcomm.com>, qemu-devel@nongnu.org
Cc: Laurent Vivier <laurent@vivier.eu>, Helge Deller <deller@gmx.de>
Subject: Re: [PATCH v2 09/11] target/hexagon: implement direct-to-guest interrupt delivery
Date: Tue, 1 Sep 2026 11:26:27 -0700 [thread overview]
Message-ID: <9c1900c5-a1e1-4f8b-9a1c-d413ef916d09@oss.qualcomm.com> (raw)
In-Reply-To: <20260901173353.200474-10-brian.cain@oss.qualcomm.com>
On 9/1/2026 10:33 AM, Brian Cain wrote:
> Interrupts 3 through 5 are routed to guest mode when CCR:GIE and the
> matching CCR:VV bit are set. Enter through GEVB rather than EVB,
> record the pre-entry state in GSR and the return address in GELR, and
> read the vector ID from the l2vic.
>
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> ---
> target/hexagon/reg_fields_def.h.inc | 7 +++
> target/hexagon/cpu.c | 5 ++
> target/hexagon/hex_interrupts.c | 91 ++++++++++++++++++++++++++---
> 3 files changed, 96 insertions(+), 7 deletions(-)
>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
next prev parent reply other threads:[~2026-09-01 18:26 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-01 17:33 [PATCH v2 00/11] Hexagon: exception, interrupt, system reg fixes Brian Cain
2026-09-01 17:33 ` [PATCH v2 01/11] target/hexagon: align exceptions for user/sysemu Brian Cain
2026-09-01 17:33 ` [PATCH v2 02/11] tests/tcg/hexagon: check priv instructions raise SIGILL Brian Cain
2026-09-01 17:33 ` [PATCH v2 03/11] hw/intc: clear pending bit on l2vic de-assertion Brian Cain
2026-09-02 21:30 ` Philippe Mathieu-Daudé
2026-09-03 19:33 ` Brian Cain
2026-09-01 17:33 ` [PATCH v2 04/11] target/hexagon: guard writes to unimplemented guest registers Brian Cain
2026-09-01 18:25 ` Pierrick Bouvier
2026-09-01 17:33 ` [PATCH v2 05/11] target/hexagon: take BQL when reading the system pcycle count Brian Cain
2026-09-01 17:33 ` [PATCH v2 06/11] target/hexagon: gate GPCYCLE guest register reads on SSR:CE Brian Cain
2026-09-02 21:16 ` Philippe Mathieu-Daudé
2026-09-03 19:36 ` Brian Cain
2026-09-04 13:19 ` Philippe Mathieu-Daudé
2026-09-01 17:33 ` [PATCH v2 07/11] target/hexagon: read UTIMERLO/UTIMERHI from the global timer Brian Cain
2026-09-02 21:21 ` Philippe Mathieu-Daudé
2026-09-01 17:33 ` [PATCH v2 08/11] target/hexagon: raise imprecise exception on multi-TLB match Brian Cain
2026-09-01 17:33 ` [PATCH v2 09/11] target/hexagon: implement direct-to-guest interrupt delivery Brian Cain
2026-09-01 18:26 ` Pierrick Bouvier [this message]
2026-09-01 17:33 ` [PATCH v2 10/11] target/hexagon: fix iassign{r, w} to cover all threads Brian Cain via qemu development
2026-09-01 17:33 ` [PATCH v2 11/11] tests/functional/hexagon: update to v0.2.12, +test_{interrupts, sys_regs} Brian Cain via qemu development
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