Re: [PATCH v2 06/11] target/hexagon: gate GPCYCLE guest register reads on SSR:CE

["Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>]

Hi Brian,

On 1/9/26 19:33, Brian Cain wrote:
> GPCYCLELO/GPCYCLEHI read as zero unless the cycle counter is enabled
> (SSR:CE), matching the hardware.
> 
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> ---
>   target/hexagon/cpu.c       | 7 +++++--
>   target/hexagon/op_helper.c | 9 ++-------
>   2 files changed, 7 insertions(+), 9 deletions(-)


> diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
> index 23894ff3d28..2cea1927263 100644
> --- a/target/hexagon/op_helper.c
> +++ b/target/hexagon/op_helper.c
> @@ -1912,13 +1912,8 @@ uint64_t HELPER(greg_read_pair)(CPUHexagonState *env, uint32_t reg)
>           return (uint64_t)(env->greg[reg]) |
>                  (((uint64_t)(env->greg[reg + 1])) << 32);
>       }
> -    switch (reg) {
> -    case HEX_GREG_GPCYCLELO:
> -        return hexagon_get_sys_pcycle_count(env);
> -    default:
> -        return (uint64_t)hexagon_greg_read(env, reg) |
> -               ((uint64_t)(hexagon_greg_read(env, reg + 1)) << 32);
> -    }
> +    return (uint64_t)hexagon_greg_read(env, reg) |
> +           ((uint64_t)(hexagon_greg_read(env, reg + 1)) << 32);
>   }

Just curious, does greg_read_pair() work with impair %reg?