Re: [PATCH v2] loongarch/mm: disable WUC for pgprot_writecombine as same as ioremap_wc

[Sui Jingfeng <sui.jingfeng@linux.dev>]

On 2024/12/19 14:34, Icenowy Zheng wrote:
> 在 2024-12-19星期四的 13:49 +0800，Sui Jingfeng写道：
>> On 2024/12/19 12:49, Icenowy Zheng wrote:
>>> 在 2024-12-19星期四的 10:54 +0800，Sui Jingfeng写道：
>>>> On 2024/12/18 20:43, Icenowy Zheng wrote:
>>>>> For the fact of drm/ast's dramatical drop, it's because write
>>>>> to
>>>>> the
>>>>> framebuffer can no longer be reordered.
>>>> No, your understanding is wrong, very very wrong and a big wrong.
>>>>
>>>> It's not because it can't reorder the write. Rather, it's because
>>>> that the CPU can't do write gathering and can't do burst write
>>>> any
>>>> more.
>>> Write gathering is a kind of write reordering,
>>
>> No, your understanding is broken.
>>
>> Write gathering *isn't* a kind of write reordering.
>> Its doesn't have to reorder, it just cache the write operation with
>> the CPU's write buffer.
>>
>>
>>> comparing to strongly
>>> ordered writing (which is literally one byte per write).
>>>
>>>> So do you still think your patch is harmless?
>>> Well, I said that performance w/o correctness is meaningless.
>>
>> The point is that Write-Combine on drm/ast will get both correctness
>> and performance.
> But in general writecombining is broken


Cached coherent ARM64 SoC has similar issue, but they didn't disable
WC in that arch-specific code.

Again, your understanding is broken.


> (if it's broken in one place,
> it's broken and not totally right, and needs to be handled).


No, your logic is completely wrong here.

1) We needs the *hardware* details (not bug phenomenon description) before make
    further judgement.

2) Its very likely that the specific device driver that suffer from the problems
    is broken.

3) Loongson downstream kernel has the write-combine enabled, and all drm drivers
    works very well.

Its just that you guys chase to radeon/andgpu driver, doing the abuse at arch
specific code.


>
-- 
Best regards,
Sui