From: Keir Fraser <keir.fraser@eu.citrix.com>
To: "Tian, Kevin" <kevin.tian@intel.com>,
'Jan Beulich' <jbeulich@novell.com>,
"xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>
Subject: Re: [Patch] x86: enforce strict memory order for x2apic
Date: Thu, 25 Sep 2008 09:36:19 +0100 [thread overview]
Message-ID: <C5010C13.27732%keir.fraser@eu.citrix.com> (raw)
In-Reply-To: <D8078B8B3B09934AA9F8F2D5FB3F28CE08873AF31B@pdsmsx502.ccr.corp.intel.com>
On 25/9/08 09:29, "Tian, Kevin" <kevin.tian@intel.com> wrote:
>> On the other hand you're penalizing LAPIC systems with this, too. I'm
>> not certain that's better than fixing the (incorrect)
>> assumptions just in
>> the x2APIC case.
>
> I agree. I'll revise the patch to add a 'mb()' in x2APIC instead,
> though that may bring a bit overhead to cases when fencing
> is not required, like event check IPI.
To be precise, mb() at top of send_IPI_mask_x2apic(), and wmb() may as well
go from on_selected_cpus() as we can assume send_IPI_mask() is a barrier.
I'll do the patch for this myself.
-- Keir
next prev parent reply other threads:[~2008-09-25 8:36 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-09-25 6:55 [Patch] x86: enforce strict memory order for x2apic Tian, Kevin
2008-09-25 8:24 ` Jan Beulich
2008-09-25 8:29 ` Tian, Kevin
2008-09-25 8:36 ` Keir Fraser [this message]
2008-09-25 8:38 ` Tian, Kevin
2008-09-25 8:40 ` Tian, Kevin
2008-09-25 9:04 ` Keir Fraser
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