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From: Keir Fraser <keir.fraser@eu.citrix.com>
To: Kouya Shimura <kouya@jp.fujitsu.com>
Cc: "xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>
Subject: Re: [PATCH] x86, hvm: Allow delivery of timer interrupts to VCPUs != 0.
Date: Fri, 03 Jul 2009 10:33:19 +0100	[thread overview]
Message-ID: <C6738EEF.EC25%keir.fraser@eu.citrix.com> (raw)
In-Reply-To: <7kzlbmmc69.fsf@pingu.sky.yk.fujitsu.co.jp>

On 03/07/2009 08:57, "Kouya Shimura" <kouya@jp.fujitsu.com> wrote:

> - I'm afraid that d->arch.hvm_domain.i8259_target == NULL

If VCPUj is != NULL then VCPUi is also != NULL for all i < j. So this is not
a concern: there's always a VCPU0 if there are any VCPUs at all.

> - if vcpu[0] is halted and all vlapic.LVT0 are masked,
>   timer doesn't work even when vlapic will be unmasked
>   not as ExtINT mode.

Not sure what you mean? If legacy IRQs are routed through the IOAPIC then it
does not matter whether LAPIC.LVT0 is masked. And __vlapic_accept_pic_intr()
correctly handles that. If virtual wire mode is not through the IOAPIC then
of course LVT0 mask does matter, but I think we have that case correct too.

> So, I think that the last __vlapic_accept_pic_intr'ed vcpu
> should be reserved in d->arch.hvm_domain.i8259_target.

I don't think the logic needs to change.

 -- Keir

  reply	other threads:[~2009-07-03  9:33 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-07-03  4:27 [PATCH] x86, hvm: Allow delivery of timer interrupts to VCPUs != 0 Kouya Shimura
2009-07-03  6:41 ` Keir Fraser
2009-07-03  7:57   ` Kouya Shimura
2009-07-03  9:33     ` Keir Fraser [this message]
2009-07-06  7:05       ` Kouya Shimura
2009-07-06  7:07         ` [PATCH 1/2] x86, hvm: cleanup hpet.c as well as i8254.c or rtc.c Kouya Shimura
2009-07-06  7:09           ` [PATCH 2/2] x86, hvm: Allow delivery of timer interrupts to VCPUs != 0 Kouya Shimura
2009-07-07 13:21             ` Keir Fraser

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