From: "Nicholas Piggin" <npiggin@gmail.com>
To: "Harsh Prateek Bora" <harshpb@linux.ibm.com>, <qemu-ppc@nongnu.org>
Cc: "Caleb Schlossin" <calebs@linux.vnet.ibm.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Frédéric Barrat" <fbarrat@linux.ibm.com>,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
qemu-devel@nongnu.org
Subject: Re: [RFC PATCH 03/10] target/ppc: Improve SPR indirect registers
Date: Wed, 29 May 2024 10:13:04 +1000 [thread overview]
Message-ID: <D1LOZVAI9RGP.315U4KSV0NNW@gmail.com> (raw)
In-Reply-To: <eed27a5e-6b32-45e0-8d76-51371fadc976@linux.ibm.com>
On Tue May 28, 2024 at 4:50 PM AEST, Harsh Prateek Bora wrote:
>
> Hi Nick,
>
> On 5/26/24 17:56, Nicholas Piggin wrote:
> > SPRC/SPRD were recently added to all BookS CPUs supported, but
> > they are only tested on POWER9 and POWER10, so restrict them to
> > those CPUs.
> >
>
> Hope you mean to restrict to P9/10 for both spapr and pnv or just pnv ?
For pnv, but they are hypervisor registers so they can not be
accessed with spapr.
[...]
> > @@ -321,11 +322,25 @@ void helper_store_sprc(CPUPPCState *env, target_ulong val)
> >
> > target_ulong helper_load_sprd(CPUPPCState *env)
> > {
> > + PowerPCCPU *cpu = env_archcpu(env);
> > + PnvCore *pc = pnv_cpu_state(cpu)->core;
>
> We may want to avoid creating local variable cpu here also like previous
> patches.
Since we have a maze of pointers and types, sometimes I like to
write the types down, but maybe that's just me :P
> However, is this helper meant to be accessible for spapr as well ?
Right, it's not. I *think* it should be okay to do this since it
should never be reached by spapr.
Thanks,
Nick
next prev parent reply other threads:[~2024-05-29 0:14 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-26 12:26 [RFC PATCH 00/10] ppc/pnv: Better big-core model, lpar-per-core, PC unit Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 01/10] ppc/pnv: Add pointer from PnvCPUState to PnvCore Nicholas Piggin
2024-05-27 15:23 ` Cédric Le Goater
2024-05-28 6:19 ` Harsh Prateek Bora
2024-05-26 12:26 ` [RFC PATCH 02/10] ppc/pnv: Move timebase state into PnvCore Nicholas Piggin
2024-05-28 6:28 ` Harsh Prateek Bora
2024-05-28 7:52 ` Cédric Le Goater
2024-05-29 0:19 ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 03/10] target/ppc: Improve SPR indirect registers Nicholas Piggin
2024-05-28 6:50 ` Harsh Prateek Bora
2024-05-29 0:13 ` Nicholas Piggin [this message]
2024-05-26 12:26 ` [RFC PATCH 04/10] ppc/pnv: specialise init for powernv8/9/10 machines Nicholas Piggin
2024-05-28 7:10 ` Harsh Prateek Bora
2024-05-28 7:45 ` Cédric Le Goater
2024-05-29 0:18 ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 05/10] ppc/pnv: Extend chip_pir class method to TIR as well Nicholas Piggin
2024-05-28 8:32 ` Harsh Prateek Bora
2024-05-29 0:24 ` Nicholas Piggin
2024-05-29 6:30 ` Cédric Le Goater
2024-05-30 6:38 ` Nicholas Piggin
2024-05-30 6:42 ` Cédric Le Goater
2024-05-26 12:26 ` [RFC PATCH 06/10] ppc: Add a core_index to CPUPPCState for SMT vCPUs Nicholas Piggin
2024-05-28 8:48 ` Harsh Prateek Bora
2024-05-28 8:52 ` Harsh Prateek Bora
2024-05-29 0:28 ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 07/10] target/ppc: Add helpers to check for SMT sibling threads Nicholas Piggin
2024-05-28 9:16 ` Harsh Prateek Bora
2024-05-29 0:31 ` Nicholas Piggin
2024-05-29 6:34 ` Cédric Le Goater
2024-05-30 6:38 ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 08/10] ppc/pnv: Invert the design for big-core machine modelling Nicholas Piggin
2024-05-29 6:57 ` Cédric Le Goater
2024-05-30 6:52 ` Nicholas Piggin
2024-05-30 7:46 ` Cédric Le Goater
2024-06-03 5:22 ` Nicholas Piggin
2024-05-29 10:49 ` Harsh Prateek Bora
2024-05-26 12:26 ` [RFC PATCH 09/10] ppc/pnv: Implement POWER10 PC xscom registers for direct controls Nicholas Piggin
2024-05-29 7:00 ` Cédric Le Goater
2024-05-30 6:53 ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 10/10] ppc/pnv: Add an LPAR per core machine option Nicholas Piggin
2024-05-29 7:02 ` Cédric Le Goater
2024-05-27 6:25 ` [RFC PATCH 00/10] ppc/pnv: Better big-core model, lpar-per-core, PC unit Cédric Le Goater
2024-05-27 7:32 ` Nicholas Piggin
2024-05-27 7:36 ` Cédric Le Goater
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=D1LOZVAI9RGP.315U4KSV0NNW@gmail.com \
--to=npiggin@gmail.com \
--cc=calebs@linux.vnet.ibm.com \
--cc=clg@kaod.org \
--cc=danielhb413@gmail.com \
--cc=fbarrat@linux.ibm.com \
--cc=harshpb@linux.ibm.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.