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From: "Nicholas Piggin" <npiggin@gmail.com>
To: "Cédric Le Goater" <clg@kaod.org>,
	"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
	qemu-ppc@nongnu.org
Cc: "Caleb Schlossin" <calebs@linux.vnet.ibm.com>,
	"Frédéric Barrat" <fbarrat@linux.ibm.com>,
	"Daniel Henrique Barboza" <danielhb413@gmail.com>,
	qemu-devel@nongnu.org
Subject: Re: [RFC PATCH 02/10] ppc/pnv: Move timebase state into PnvCore
Date: Wed, 29 May 2024 10:19:52 +1000	[thread overview]
Message-ID: <D1LP52PCE3NS.71SEY8XILT96@gmail.com> (raw)
In-Reply-To: <c70671b1-26e7-46a6-8651-99777ae27f36@kaod.org>

On Tue May 28, 2024 at 5:52 PM AEST, Cédric Le Goater wrote:
> On 5/28/24 08:28, Harsh Prateek Bora wrote:
> > 
> > 
> > On 5/26/24 17:56, Nicholas Piggin wrote:
> >> The timebase state machine is per per-core state and can be driven
> >> by any thread in the core. It is currently implemented as a hack
> >> where the state is in a CPU structure and only thread 0's state is
> >> accessed by the chiptod, which limits programming the timebase
> >> side of the state machine to thread 0 of a core.
> >>
> >> Move the state out into PnvCore and share it among all threads.
> >>
> >> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> >> ---
> >>   include/hw/ppc/pnv_core.h    | 17 ++++++++++++
> >>   target/ppc/cpu.h             | 20 --------------
> >>   hw/ppc/pnv_chiptod.c         |  6 ++--
> >>   target/ppc/timebase_helper.c | 53 ++++++++++++++++++++----------------
> >>   4 files changed, 49 insertions(+), 47 deletions(-)
> >>
> >> diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
> >> index 30c1e5b1a3..f434c71547 100644
> >> --- a/include/hw/ppc/pnv_core.h
> >> +++ b/include/hw/ppc/pnv_core.h
> >> @@ -25,6 +25,20 @@
> >>   #include "hw/ppc/pnv.h"
> >>   #include "qom/object.h"
> >> +/* ChipTOD and TimeBase State Machine */
> >> +struct pnv_tod_tbst {
> >> +    int tb_ready_for_tod; /* core TB ready to receive TOD from chiptod */
> >> +    int tod_sent_to_tb;   /* chiptod sent TOD to the core TB */
> >> +
> >> +    /*
> >> +     * "Timers" for async TBST events are simulated by mfTFAC because TFAC
> >> +     * is polled for such events. These are just used to ensure firmware
> >> +     * performs the polling at least a few times.
> >> +     */
> >> +    int tb_state_timer;
> >> +    int tb_sync_pulse_timer;
> >> +};
> >> +
> >>   #define TYPE_PNV_CORE "powernv-cpu-core"
> >>   OBJECT_DECLARE_TYPE(PnvCore, PnvCoreClass,
> >>                       PNV_CORE)
> >> @@ -38,6 +52,9 @@ struct PnvCore {
> >>       uint32_t pir;
> >>       uint32_t hwid;
> >>       uint64_t hrmor;
> >> +
> >> +    struct pnv_tod_tbst pnv_tod_tbst;
> >> +
> > 
> > Now that it is part of struct PnvCore itself, we can drop pnv_ prefix
> > and just call the member variable as tod_tbst ?
>
> yes and rename pnv_tod_tbst using CamelCase please.

Okay will do. That'll look nicer.

Thanks,
Nick


  reply	other threads:[~2024-05-29  0:20 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-26 12:26 [RFC PATCH 00/10] ppc/pnv: Better big-core model, lpar-per-core, PC unit Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 01/10] ppc/pnv: Add pointer from PnvCPUState to PnvCore Nicholas Piggin
2024-05-27 15:23   ` Cédric Le Goater
2024-05-28  6:19   ` Harsh Prateek Bora
2024-05-26 12:26 ` [RFC PATCH 02/10] ppc/pnv: Move timebase state into PnvCore Nicholas Piggin
2024-05-28  6:28   ` Harsh Prateek Bora
2024-05-28  7:52     ` Cédric Le Goater
2024-05-29  0:19       ` Nicholas Piggin [this message]
2024-05-26 12:26 ` [RFC PATCH 03/10] target/ppc: Improve SPR indirect registers Nicholas Piggin
2024-05-28  6:50   ` Harsh Prateek Bora
2024-05-29  0:13     ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 04/10] ppc/pnv: specialise init for powernv8/9/10 machines Nicholas Piggin
2024-05-28  7:10   ` Harsh Prateek Bora
2024-05-28  7:45     ` Cédric Le Goater
2024-05-29  0:18       ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 05/10] ppc/pnv: Extend chip_pir class method to TIR as well Nicholas Piggin
2024-05-28  8:32   ` Harsh Prateek Bora
2024-05-29  0:24     ` Nicholas Piggin
2024-05-29  6:30       ` Cédric Le Goater
2024-05-30  6:38         ` Nicholas Piggin
2024-05-30  6:42           ` Cédric Le Goater
2024-05-26 12:26 ` [RFC PATCH 06/10] ppc: Add a core_index to CPUPPCState for SMT vCPUs Nicholas Piggin
2024-05-28  8:48   ` Harsh Prateek Bora
2024-05-28  8:52     ` Harsh Prateek Bora
2024-05-29  0:28       ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 07/10] target/ppc: Add helpers to check for SMT sibling threads Nicholas Piggin
2024-05-28  9:16   ` Harsh Prateek Bora
2024-05-29  0:31     ` Nicholas Piggin
2024-05-29  6:34   ` Cédric Le Goater
2024-05-30  6:38     ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 08/10] ppc/pnv: Invert the design for big-core machine modelling Nicholas Piggin
2024-05-29  6:57   ` Cédric Le Goater
2024-05-30  6:52     ` Nicholas Piggin
2024-05-30  7:46       ` Cédric Le Goater
2024-06-03  5:22         ` Nicholas Piggin
2024-05-29 10:49   ` Harsh Prateek Bora
2024-05-26 12:26 ` [RFC PATCH 09/10] ppc/pnv: Implement POWER10 PC xscom registers for direct controls Nicholas Piggin
2024-05-29  7:00   ` Cédric Le Goater
2024-05-30  6:53     ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 10/10] ppc/pnv: Add an LPAR per core machine option Nicholas Piggin
2024-05-29  7:02   ` Cédric Le Goater
2024-05-27  6:25 ` [RFC PATCH 00/10] ppc/pnv: Better big-core model, lpar-per-core, PC unit Cédric Le Goater
2024-05-27  7:32   ` Nicholas Piggin
2024-05-27  7:36     ` Cédric Le Goater

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