* [PATCH 1/8] qtest/pci: Enforce balanced iomap/unmap
2024-12-12 8:34 [PATCH 0/8] Add XHCI TR NOOP support, plus PCI, MSIX changes Nicholas Piggin
@ 2024-12-12 8:34 ` Nicholas Piggin
2024-12-12 8:34 ` [PATCH 2/8] qtest/libqos/pci: Fix qpci_msix_enable sharing bar0 Nicholas Piggin
` (6 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Nicholas Piggin @ 2024-12-12 8:34 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, Michael S. Tsirkin, Marcel Apfelbaum,
Fabiano Rosas, Laurent Vivier, Paolo Bonzini, Dmitry Fleytman,
Akihiko Odaki, Sriram Yagnaraman
Add assertions to ensure a BAR is not mapped twice, and only
previously mapped BARs are unmapped. This can help catch some
bugs.
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
tests/qtest/libqos/ahci.h | 1 +
tests/qtest/libqos/pci.h | 2 ++
tests/qtest/libqos/virtio-pci.h | 1 +
tests/qtest/ahci-test.c | 2 ++
tests/qtest/libqos/ahci.c | 6 ++++++
tests/qtest/libqos/pci.c | 32 +++++++++++++++++++++++++++++++-
tests/qtest/libqos/virtio-pci.c | 6 +++++-
7 files changed, 48 insertions(+), 2 deletions(-)
diff --git a/tests/qtest/libqos/ahci.h b/tests/qtest/libqos/ahci.h
index a0487a1557d..5d7e26aee2a 100644
--- a/tests/qtest/libqos/ahci.h
+++ b/tests/qtest/libqos/ahci.h
@@ -575,6 +575,7 @@ QPCIDevice *get_ahci_device(QTestState *qts, uint32_t *fingerprint);
void free_ahci_device(QPCIDevice *dev);
void ahci_pci_enable(AHCIQState *ahci);
void start_ahci_device(AHCIQState *ahci);
+void stop_ahci_device(AHCIQState *ahci);
void ahci_hba_enable(AHCIQState *ahci);
/* Port Management */
diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h
index 83896145235..9dc82ea723a 100644
--- a/tests/qtest/libqos/pci.h
+++ b/tests/qtest/libqos/pci.h
@@ -65,6 +65,8 @@ struct QPCIDevice
{
QPCIBus *bus;
int devfn;
+ bool bars_mapped[6];
+ QPCIBar bars[6];
bool msix_enabled;
QPCIBar msix_table_bar, msix_pba_bar;
uint64_t msix_table_off, msix_pba_off;
diff --git a/tests/qtest/libqos/virtio-pci.h b/tests/qtest/libqos/virtio-pci.h
index f5115cacba2..efdf904b254 100644
--- a/tests/qtest/libqos/virtio-pci.h
+++ b/tests/qtest/libqos/virtio-pci.h
@@ -26,6 +26,7 @@ typedef struct QVirtioPCIDevice {
uint64_t config_msix_addr;
uint32_t config_msix_data;
+ bool enabled;
int bar_idx;
/* VIRTIO 1.0 */
diff --git a/tests/qtest/ahci-test.c b/tests/qtest/ahci-test.c
index 5a1923f721b..b3dae7a8ce4 100644
--- a/tests/qtest/ahci-test.c
+++ b/tests/qtest/ahci-test.c
@@ -1483,6 +1483,8 @@ static void test_reset_pending_callback(void)
/* Wait for throttled write to finish. */
sleep(1);
+ stop_ahci_device(ahci);
+
/* Start again. */
ahci_clean_mem(ahci);
ahci_pci_enable(ahci);
diff --git a/tests/qtest/libqos/ahci.c b/tests/qtest/libqos/ahci.c
index 34a75b7f43b..cfc435b6663 100644
--- a/tests/qtest/libqos/ahci.c
+++ b/tests/qtest/libqos/ahci.c
@@ -217,6 +217,12 @@ void start_ahci_device(AHCIQState *ahci)
qpci_device_enable(ahci->dev);
}
+void stop_ahci_device(AHCIQState *ahci)
+{
+ /* Map AHCI's ABAR (BAR5) */
+ qpci_iounmap(ahci->dev, ahci->hba_bar);
+}
+
/**
* Test and initialize the AHCI's HBA memory areas.
* Initialize and start any ports with devices attached.
diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c
index b23d72346b6..a42ca08261d 100644
--- a/tests/qtest/libqos/pci.c
+++ b/tests/qtest/libqos/pci.c
@@ -93,12 +93,17 @@ QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn)
void qpci_device_init(QPCIDevice *dev, QPCIBus *bus, QPCIAddress *addr)
{
uint16_t vendor_id, device_id;
+ int i;
qpci_device_set(dev, bus, addr->devfn);
vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID);
device_id = qpci_config_readw(dev, PCI_DEVICE_ID);
g_assert(!addr->vendor_id || vendor_id == addr->vendor_id);
g_assert(!addr->device_id || device_id == addr->device_id);
+
+ for (i = 0; i < 6; i++) {
+ g_assert(!dev->bars_mapped[i]);
+ }
}
static uint8_t qpci_find_resource_reserve_capability(QPCIDevice *dev)
@@ -531,6 +536,8 @@ QPCIBar qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr)
uint64_t loc;
g_assert(barno >= 0 && barno <= 5);
+ g_assert(!dev->bars_mapped[barno]);
+
bar_reg = bar_reg_map[barno];
qpci_config_writel(dev, bar_reg, 0xFFFFFFFF);
@@ -574,12 +581,35 @@ QPCIBar qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr)
}
bar.addr = loc;
+
+ dev->bars_mapped[barno] = true;
+ dev->bars[barno] = bar;
+
return bar;
}
void qpci_iounmap(QPCIDevice *dev, QPCIBar bar)
{
- /* FIXME */
+ static const int bar_reg_map[] = {
+ PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2,
+ PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5,
+ };
+ int bar_reg;
+ int i;
+
+ for (i = 0; i < 6; i++) {
+ if (!dev->bars_mapped[i]) {
+ continue;
+ }
+ if (dev->bars[i].addr == bar.addr) {
+ dev->bars_mapped[i] = false;
+ bar_reg = bar_reg_map[i];
+ qpci_config_writel(dev, bar_reg, 0xFFFFFFFF);
+ /* FIXME: the address space is leaked */
+ return;
+ }
+ }
+ g_assert_not_reached();
}
QPCIBar qpci_legacy_iomap(QPCIDevice *dev, uint16_t addr)
diff --git a/tests/qtest/libqos/virtio-pci.c b/tests/qtest/libqos/virtio-pci.c
index 485b8f6b7e0..2b59fb181c9 100644
--- a/tests/qtest/libqos/virtio-pci.c
+++ b/tests/qtest/libqos/virtio-pci.c
@@ -304,11 +304,15 @@ void qvirtio_pci_device_enable(QVirtioPCIDevice *d)
{
qpci_device_enable(d->pdev);
d->bar = qpci_iomap(d->pdev, d->bar_idx, NULL);
+ d->enabled = true;
}
void qvirtio_pci_device_disable(QVirtioPCIDevice *d)
{
- qpci_iounmap(d->pdev, d->bar);
+ if (d->enabled) {
+ qpci_iounmap(d->pdev, d->bar);
+ d->enabled = false;
+ }
}
void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci,
--
2.45.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 2/8] qtest/libqos/pci: Fix qpci_msix_enable sharing bar0
2024-12-12 8:34 [PATCH 0/8] Add XHCI TR NOOP support, plus PCI, MSIX changes Nicholas Piggin
2024-12-12 8:34 ` [PATCH 1/8] qtest/pci: Enforce balanced iomap/unmap Nicholas Piggin
@ 2024-12-12 8:34 ` Nicholas Piggin
2024-12-12 8:34 ` [PATCH 3/8] pci/msix: Implement PBA writes Nicholas Piggin
` (5 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Nicholas Piggin @ 2024-12-12 8:34 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, Michael S. Tsirkin, Marcel Apfelbaum,
Fabiano Rosas, Laurent Vivier, Paolo Bonzini, Dmitry Fleytman,
Akihiko Odaki, Sriram Yagnaraman
Devices where the MSI-X addresses are shared with other MMIO on BAR0
can not use msi_enable because it unmaps and remaps BAR0, which
interferes with device MMIO mappings. xhci-nec is one such device we
would like to test msix with.
Use the BAR iomap tracking structure introduced in the previous change
to have qpci_misx_enable() use existing iomaps if msix bars are
already mapped.
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
tests/qtest/libqos/pci.h | 1 +
tests/qtest/libqos/pci.c | 40 ++++++++++++++++++++++++++++++++++------
2 files changed, 35 insertions(+), 6 deletions(-)
diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h
index 9dc82ea723a..5a7b2454ad5 100644
--- a/tests/qtest/libqos/pci.h
+++ b/tests/qtest/libqos/pci.h
@@ -68,6 +68,7 @@ struct QPCIDevice
bool bars_mapped[6];
QPCIBar bars[6];
bool msix_enabled;
+ bool msix_table_bar_iomap, msix_pba_bar_iomap;
QPCIBar msix_table_bar, msix_pba_bar;
uint64_t msix_table_off, msix_pba_off;
};
diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c
index a42ca08261d..023c1617680 100644
--- a/tests/qtest/libqos/pci.c
+++ b/tests/qtest/libqos/pci.c
@@ -288,15 +288,21 @@ void qpci_msix_enable(QPCIDevice *dev)
table = qpci_config_readl(dev, addr + PCI_MSIX_TABLE);
bir_table = table & PCI_MSIX_FLAGS_BIRMASK;
- dev->msix_table_bar = qpci_iomap(dev, bir_table, NULL);
+ if (dev->bars_mapped[bir_table]) {
+ dev->msix_table_bar = dev->bars[bir_table];
+ } else {
+ dev->msix_table_bar_iomap = true;
+ dev->msix_table_bar = qpci_iomap(dev, bir_table, NULL);
+ }
dev->msix_table_off = table & ~PCI_MSIX_FLAGS_BIRMASK;
table = qpci_config_readl(dev, addr + PCI_MSIX_PBA);
bir_pba = table & PCI_MSIX_FLAGS_BIRMASK;
- if (bir_pba != bir_table) {
- dev->msix_pba_bar = qpci_iomap(dev, bir_pba, NULL);
+ if (dev->bars_mapped[bir_pba]) {
+ dev->msix_pba_bar = dev->bars[bir_pba];
} else {
- dev->msix_pba_bar = dev->msix_table_bar;
+ dev->msix_pba_bar_iomap = true;
+ dev->msix_pba_bar = qpci_iomap(dev, bir_pba, NULL);
}
dev->msix_pba_off = table & ~PCI_MSIX_FLAGS_BIRMASK;
@@ -307,6 +313,7 @@ void qpci_msix_disable(QPCIDevice *dev)
{
uint8_t addr;
uint16_t val;
+ uint32_t table;
g_assert(dev->msix_enabled);
addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX, 0);
@@ -315,10 +322,31 @@ void qpci_msix_disable(QPCIDevice *dev)
qpci_config_writew(dev, addr + PCI_MSIX_FLAGS,
val & ~PCI_MSIX_FLAGS_ENABLE);
- if (dev->msix_pba_bar.addr != dev->msix_table_bar.addr) {
+ if (dev->msix_pba_bar_iomap) {
+ dev->msix_pba_bar_iomap = false;
qpci_iounmap(dev, dev->msix_pba_bar);
+ } else {
+ /*
+ * If we had reused an existing iomap, ensure it is still mapped
+ * otherwise it would be a bug if it were unmapped before msix is
+ * disabled. A refcounting iomap implementation could avoid this
+ * issue entirely, but let's wait until that's needed.
+ */
+ uint8_t bir_pba;
+ table = qpci_config_readl(dev, addr + PCI_MSIX_PBA);
+ bir_pba = table & PCI_MSIX_FLAGS_BIRMASK;
+ g_assert(dev->bars_mapped[bir_pba]);
+ }
+
+ if (dev->msix_table_bar_iomap) {
+ dev->msix_table_bar_iomap = false;
+ qpci_iounmap(dev, dev->msix_table_bar);
+ } else {
+ uint8_t bir_table;
+ table = qpci_config_readl(dev, addr + PCI_MSIX_TABLE);
+ bir_table = table & PCI_MSIX_FLAGS_BIRMASK;
+ g_assert(dev->bars_mapped[bir_table]);
}
- qpci_iounmap(dev, dev->msix_table_bar);
dev->msix_enabled = 0;
dev->msix_table_off = 0;
--
2.45.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 3/8] pci/msix: Implement PBA writes
2024-12-12 8:34 [PATCH 0/8] Add XHCI TR NOOP support, plus PCI, MSIX changes Nicholas Piggin
2024-12-12 8:34 ` [PATCH 1/8] qtest/pci: Enforce balanced iomap/unmap Nicholas Piggin
2024-12-12 8:34 ` [PATCH 2/8] qtest/libqos/pci: Fix qpci_msix_enable sharing bar0 Nicholas Piggin
@ 2024-12-12 8:34 ` Nicholas Piggin
2024-12-13 5:14 ` Akihiko Odaki
2024-12-12 8:34 ` [PATCH 4/8] tests/qtest/e1000e|igb: Fix e1000e and igb tests to re-trigger interrupts Nicholas Piggin
` (4 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Nicholas Piggin @ 2024-12-12 8:34 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, Michael S. Tsirkin, Marcel Apfelbaum,
Fabiano Rosas, Laurent Vivier, Paolo Bonzini, Dmitry Fleytman,
Akihiko Odaki, Sriram Yagnaraman
Implement MMIO PBA writes, 1 to trigger and 0 to clear.
This functionality is used by some qtests, which keep the msix irq
masked and test irq pending via the PBA bits, for simplicity. Some
tests expect to be able to clear the irq with a store, so a side-effect
of this is that qpci_msix_pending() would actually clear the pending
bit where it previously did not. This actually causes some [possibly
buggy] tests to fail. So to avoid breakage until tests are re-examined,
prior behavior of qpci_msix_pending() is kept by changing it to avoid
clearing PBA.
A new function qpci_msix_test_clear_pending() is added for tests that
do want the PBA clearing, and it will be used by XHCI and e1000e/igb
tests in subsequent changes.
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Cc: Dmitry Fleytman <dmitry.fleytman@gmail.com>
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Sriram Yagnaraman <sriram.yagnaraman@ericsson.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
tests/qtest/libqos/pci.h | 1 +
hw/pci/msix.c | 16 ++++++++++++++++
tests/qtest/libqos/pci.c | 20 +++++++++++++++++---
3 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h
index 5a7b2454ad5..de540f7803f 100644
--- a/tests/qtest/libqos/pci.h
+++ b/tests/qtest/libqos/pci.h
@@ -94,6 +94,7 @@ uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id, uint8_t start_addr);
void qpci_msix_enable(QPCIDevice *dev);
void qpci_msix_disable(QPCIDevice *dev);
bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry);
+bool qpci_msix_test_clear_pending(QPCIDevice *dev, uint16_t entry);
bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry);
uint16_t qpci_msix_table_size(QPCIDevice *dev);
diff --git a/hw/pci/msix.c b/hw/pci/msix.c
index 487e49834ee..b16b03b888f 100644
--- a/hw/pci/msix.c
+++ b/hw/pci/msix.c
@@ -260,6 +260,22 @@ static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr,
static void msix_pba_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
+ PCIDevice *dev = opaque;
+ unsigned vector_start = addr * 8;
+ unsigned vector_end = MIN(addr + size * 8, dev->msix_entries_nr);
+ unsigned i;
+
+ for (i = vector_start; i < vector_end; i++) {
+ if ((val >> i) & 1) {
+ if (!msix_is_pending(dev, i)) {
+ msix_notify(dev, i);
+ }
+ } else {
+ if (msix_is_pending(dev, i)) {
+ msix_clr_pending(dev, i);
+ }
+ }
+ }
}
static const MemoryRegionOps msix_pba_mmio_ops = {
diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c
index 023c1617680..f8d655a0e61 100644
--- a/tests/qtest/libqos/pci.c
+++ b/tests/qtest/libqos/pci.c
@@ -361,9 +361,23 @@ bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry)
g_assert(dev->msix_enabled);
pba_entry = qpci_io_readl(dev, dev->msix_pba_bar, dev->msix_pba_off + off);
- qpci_io_writel(dev, dev->msix_pba_bar, dev->msix_pba_off + off,
- pba_entry & ~(1 << bit_n));
- return (pba_entry & (1 << bit_n)) != 0;
+ return pba_entry & (1 << bit_n);
+}
+
+bool qpci_msix_test_clear_pending(QPCIDevice *dev, uint16_t entry)
+{
+ uint32_t pba_entry;
+ uint8_t bit_n = entry % 32;
+ uint64_t off = (entry / 32) * PCI_MSIX_ENTRY_SIZE / 4;
+
+ g_assert(dev->msix_enabled);
+ pba_entry = qpci_io_readl(dev, dev->msix_pba_bar, dev->msix_pba_off + off);
+ if (pba_entry & (1 << bit_n)) {
+ qpci_io_writel(dev, dev->msix_pba_bar, dev->msix_pba_off + off,
+ pba_entry & ~(1 << bit_n));
+ return true;
+ }
+ return false;
}
bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry)
--
2.45.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 3/8] pci/msix: Implement PBA writes
2024-12-12 8:34 ` [PATCH 3/8] pci/msix: Implement PBA writes Nicholas Piggin
@ 2024-12-13 5:14 ` Akihiko Odaki
2024-12-18 1:44 ` Nicholas Piggin
0 siblings, 1 reply; 14+ messages in thread
From: Akihiko Odaki @ 2024-12-13 5:14 UTC (permalink / raw)
To: Nicholas Piggin, qemu-devel
Cc: Michael S. Tsirkin, Marcel Apfelbaum, Fabiano Rosas,
Laurent Vivier, Paolo Bonzini, Dmitry Fleytman, Sriram Yagnaraman
On 2024/12/12 17:34, Nicholas Piggin wrote:
> Implement MMIO PBA writes, 1 to trigger and 0 to clear.
>
> This functionality is used by some qtests, which keep the msix irq
> masked and test irq pending via the PBA bits, for simplicity. Some
> tests expect to be able to clear the irq with a store, so a side-effect
> of this is that qpci_msix_pending() would actually clear the pending
> bit where it previously did not. This actually causes some [possibly
> buggy] tests to fail. So to avoid breakage until tests are re-examined,
> prior behavior of qpci_msix_pending() is kept by changing it to avoid
> clearing PBA.
>
> A new function qpci_msix_test_clear_pending() is added for tests that
> do want the PBA clearing, and it will be used by XHCI and e1000e/igb
> tests in subsequent changes.
The specification says software should never write Pending Bits and its
result is undefined. Tests should have an alternative method to clear
Pending Bits.
A possible solution is to unmask the interrupt, wait until the Pending
Bits get cleared, and mask it again.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/8] pci/msix: Implement PBA writes
2024-12-13 5:14 ` Akihiko Odaki
@ 2024-12-18 1:44 ` Nicholas Piggin
0 siblings, 0 replies; 14+ messages in thread
From: Nicholas Piggin @ 2024-12-18 1:44 UTC (permalink / raw)
To: Akihiko Odaki, qemu-devel
Cc: Michael S. Tsirkin, Marcel Apfelbaum, Fabiano Rosas,
Laurent Vivier, Paolo Bonzini, Dmitry Fleytman, Sriram Yagnaraman
On Fri Dec 13, 2024 at 3:14 PM AEST, Akihiko Odaki wrote:
> On 2024/12/12 17:34, Nicholas Piggin wrote:
> > Implement MMIO PBA writes, 1 to trigger and 0 to clear.
> >
> > This functionality is used by some qtests, which keep the msix irq
> > masked and test irq pending via the PBA bits, for simplicity. Some
> > tests expect to be able to clear the irq with a store, so a side-effect
> > of this is that qpci_msix_pending() would actually clear the pending
> > bit where it previously did not. This actually causes some [possibly
> > buggy] tests to fail. So to avoid breakage until tests are re-examined,
> > prior behavior of qpci_msix_pending() is kept by changing it to avoid
> > clearing PBA.
> >
> > A new function qpci_msix_test_clear_pending() is added for tests that
> > do want the PBA clearing, and it will be used by XHCI and e1000e/igb
> > tests in subsequent changes.
>
> The specification says software should never write Pending Bits and its
> result is undefined. Tests should have an alternative method to clear
> Pending Bits.
Thanks for correcting me. I guess qpci_msix_pending() should not be
trying to write to the PBA either then.
> A possible solution is to unmask the interrupt, wait until the Pending
> Bits get cleared, and mask it again.
PCI spec says
If a masked vector has its Pending bit set, and the associated
underlying interrupt events are somehow satisfied (usually by software
though the exact manner is function-specific), the function must clear
the Pending bit, to avoid sending a spurious interrupt message later
when software unmasks the vector. However, if a subsequent interrupt
event occurs while the vector is still masked, the function must again
set the Pending bit.
It looks like e1000e acutally does that with e1000e_msix_clear{_one}.
So perhaps this will work just with the e1000e ICR clearing patch. I
will test.
e1000e and igb are the only devices that call msix_clr_pending. Does
that mean many others probably do not implement this behaviour
correctly?
Thanks,
Nick
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 4/8] tests/qtest/e1000e|igb: Fix e1000e and igb tests to re-trigger interrupts
2024-12-12 8:34 [PATCH 0/8] Add XHCI TR NOOP support, plus PCI, MSIX changes Nicholas Piggin
` (2 preceding siblings ...)
2024-12-12 8:34 ` [PATCH 3/8] pci/msix: Implement PBA writes Nicholas Piggin
@ 2024-12-12 8:34 ` Nicholas Piggin
2024-12-12 8:34 ` [PATCH 5/8] hw/usb/xhci: Move HCD constants to a header and add register constants Nicholas Piggin
` (3 subsequent siblings)
7 siblings, 0 replies; 14+ messages in thread
From: Nicholas Piggin @ 2024-12-12 8:34 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, Michael S. Tsirkin, Marcel Apfelbaum,
Fabiano Rosas, Laurent Vivier, Paolo Bonzini, Dmitry Fleytman,
Akihiko Odaki, Sriram Yagnaraman
The e1000e and igb tests don't clear the msix pending bit after waiting
for it sit is masked so the irq doesn't get delivered. Failing to clear
the pending interrupt means all subsequent waits for interrupt after the
first do not actually wait for an interrupt genreated by the device.
Explicitly clearing the msix pending bit results in the
multiple-transfers test hanging waiting for the second interrupt. This
happens because the e1000e and igb tests do not clear (or set
auto-clear) on queue interrupts, so the cause remains ste in ICR/EICR,
which inhibits triggering of a new interrupt.
Fix both these problems. Clear the msix pending bit explicitly after
waiting for it; and clear the ICR/EICR cause bits after seeing and
interrupt (also verify we saw the correct cause bit).
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Cc: Dmitry Fleytman <dmitry.fleytman@gmail.com>
Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Sriram Yagnaraman <sriram.yagnaraman@ericsson.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
tests/qtest/e1000e-test.c | 8 ++++++--
tests/qtest/igb-test.c | 8 ++++++--
tests/qtest/libqos/e1000e.c | 2 +-
3 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/tests/qtest/e1000e-test.c b/tests/qtest/e1000e-test.c
index de9738fdb74..a69759da70e 100644
--- a/tests/qtest/e1000e-test.c
+++ b/tests/qtest/e1000e-test.c
@@ -64,8 +64,10 @@ static void e1000e_send_verify(QE1000E *d, int *test_sockets, QGuestAllocator *a
/* Put descriptor to the ring */
e1000e_tx_ring_push(d, &descr);
- /* Wait for TX WB interrupt */
+ /* Wait for TX WB interrupt (this clears the MSIX PBA) */
e1000e_wait_isr(d, E1000E_TX0_MSG_ID);
+ /* Read ICR which clears it ready for next interrupt, assert TXQ0 cause */
+ g_assert(e1000e_macreg_read(d, E1000_ICR) & E1000_ICR_TXQ0);
/* Check DD bit */
g_assert_cmphex(le32_to_cpu(descr.upper.data) & E1000_TXD_STAT_DD, ==,
@@ -115,8 +117,10 @@ static void e1000e_receive_verify(QE1000E *d, int *test_sockets, QGuestAllocator
/* Put descriptor to the ring */
e1000e_rx_ring_push(d, &descr);
- /* Wait for TX WB interrupt */
+ /* Wait for TX WB interrupt (this clears the MSIX PBA) */
e1000e_wait_isr(d, E1000E_RX0_MSG_ID);
+ /* Read ICR which clears it ready for next interrupt, assert RXQ0 cause */
+ g_assert(e1000e_macreg_read(d, E1000_ICR) & E1000_ICR_RXQ0);
/* Check DD bit */
g_assert_cmphex(le32_to_cpu(descr.wb.upper.status_error) &
diff --git a/tests/qtest/igb-test.c b/tests/qtest/igb-test.c
index 3d397ea6973..2f22c4fb208 100644
--- a/tests/qtest/igb-test.c
+++ b/tests/qtest/igb-test.c
@@ -67,8 +67,10 @@ static void igb_send_verify(QE1000E *d, int *test_sockets, QGuestAllocator *allo
/* Put descriptor to the ring */
e1000e_tx_ring_push(d, &descr);
- /* Wait for TX WB interrupt */
+ /* Wait for TX WB interrupt (this clears the MSIX PBA) */
e1000e_wait_isr(d, E1000E_TX0_MSG_ID);
+ /* Read EICR which clears it ready for next interrupt, assert TXQ0 cause */
+ g_assert(e1000e_macreg_read(d, E1000_EICR) & (1 << E1000E_TX0_MSG_ID));
/* Check DD bit */
g_assert_cmphex(le32_to_cpu(descr.wb.status) & E1000_TXD_STAT_DD, ==,
@@ -118,8 +120,10 @@ static void igb_receive_verify(QE1000E *d, int *test_sockets, QGuestAllocator *a
/* Put descriptor to the ring */
e1000e_rx_ring_push(d, &descr);
- /* Wait for TX WB interrupt */
+ /* Wait for TX WB interrupt (this clears the MSIX PBA) */
e1000e_wait_isr(d, E1000E_RX0_MSG_ID);
+ /* Read EICR which clears it ready for next interrupt, assert RXQ0 cause */
+ g_assert(e1000e_macreg_read(d, E1000_EICR) & (1 << E1000E_RX0_MSG_ID));
/* Check DD bit */
g_assert_cmphex(le32_to_cpu(descr.wb.upper.status_error) &
diff --git a/tests/qtest/libqos/e1000e.c b/tests/qtest/libqos/e1000e.c
index 925654c7fd4..8ef6a04f43e 100644
--- a/tests/qtest/libqos/e1000e.c
+++ b/tests/qtest/libqos/e1000e.c
@@ -83,7 +83,7 @@ void e1000e_wait_isr(QE1000E *d, uint16_t msg_id)
guint64 end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND;
do {
- if (qpci_msix_pending(&d_pci->pci_dev, msg_id)) {
+ if (qpci_msix_test_clear_pending(&d_pci->pci_dev, msg_id)) {
return;
}
qtest_clock_step(d_pci->pci_dev.bus->qts, 10000);
--
2.45.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 5/8] hw/usb/xhci: Move HCD constants to a header and add register constants
2024-12-12 8:34 [PATCH 0/8] Add XHCI TR NOOP support, plus PCI, MSIX changes Nicholas Piggin
` (3 preceding siblings ...)
2024-12-12 8:34 ` [PATCH 4/8] tests/qtest/e1000e|igb: Fix e1000e and igb tests to re-trigger interrupts Nicholas Piggin
@ 2024-12-12 8:34 ` Nicholas Piggin
2024-12-18 15:08 ` Phil Dennis-Jordan
2024-12-12 8:34 ` [PATCH 6/8] qtest/xhci: Add controller and device setup and ring tests Nicholas Piggin
` (2 subsequent siblings)
7 siblings, 1 reply; 14+ messages in thread
From: Nicholas Piggin @ 2024-12-12 8:34 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, Michael S. Tsirkin, Marcel Apfelbaum,
Fabiano Rosas, Laurent Vivier, Paolo Bonzini, Dmitry Fleytman,
Akihiko Odaki, Sriram Yagnaraman
Prepare to use some of these constants in xhci qtest code.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/usb/hcd-xhci.h | 190 +++++++++++++++++++++++++++++++
hw/usb/hcd-xhci.c | 283 ++++++++++------------------------------------
2 files changed, 250 insertions(+), 223 deletions(-)
diff --git a/hw/usb/hcd-xhci.h b/hw/usb/hcd-xhci.h
index fe16d7ad055..5781542f40e 100644
--- a/hw/usb/hcd-xhci.h
+++ b/hw/usb/hcd-xhci.h
@@ -115,6 +115,196 @@ typedef enum TRBCCode {
CC_SPLIT_TRANSACTION_ERROR
} TRBCCode;
+/* Register definitions */
+#define XHCI_HCCAP_CAPLENGTH 0x00
+#define XHCI_HCCAP_HCIVERSION 0x02
+#define XHCI_HCCAP_HCSPARAMS1 0x04
+#define XHCI_HCCAP_HCSPARAMS2 0x08
+#define XHCI_HCCAP_HCSPARAMS3 0x0C
+#define XHCI_HCCAP_HCCPARAMS1 0x10
+#define XHCI_HCCAP_DBOFF 0x14
+#define XHCI_HCCAP_RTSOFF 0x18
+#define XHCI_HCCAP_HCCPARAMS2 0x1C
+#define XHCI_HCCAP_EXTCAP_START 0x20 /* SW-defined */
+
+#define XHCI_PORT_PORTSC 0x00
+#define PORTSC_CCS (1 << 0)
+#define PORTSC_PED (1 << 1)
+#define PORTSC_OCA (1 << 3)
+#define PORTSC_PR (1 << 4)
+#define PORTSC_PLS_SHIFT 5
+#define PORTSC_PLS_MASK 0xf
+#define PORTSC_PP (1 << 9)
+#define PORTSC_SPEED_SHIFT 10
+#define PORTSC_SPEED_MASK 0xf
+#define PORTSC_SPEED_FULL (1 << 10)
+#define PORTSC_SPEED_LOW (2 << 10)
+#define PORTSC_SPEED_HIGH (3 << 10)
+#define PORTSC_SPEED_SUPER (4 << 10)
+#define PORTSC_PIC_SHIFT 14
+#define PORTSC_PIC_MASK 0x3
+#define PORTSC_LWS (1 << 16)
+#define PORTSC_CSC (1 << 17)
+#define PORTSC_PEC (1 << 18)
+#define PORTSC_WRC (1 << 19)
+#define PORTSC_OCC (1 << 20)
+#define PORTSC_PRC (1 << 21)
+#define PORTSC_PLC (1 << 22)
+#define PORTSC_CEC (1 << 23)
+#define PORTSC_CAS (1 << 24)
+#define PORTSC_WCE (1 << 25)
+#define PORTSC_WDE (1 << 26)
+#define PORTSC_WOE (1 << 27)
+#define PORTSC_DR (1 << 30)
+#define PORTSC_WPR (1 << 31)
+#define XHCI_PORT_PORTPMSC 0x04
+#define XHCI_PORT_PORTLI 0x08
+#define XHCI_PORT_PORTHLPMC 0x0C
+
+#define XHCI_OPER_USBCMD 0x00
+#define USBCMD_RS (1 << 0)
+#define USBCMD_HCRST (1 << 1)
+#define USBCMD_INTE (1 << 2)
+#define USBCMD_HSEE (1 << 3)
+#define USBCMD_LHCRST (1 << 7)
+#define USBCMD_CSS (1 << 8)
+#define USBCMD_CRS (1 << 9)
+#define USBCMD_EWE (1 << 10)
+#define USBCMD_EU3S (1 << 11)
+#define XHCI_OPER_USBSTS 0x04
+#define USBSTS_HCH (1 << 0)
+#define USBSTS_HSE (1 << 2)
+#define USBSTS_EINT (1 << 3)
+#define USBSTS_PCD (1 << 4)
+#define USBSTS_SSS (1 << 8)
+#define USBSTS_RSS (1 << 9)
+#define USBSTS_SRE (1 << 10)
+#define USBSTS_CNR (1 << 11)
+#define USBSTS_HCE (1 << 12)
+#define XHCI_OPER_PAGESIZE 0x08
+#define XHCI_OPER_DNCTRL 0x14
+#define XHCI_OPER_CRCR_LO 0x18
+#define CRCR_RCS (1 << 0)
+#define CRCR_CS (1 << 1)
+#define CRCR_CA (1 << 2)
+#define CRCR_CRR (1 << 3)
+#define XHCI_OPER_CRCR_HI 0x1C
+#define XHCI_OPER_DCBAAP_LO 0x30
+#define XHCI_OPER_DCBAAP_HI 0x34
+#define XHCI_OPER_CONFIG 0x38
+
+#define XHCI_OPER_MFINDEX 0x00
+#define XHCI_OPER_IR0 0x20
+#define XHCI_OPER_IR_SZ 0x20
+
+#define XHCI_INTR_IMAN 0x00
+#define IMAN_IP (1 << 0)
+#define IMAN_IE (1 << 1)
+#define XHCI_INTR_IMOD 0x04
+#define XHCI_INTR_ERSTSZ 0x08
+#define XHCI_INTR_ERSTBA_LO 0x10
+#define XHCI_INTR_ERSTBA_HI 0x14
+#define XHCI_INTR_ERDP_LO 0x18
+#define ERDP_EHB (1 << 3)
+#define XHCI_INTR_ERDP_HI 0x1C
+
+#define TRB_SIZE 16
+typedef struct XHCITRB {
+ uint64_t parameter;
+ uint32_t status;
+ uint32_t control;
+ dma_addr_t addr;
+ bool ccs;
+} XHCITRB;
+
+enum {
+ PLS_U0 = 0,
+ PLS_U1 = 1,
+ PLS_U2 = 2,
+ PLS_U3 = 3,
+ PLS_DISABLED = 4,
+ PLS_RX_DETECT = 5,
+ PLS_INACTIVE = 6,
+ PLS_POLLING = 7,
+ PLS_RECOVERY = 8,
+ PLS_HOT_RESET = 9,
+ PLS_COMPILANCE_MODE = 10,
+ PLS_TEST_MODE = 11,
+ PLS_RESUME = 15,
+};
+
+#define CR_LINK TR_LINK
+
+#define TRB_C (1 << 0)
+#define TRB_TYPE_SHIFT 10
+#define TRB_TYPE_MASK 0x3f
+#define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
+
+#define TRB_EV_ED (1 << 2)
+
+#define TRB_TR_ENT (1 << 1)
+#define TRB_TR_ISP (1 << 2)
+#define TRB_TR_NS (1 << 3)
+#define TRB_TR_CH (1 << 4)
+#define TRB_TR_IOC (1 << 5)
+#define TRB_TR_IDT (1 << 6)
+#define TRB_TR_TBC_SHIFT 7
+#define TRB_TR_TBC_MASK 0x3
+#define TRB_TR_BEI (1 << 9)
+#define TRB_TR_TLBPC_SHIFT 16
+#define TRB_TR_TLBPC_MASK 0xf
+#define TRB_TR_FRAMEID_SHIFT 20
+#define TRB_TR_FRAMEID_MASK 0x7ff
+#define TRB_TR_SIA (1 << 31)
+
+#define TRB_TR_DIR (1 << 16)
+
+#define TRB_CR_SLOTID_SHIFT 24
+#define TRB_CR_SLOTID_MASK 0xff
+#define TRB_CR_EPID_SHIFT 16
+#define TRB_CR_EPID_MASK 0x1f
+
+#define TRB_CR_BSR (1 << 9)
+#define TRB_CR_DC (1 << 9)
+
+#define TRB_LK_TC (1 << 1)
+
+#define TRB_INTR_SHIFT 22
+#define TRB_INTR_MASK 0x3ff
+#define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
+
+#define EP_TYPE_MASK 0x7
+#define EP_TYPE_SHIFT 3
+
+#define EP_STATE_MASK 0x7
+#define EP_DISABLED (0 << 0)
+#define EP_RUNNING (1 << 0)
+#define EP_HALTED (2 << 0)
+#define EP_STOPPED (3 << 0)
+#define EP_ERROR (4 << 0)
+
+#define SLOT_STATE_MASK 0x1f
+#define SLOT_STATE_SHIFT 27
+#define SLOT_STATE(s) (((s) >> SLOT_STATE_SHIFT) & SLOT_STATE_MASK)
+#define SLOT_ENABLED 0
+#define SLOT_DEFAULT 1
+#define SLOT_ADDRESSED 2
+#define SLOT_CONFIGURED 3
+
+#define SLOT_CONTEXT_ENTRIES_MASK 0x1f
+#define SLOT_CONTEXT_ENTRIES_SHIFT 27
+
+typedef enum EPType {
+ ET_INVALID = 0,
+ ET_ISO_OUT,
+ ET_BULK_OUT,
+ ET_INTR_OUT,
+ ET_CONTROL,
+ ET_ISO_IN,
+ ET_BULK_IN,
+ ET_INTR_IN,
+} EPType;
+
typedef struct XHCIRing {
dma_addr_t dequeue;
bool ccs;
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index d85adaca0dc..df0421ec326 100644
--- a/hw/usb/hcd-xhci.c
+++ b/hw/usb/hcd-xhci.c
@@ -65,154 +65,6 @@
# error Increase XHCI_LEN_REGS
#endif
-/* bit definitions */
-#define USBCMD_RS (1<<0)
-#define USBCMD_HCRST (1<<1)
-#define USBCMD_INTE (1<<2)
-#define USBCMD_HSEE (1<<3)
-#define USBCMD_LHCRST (1<<7)
-#define USBCMD_CSS (1<<8)
-#define USBCMD_CRS (1<<9)
-#define USBCMD_EWE (1<<10)
-#define USBCMD_EU3S (1<<11)
-
-#define USBSTS_HCH (1<<0)
-#define USBSTS_HSE (1<<2)
-#define USBSTS_EINT (1<<3)
-#define USBSTS_PCD (1<<4)
-#define USBSTS_SSS (1<<8)
-#define USBSTS_RSS (1<<9)
-#define USBSTS_SRE (1<<10)
-#define USBSTS_CNR (1<<11)
-#define USBSTS_HCE (1<<12)
-
-
-#define PORTSC_CCS (1<<0)
-#define PORTSC_PED (1<<1)
-#define PORTSC_OCA (1<<3)
-#define PORTSC_PR (1<<4)
-#define PORTSC_PLS_SHIFT 5
-#define PORTSC_PLS_MASK 0xf
-#define PORTSC_PP (1<<9)
-#define PORTSC_SPEED_SHIFT 10
-#define PORTSC_SPEED_MASK 0xf
-#define PORTSC_SPEED_FULL (1<<10)
-#define PORTSC_SPEED_LOW (2<<10)
-#define PORTSC_SPEED_HIGH (3<<10)
-#define PORTSC_SPEED_SUPER (4<<10)
-#define PORTSC_PIC_SHIFT 14
-#define PORTSC_PIC_MASK 0x3
-#define PORTSC_LWS (1<<16)
-#define PORTSC_CSC (1<<17)
-#define PORTSC_PEC (1<<18)
-#define PORTSC_WRC (1<<19)
-#define PORTSC_OCC (1<<20)
-#define PORTSC_PRC (1<<21)
-#define PORTSC_PLC (1<<22)
-#define PORTSC_CEC (1<<23)
-#define PORTSC_CAS (1<<24)
-#define PORTSC_WCE (1<<25)
-#define PORTSC_WDE (1<<26)
-#define PORTSC_WOE (1<<27)
-#define PORTSC_DR (1<<30)
-#define PORTSC_WPR (1<<31)
-
-#define CRCR_RCS (1<<0)
-#define CRCR_CS (1<<1)
-#define CRCR_CA (1<<2)
-#define CRCR_CRR (1<<3)
-
-#define IMAN_IP (1<<0)
-#define IMAN_IE (1<<1)
-
-#define ERDP_EHB (1<<3)
-
-#define TRB_SIZE 16
-typedef struct XHCITRB {
- uint64_t parameter;
- uint32_t status;
- uint32_t control;
- dma_addr_t addr;
- bool ccs;
-} XHCITRB;
-
-enum {
- PLS_U0 = 0,
- PLS_U1 = 1,
- PLS_U2 = 2,
- PLS_U3 = 3,
- PLS_DISABLED = 4,
- PLS_RX_DETECT = 5,
- PLS_INACTIVE = 6,
- PLS_POLLING = 7,
- PLS_RECOVERY = 8,
- PLS_HOT_RESET = 9,
- PLS_COMPILANCE_MODE = 10,
- PLS_TEST_MODE = 11,
- PLS_RESUME = 15,
-};
-
-#define CR_LINK TR_LINK
-
-#define TRB_C (1<<0)
-#define TRB_TYPE_SHIFT 10
-#define TRB_TYPE_MASK 0x3f
-#define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
-
-#define TRB_EV_ED (1<<2)
-
-#define TRB_TR_ENT (1<<1)
-#define TRB_TR_ISP (1<<2)
-#define TRB_TR_NS (1<<3)
-#define TRB_TR_CH (1<<4)
-#define TRB_TR_IOC (1<<5)
-#define TRB_TR_IDT (1<<6)
-#define TRB_TR_TBC_SHIFT 7
-#define TRB_TR_TBC_MASK 0x3
-#define TRB_TR_BEI (1<<9)
-#define TRB_TR_TLBPC_SHIFT 16
-#define TRB_TR_TLBPC_MASK 0xf
-#define TRB_TR_FRAMEID_SHIFT 20
-#define TRB_TR_FRAMEID_MASK 0x7ff
-#define TRB_TR_SIA (1<<31)
-
-#define TRB_TR_DIR (1<<16)
-
-#define TRB_CR_SLOTID_SHIFT 24
-#define TRB_CR_SLOTID_MASK 0xff
-#define TRB_CR_EPID_SHIFT 16
-#define TRB_CR_EPID_MASK 0x1f
-
-#define TRB_CR_BSR (1<<9)
-#define TRB_CR_DC (1<<9)
-
-#define TRB_LK_TC (1<<1)
-
-#define TRB_INTR_SHIFT 22
-#define TRB_INTR_MASK 0x3ff
-#define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
-
-#define EP_TYPE_MASK 0x7
-#define EP_TYPE_SHIFT 3
-
-#define EP_STATE_MASK 0x7
-#define EP_DISABLED (0<<0)
-#define EP_RUNNING (1<<0)
-#define EP_HALTED (2<<0)
-#define EP_STOPPED (3<<0)
-#define EP_ERROR (4<<0)
-
-#define SLOT_STATE_MASK 0x1f
-#define SLOT_STATE_SHIFT 27
-#define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
-#define SLOT_ENABLED 0
-#define SLOT_DEFAULT 1
-#define SLOT_ADDRESSED 2
-#define SLOT_CONFIGURED 3
-
-#define SLOT_CONTEXT_ENTRIES_MASK 0x1f
-#define SLOT_CONTEXT_ENTRIES_SHIFT 27
-
#define get_field(data, field) \
(((data) >> field##_SHIFT) & field##_MASK)
@@ -223,17 +75,6 @@ enum {
*data = val_; \
} while (0)
-typedef enum EPType {
- ET_INVALID = 0,
- ET_ISO_OUT,
- ET_BULK_OUT,
- ET_INTR_OUT,
- ET_CONTROL,
- ET_ISO_IN,
- ET_BULK_IN,
- ET_INTR_IN,
-} EPType;
-
typedef struct XHCITransfer {
XHCIEPContext *epctx;
USBPacket packet;
@@ -2736,56 +2577,55 @@ static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
uint32_t ret;
switch (reg) {
- case 0x00: /* HCIVERSION, CAPLENGTH */
+ case XHCI_HCCAP_CAPLENGTH: /* Covers HCIVERSION and CAPLENGTH */
ret = 0x01000000 | LEN_CAP;
break;
- case 0x04: /* HCSPARAMS 1 */
+ case XHCI_HCCAP_HCSPARAMS1:
ret = ((xhci->numports_2+xhci->numports_3)<<24)
| (xhci->numintrs<<8) | xhci->numslots;
break;
- case 0x08: /* HCSPARAMS 2 */
+ case XHCI_HCCAP_HCSPARAMS2:
ret = 0x0000000f;
break;
- case 0x0c: /* HCSPARAMS 3 */
+ case XHCI_HCCAP_HCSPARAMS3:
ret = 0x00000000;
break;
- case 0x10: /* HCCPARAMS */
- if (sizeof(dma_addr_t) == 4) {
- ret = 0x00080000 | (xhci->max_pstreams_mask << 12);
- } else {
- ret = 0x00080001 | (xhci->max_pstreams_mask << 12);
+ case XHCI_HCCAP_HCCPARAMS1:
+ ret = (XHCI_HCCAP_EXTCAP_START >> 2) | (xhci->max_pstreams_mask << 12);
+ if (sizeof(dma_addr_t) == 8) {
+ ret |= 0x00000001; /* AC64 */
}
break;
- case 0x14: /* DBOFF */
+ case XHCI_HCCAP_DBOFF:
ret = OFF_DOORBELL;
break;
- case 0x18: /* RTSOFF */
+ case XHCI_HCCAP_RTSOFF:
ret = OFF_RUNTIME;
break;
/* extended capabilities */
- case 0x20: /* Supported Protocol:00 */
+ case XHCI_HCCAP_EXTCAP_START + 0x00: /* Supported Protocol:00 */
ret = 0x02000402; /* USB 2.0 */
break;
- case 0x24: /* Supported Protocol:04 */
+ case XHCI_HCCAP_EXTCAP_START + 0x04: /* Supported Protocol:04 */
ret = 0x20425355; /* "USB " */
break;
- case 0x28: /* Supported Protocol:08 */
+ case XHCI_HCCAP_EXTCAP_START + 0x08: /* Supported Protocol:08 */
ret = (xhci->numports_2 << 8) | (xhci->numports_3 + 1);
break;
- case 0x2c: /* Supported Protocol:0c */
+ case XHCI_HCCAP_EXTCAP_START + 0x0c: /* Supported Protocol:0c */
ret = 0x00000000; /* reserved */
break;
- case 0x30: /* Supported Protocol:00 */
+ case XHCI_HCCAP_EXTCAP_START + 0x10: /* Supported Protocol:00 */
ret = 0x03000002; /* USB 3.0 */
break;
- case 0x34: /* Supported Protocol:04 */
+ case XHCI_HCCAP_EXTCAP_START + 0x14: /* Supported Protocol:04 */
ret = 0x20425355; /* "USB " */
break;
- case 0x38: /* Supported Protocol:08 */
+ case XHCI_HCCAP_EXTCAP_START + 0x18: /* Supported Protocol:08 */
ret = (xhci->numports_3 << 8) | 1;
break;
- case 0x3c: /* Supported Protocol:0c */
+ case XHCI_HCCAP_EXTCAP_START + 0x1c: /* Supported Protocol:0c */
ret = 0x00000000; /* reserved */
break;
default:
@@ -2803,14 +2643,13 @@ static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
uint32_t ret;
switch (reg) {
- case 0x00: /* PORTSC */
+ case XHCI_PORT_PORTSC:
ret = port->portsc;
break;
- case 0x04: /* PORTPMSC */
- case 0x08: /* PORTLI */
+ case XHCI_PORT_PORTPMSC:
+ case XHCI_PORT_PORTLI:
ret = 0;
break;
- case 0x0c: /* reserved */
default:
trace_usb_xhci_unimplemented("port read", reg);
ret = 0;
@@ -2829,7 +2668,7 @@ static void xhci_port_write(void *ptr, hwaddr reg,
trace_usb_xhci_port_write(port->portnr, reg, val);
switch (reg) {
- case 0x00: /* PORTSC */
+ case XHCI_PORT_PORTSC:
/* write-1-to-start bits */
if (val & PORTSC_WPR) {
xhci_port_reset(port, true);
@@ -2880,8 +2719,6 @@ static void xhci_port_write(void *ptr, hwaddr reg,
xhci_port_notify(port, notify);
}
break;
- case 0x04: /* PORTPMSC */
- case 0x08: /* PORTLI */
default:
trace_usb_xhci_unimplemented("port write", reg);
}
@@ -2893,31 +2730,31 @@ static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
uint32_t ret;
switch (reg) {
- case 0x00: /* USBCMD */
+ case XHCI_OPER_USBCMD:
ret = xhci->usbcmd;
break;
- case 0x04: /* USBSTS */
+ case XHCI_OPER_USBSTS:
ret = xhci->usbsts;
break;
- case 0x08: /* PAGESIZE */
+ case XHCI_OPER_PAGESIZE:
ret = 1; /* 4KiB */
break;
- case 0x14: /* DNCTRL */
+ case XHCI_OPER_DNCTRL:
ret = xhci->dnctrl;
break;
- case 0x18: /* CRCR low */
+ case XHCI_OPER_CRCR_LO:
ret = xhci->crcr_low & ~0xe;
break;
- case 0x1c: /* CRCR high */
+ case XHCI_OPER_CRCR_HI:
ret = xhci->crcr_high;
break;
- case 0x30: /* DCBAAP low */
+ case XHCI_OPER_DCBAAP_LO:
ret = xhci->dcbaap_low;
break;
- case 0x34: /* DCBAAP high */
+ case XHCI_OPER_DCBAAP_HI:
ret = xhci->dcbaap_high;
break;
- case 0x38: /* CONFIG */
+ case XHCI_OPER_CONFIG:
ret = xhci->config;
break;
default:
@@ -2937,7 +2774,7 @@ static void xhci_oper_write(void *ptr, hwaddr reg,
trace_usb_xhci_oper_write(reg, val);
switch (reg) {
- case 0x00: /* USBCMD */
+ case XHCI_OPER_USBCMD:
if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
xhci_run(xhci);
} else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
@@ -2959,19 +2796,19 @@ static void xhci_oper_write(void *ptr, hwaddr reg,
xhci_intr_update(xhci, 0);
break;
- case 0x04: /* USBSTS */
+ case XHCI_OPER_USBSTS:
/* these bits are write-1-to-clear */
xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
xhci_intr_update(xhci, 0);
break;
- case 0x14: /* DNCTRL */
+ case XHCI_OPER_DNCTRL:
xhci->dnctrl = val & 0xffff;
break;
- case 0x18: /* CRCR low */
+ case XHCI_OPER_CRCR_LO:
xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
break;
- case 0x1c: /* CRCR high */
+ case XHCI_OPER_CRCR_HI:
xhci->crcr_high = val;
if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
@@ -2984,13 +2821,13 @@ static void xhci_oper_write(void *ptr, hwaddr reg,
}
xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
break;
- case 0x30: /* DCBAAP low */
+ case XHCI_OPER_DCBAAP_LO:
xhci->dcbaap_low = val & 0xffffffc0;
break;
- case 0x34: /* DCBAAP high */
+ case XHCI_OPER_DCBAAP_HI:
xhci->dcbaap_high = val;
break;
- case 0x38: /* CONFIG */
+ case XHCI_OPER_CONFIG:
xhci->config = val & 0xff;
break;
default:
@@ -3004,9 +2841,9 @@ static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
XHCIState *xhci = ptr;
uint32_t ret = 0;
- if (reg < 0x20) {
+ if (reg < XHCI_OPER_IR0) {
switch (reg) {
- case 0x00: /* MFINDEX */
+ case XHCI_OPER_MFINDEX:
ret = xhci_mfindex_get(xhci) & 0x3fff;
break;
default:
@@ -3014,28 +2851,28 @@ static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
break;
}
} else {
- int v = (reg - 0x20) / 0x20;
+ int v = (reg - XHCI_OPER_IR0) / XHCI_OPER_IR_SZ;
XHCIInterrupter *intr = &xhci->intr[v];
- switch (reg & 0x1f) {
- case 0x00: /* IMAN */
+ switch (reg & (XHCI_OPER_IR_SZ - 1)) {
+ case XHCI_INTR_IMAN:
ret = intr->iman;
break;
- case 0x04: /* IMOD */
+ case XHCI_INTR_IMOD:
ret = intr->imod;
break;
- case 0x08: /* ERSTSZ */
+ case XHCI_INTR_ERSTSZ:
ret = intr->erstsz;
break;
- case 0x10: /* ERSTBA low */
+ case XHCI_INTR_ERSTBA_LO:
ret = intr->erstba_low;
break;
- case 0x14: /* ERSTBA high */
+ case XHCI_INTR_ERSTBA_HI:
ret = intr->erstba_high;
break;
- case 0x18: /* ERDP low */
+ case XHCI_INTR_ERDP_LO:
ret = intr->erdp_low;
break;
- case 0x1c: /* ERDP high */
+ case XHCI_INTR_ERDP_HI:
ret = intr->erdp_high;
break;
}
@@ -3054,15 +2891,15 @@ static void xhci_runtime_write(void *ptr, hwaddr reg,
trace_usb_xhci_runtime_write(reg, val);
- if (reg < 0x20) {
+ if (reg < XHCI_OPER_IR0) {
trace_usb_xhci_unimplemented("runtime write", reg);
return;
}
- v = (reg - 0x20) / 0x20;
+ v = (reg - XHCI_OPER_IR0) / XHCI_OPER_IR_SZ;
intr = &xhci->intr[v];
- switch (reg & 0x1f) {
- case 0x00: /* IMAN */
+ switch (reg & (XHCI_OPER_IR_SZ - 1)) {
+ case XHCI_INTR_IMAN:
if (val & IMAN_IP) {
intr->iman &= ~IMAN_IP;
}
@@ -3070,13 +2907,13 @@ static void xhci_runtime_write(void *ptr, hwaddr reg,
intr->iman |= val & IMAN_IE;
xhci_intr_update(xhci, v);
break;
- case 0x04: /* IMOD */
+ case XHCI_INTR_IMOD:
intr->imod = val;
break;
- case 0x08: /* ERSTSZ */
+ case XHCI_INTR_ERSTSZ:
intr->erstsz = val & 0xffff;
break;
- case 0x10: /* ERSTBA low */
+ case XHCI_INTR_ERSTBA_LO:
if (xhci->nec_quirks) {
/* NEC driver bug: it doesn't align this to 64 bytes */
intr->erstba_low = val & 0xfffffff0;
@@ -3084,11 +2921,11 @@ static void xhci_runtime_write(void *ptr, hwaddr reg,
intr->erstba_low = val & 0xffffffc0;
}
break;
- case 0x14: /* ERSTBA high */
+ case XHCI_INTR_ERSTBA_HI:
intr->erstba_high = val;
xhci_er_reset(xhci, v);
break;
- case 0x18: /* ERDP low */
+ case XHCI_INTR_ERDP_LO:
if (val & ERDP_EHB) {
intr->erdp_low &= ~ERDP_EHB;
}
@@ -3103,7 +2940,7 @@ static void xhci_runtime_write(void *ptr, hwaddr reg,
}
}
break;
- case 0x1c: /* ERDP high */
+ case XHCI_INTR_ERDP_HI:
intr->erdp_high = val;
break;
default:
--
2.45.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 5/8] hw/usb/xhci: Move HCD constants to a header and add register constants
2024-12-12 8:34 ` [PATCH 5/8] hw/usb/xhci: Move HCD constants to a header and add register constants Nicholas Piggin
@ 2024-12-18 15:08 ` Phil Dennis-Jordan
2024-12-19 1:50 ` Nicholas Piggin
0 siblings, 1 reply; 14+ messages in thread
From: Phil Dennis-Jordan @ 2024-12-18 15:08 UTC (permalink / raw)
To: Nicholas Piggin
Cc: qemu-devel, Michael S. Tsirkin, Marcel Apfelbaum, Fabiano Rosas,
Laurent Vivier, Paolo Bonzini, Dmitry Fleytman, Akihiko Odaki,
Sriram Yagnaraman
[-- Attachment #1: Type: text/plain, Size: 26151 bytes --]
This looks sensible to me overall.
For the new symbolic constants for MMIO register offsets such as
XHCI_OPER_*, XHCI_INTR_* and so on, I'm wondering if it would be clearer to
give them all an _OFFSET suffix. It's not perfectly consistent to do so
across the code base, but quite a few device types do follow that
convention. In my opinion it improves readability, especially in the header
file, where these offset constants are frequently mixed in with constant
values that can be written to or read from these registers.
I think I also found a regression, and there's a couple other comments on
stylistic matters inline:
On Thu, 12 Dec 2024 at 09:37, Nicholas Piggin <npiggin@gmail.com> wrote:
> Prepare to use some of these constants in xhci qtest code.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> hw/usb/hcd-xhci.h | 190 +++++++++++++++++++++++++++++++
> hw/usb/hcd-xhci.c | 283 ++++++++++------------------------------------
> 2 files changed, 250 insertions(+), 223 deletions(-)
>
> diff --git a/hw/usb/hcd-xhci.h b/hw/usb/hcd-xhci.h
> index fe16d7ad055..5781542f40e 100644
> --- a/hw/usb/hcd-xhci.h
> +++ b/hw/usb/hcd-xhci.h
> @@ -115,6 +115,196 @@ typedef enum TRBCCode {
> CC_SPLIT_TRANSACTION_ERROR
> } TRBCCode;
>
> +/* Register definitions */
> +#define XHCI_HCCAP_CAPLENGTH 0x00
> +#define XHCI_HCCAP_HCIVERSION 0x02
> +#define XHCI_HCCAP_HCSPARAMS1 0x04
> +#define XHCI_HCCAP_HCSPARAMS2 0x08
> +#define XHCI_HCCAP_HCSPARAMS3 0x0C
> +#define XHCI_HCCAP_HCCPARAMS1 0x10
> +#define XHCI_HCCAP_DBOFF 0x14
> +#define XHCI_HCCAP_RTSOFF 0x18
> +#define XHCI_HCCAP_HCCPARAMS2 0x1C
> +#define XHCI_HCCAP_EXTCAP_START 0x20 /* SW-defined */
> +
> +#define XHCI_PORT_PORTSC 0x00
> +#define PORTSC_CCS (1 << 0)
> +#define PORTSC_PED (1 << 1)
> +#define PORTSC_OCA (1 << 3)
> +#define PORTSC_PR (1 << 4)
> +#define PORTSC_PLS_SHIFT 5
> +#define PORTSC_PLS_MASK 0xf
> +#define PORTSC_PP (1 << 9)
> +#define PORTSC_SPEED_SHIFT 10
> +#define PORTSC_SPEED_MASK 0xf
> +#define PORTSC_SPEED_FULL (1 << 10)
> +#define PORTSC_SPEED_LOW (2 << 10)
> +#define PORTSC_SPEED_HIGH (3 << 10)
> +#define PORTSC_SPEED_SUPER (4 << 10)
> +#define PORTSC_PIC_SHIFT 14
> +#define PORTSC_PIC_MASK 0x3
> +#define PORTSC_LWS (1 << 16)
> +#define PORTSC_CSC (1 << 17)
> +#define PORTSC_PEC (1 << 18)
> +#define PORTSC_WRC (1 << 19)
> +#define PORTSC_OCC (1 << 20)
> +#define PORTSC_PRC (1 << 21)
> +#define PORTSC_PLC (1 << 22)
> +#define PORTSC_CEC (1 << 23)
> +#define PORTSC_CAS (1 << 24)
> +#define PORTSC_WCE (1 << 25)
> +#define PORTSC_WDE (1 << 26)
> +#define PORTSC_WOE (1 << 27)
> +#define PORTSC_DR (1 << 30)
> +#define PORTSC_WPR (1 << 31)
> +#define XHCI_PORT_PORTPMSC 0x04
> +#define XHCI_PORT_PORTLI 0x08
> +#define XHCI_PORT_PORTHLPMC 0x0C
> +
> +#define XHCI_OPER_USBCMD 0x00
> +#define USBCMD_RS (1 << 0)
> +#define USBCMD_HCRST (1 << 1)
> +#define USBCMD_INTE (1 << 2)
> +#define USBCMD_HSEE (1 << 3)
> +#define USBCMD_LHCRST (1 << 7)
> +#define USBCMD_CSS (1 << 8)
> +#define USBCMD_CRS (1 << 9)
> +#define USBCMD_EWE (1 << 10)
> +#define USBCMD_EU3S (1 << 11)
> +#define XHCI_OPER_USBSTS 0x04
> +#define USBSTS_HCH (1 << 0)
> +#define USBSTS_HSE (1 << 2)
> +#define USBSTS_EINT (1 << 3)
> +#define USBSTS_PCD (1 << 4)
> +#define USBSTS_SSS (1 << 8)
> +#define USBSTS_RSS (1 << 9)
> +#define USBSTS_SRE (1 << 10)
> +#define USBSTS_CNR (1 << 11)
> +#define USBSTS_HCE (1 << 12)
> +#define XHCI_OPER_PAGESIZE 0x08
> +#define XHCI_OPER_DNCTRL 0x14
> +#define XHCI_OPER_CRCR_LO 0x18
> +#define CRCR_RCS (1 << 0)
> +#define CRCR_CS (1 << 1)
> +#define CRCR_CA (1 << 2)
> +#define CRCR_CRR (1 << 3)
> +#define XHCI_OPER_CRCR_HI 0x1C
> +#define XHCI_OPER_DCBAAP_LO 0x30
> +#define XHCI_OPER_DCBAAP_HI 0x34
> +#define XHCI_OPER_CONFIG 0x38
> +
> +#define XHCI_OPER_MFINDEX 0x00
> +#define XHCI_OPER_IR0 0x20
> +#define XHCI_OPER_IR_SZ 0x20
> +
> +#define XHCI_INTR_IMAN 0x00
> +#define IMAN_IP (1 << 0)
> +#define IMAN_IE (1 << 1)
> +#define XHCI_INTR_IMOD 0x04
> +#define XHCI_INTR_ERSTSZ 0x08
> +#define XHCI_INTR_ERSTBA_LO 0x10
> +#define XHCI_INTR_ERSTBA_HI 0x14
> +#define XHCI_INTR_ERDP_LO 0x18
> +#define ERDP_EHB (1 << 3)
> +#define XHCI_INTR_ERDP_HI 0x1C
> +
> +#define TRB_SIZE 16
> +typedef struct XHCITRB {
> + uint64_t parameter;
> + uint32_t status;
> + uint32_t control;
> + dma_addr_t addr;
> + bool ccs;
> +} XHCITRB;
> +
> +enum {
> + PLS_U0 = 0,
> + PLS_U1 = 1,
> + PLS_U2 = 2,
> + PLS_U3 = 3,
> + PLS_DISABLED = 4,
> + PLS_RX_DETECT = 5,
> + PLS_INACTIVE = 6,
> + PLS_POLLING = 7,
> + PLS_RECOVERY = 8,
> + PLS_HOT_RESET = 9,
> + PLS_COMPILANCE_MODE = 10,
> + PLS_TEST_MODE = 11,
> + PLS_RESUME = 15,
> +};
> +
> +#define CR_LINK TR_LINK
> +
> +#define TRB_C (1 << 0)
> +#define TRB_TYPE_SHIFT 10
> +#define TRB_TYPE_MASK 0x3f
> +#define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) &
> TRB_TYPE_MASK)
> +
> +#define TRB_EV_ED (1 << 2)
> +
> +#define TRB_TR_ENT (1 << 1)
> +#define TRB_TR_ISP (1 << 2)
> +#define TRB_TR_NS (1 << 3)
> +#define TRB_TR_CH (1 << 4)
> +#define TRB_TR_IOC (1 << 5)
> +#define TRB_TR_IDT (1 << 6)
> +#define TRB_TR_TBC_SHIFT 7
> +#define TRB_TR_TBC_MASK 0x3
> +#define TRB_TR_BEI (1 << 9)
> +#define TRB_TR_TLBPC_SHIFT 16
> +#define TRB_TR_TLBPC_MASK 0xf
> +#define TRB_TR_FRAMEID_SHIFT 20
> +#define TRB_TR_FRAMEID_MASK 0x7ff
> +#define TRB_TR_SIA (1 << 31)
> +
> +#define TRB_TR_DIR (1 << 16)
> +
> +#define TRB_CR_SLOTID_SHIFT 24
> +#define TRB_CR_SLOTID_MASK 0xff
> +#define TRB_CR_EPID_SHIFT 16
> +#define TRB_CR_EPID_MASK 0x1f
> +
> +#define TRB_CR_BSR (1 << 9)
> +#define TRB_CR_DC (1 << 9)
> +
> +#define TRB_LK_TC (1 << 1)
> +
> +#define TRB_INTR_SHIFT 22
> +#define TRB_INTR_MASK 0x3ff
> +#define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) &
> TRB_INTR_MASK)
> +
> +#define EP_TYPE_MASK 0x7
> +#define EP_TYPE_SHIFT 3
> +
> +#define EP_STATE_MASK 0x7
> +#define EP_DISABLED (0 << 0)
> +#define EP_RUNNING (1 << 0)
> +#define EP_HALTED (2 << 0)
> +#define EP_STOPPED (3 << 0)
> +#define EP_ERROR (4 << 0)
> +
> +#define SLOT_STATE_MASK 0x1f
> +#define SLOT_STATE_SHIFT 27
> +#define SLOT_STATE(s) (((s) >> SLOT_STATE_SHIFT) & SLOT_STATE_MASK)
> +#define SLOT_ENABLED 0
> +#define SLOT_DEFAULT 1
> +#define SLOT_ADDRESSED 2
> +#define SLOT_CONFIGURED 3
> +
> +#define SLOT_CONTEXT_ENTRIES_MASK 0x1f
> +#define SLOT_CONTEXT_ENTRIES_SHIFT 27
> +
> +typedef enum EPType {
> + ET_INVALID = 0,
> + ET_ISO_OUT,
> + ET_BULK_OUT,
> + ET_INTR_OUT,
> + ET_CONTROL,
> + ET_ISO_IN,
> + ET_BULK_IN,
> + ET_INTR_IN,
> +} EPType;
> +
> typedef struct XHCIRing {
> dma_addr_t dequeue;
> bool ccs;
> diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
> index d85adaca0dc..df0421ec326 100644
> --- a/hw/usb/hcd-xhci.c
> +++ b/hw/usb/hcd-xhci.c
> @@ -65,154 +65,6 @@
> # error Increase XHCI_LEN_REGS
> #endif
>
> -/* bit definitions */
> -#define USBCMD_RS (1<<0)
> -#define USBCMD_HCRST (1<<1)
> -#define USBCMD_INTE (1<<2)
> -#define USBCMD_HSEE (1<<3)
> -#define USBCMD_LHCRST (1<<7)
> -#define USBCMD_CSS (1<<8)
> -#define USBCMD_CRS (1<<9)
> -#define USBCMD_EWE (1<<10)
> -#define USBCMD_EU3S (1<<11)
> -
> -#define USBSTS_HCH (1<<0)
> -#define USBSTS_HSE (1<<2)
> -#define USBSTS_EINT (1<<3)
> -#define USBSTS_PCD (1<<4)
> -#define USBSTS_SSS (1<<8)
> -#define USBSTS_RSS (1<<9)
> -#define USBSTS_SRE (1<<10)
> -#define USBSTS_CNR (1<<11)
> -#define USBSTS_HCE (1<<12)
> -
> -
> -#define PORTSC_CCS (1<<0)
> -#define PORTSC_PED (1<<1)
> -#define PORTSC_OCA (1<<3)
> -#define PORTSC_PR (1<<4)
> -#define PORTSC_PLS_SHIFT 5
> -#define PORTSC_PLS_MASK 0xf
> -#define PORTSC_PP (1<<9)
> -#define PORTSC_SPEED_SHIFT 10
> -#define PORTSC_SPEED_MASK 0xf
> -#define PORTSC_SPEED_FULL (1<<10)
> -#define PORTSC_SPEED_LOW (2<<10)
> -#define PORTSC_SPEED_HIGH (3<<10)
> -#define PORTSC_SPEED_SUPER (4<<10)
> -#define PORTSC_PIC_SHIFT 14
> -#define PORTSC_PIC_MASK 0x3
> -#define PORTSC_LWS (1<<16)
> -#define PORTSC_CSC (1<<17)
> -#define PORTSC_PEC (1<<18)
> -#define PORTSC_WRC (1<<19)
> -#define PORTSC_OCC (1<<20)
> -#define PORTSC_PRC (1<<21)
> -#define PORTSC_PLC (1<<22)
> -#define PORTSC_CEC (1<<23)
> -#define PORTSC_CAS (1<<24)
> -#define PORTSC_WCE (1<<25)
> -#define PORTSC_WDE (1<<26)
> -#define PORTSC_WOE (1<<27)
> -#define PORTSC_DR (1<<30)
> -#define PORTSC_WPR (1<<31)
> -
> -#define CRCR_RCS (1<<0)
> -#define CRCR_CS (1<<1)
> -#define CRCR_CA (1<<2)
> -#define CRCR_CRR (1<<3)
> -
> -#define IMAN_IP (1<<0)
> -#define IMAN_IE (1<<1)
> -
> -#define ERDP_EHB (1<<3)
> -
> -#define TRB_SIZE 16
> -typedef struct XHCITRB {
> - uint64_t parameter;
> - uint32_t status;
> - uint32_t control;
> - dma_addr_t addr;
> - bool ccs;
> -} XHCITRB;
> -
> -enum {
> - PLS_U0 = 0,
> - PLS_U1 = 1,
> - PLS_U2 = 2,
> - PLS_U3 = 3,
> - PLS_DISABLED = 4,
> - PLS_RX_DETECT = 5,
> - PLS_INACTIVE = 6,
> - PLS_POLLING = 7,
> - PLS_RECOVERY = 8,
> - PLS_HOT_RESET = 9,
> - PLS_COMPILANCE_MODE = 10,
> - PLS_TEST_MODE = 11,
> - PLS_RESUME = 15,
> -};
> -
> -#define CR_LINK TR_LINK
> -
> -#define TRB_C (1<<0)
> -#define TRB_TYPE_SHIFT 10
> -#define TRB_TYPE_MASK 0x3f
> -#define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) &
> TRB_TYPE_MASK)
> -
> -#define TRB_EV_ED (1<<2)
> -
> -#define TRB_TR_ENT (1<<1)
> -#define TRB_TR_ISP (1<<2)
> -#define TRB_TR_NS (1<<3)
> -#define TRB_TR_CH (1<<4)
> -#define TRB_TR_IOC (1<<5)
> -#define TRB_TR_IDT (1<<6)
> -#define TRB_TR_TBC_SHIFT 7
> -#define TRB_TR_TBC_MASK 0x3
> -#define TRB_TR_BEI (1<<9)
> -#define TRB_TR_TLBPC_SHIFT 16
> -#define TRB_TR_TLBPC_MASK 0xf
> -#define TRB_TR_FRAMEID_SHIFT 20
> -#define TRB_TR_FRAMEID_MASK 0x7ff
> -#define TRB_TR_SIA (1<<31)
> -
> -#define TRB_TR_DIR (1<<16)
> -
> -#define TRB_CR_SLOTID_SHIFT 24
> -#define TRB_CR_SLOTID_MASK 0xff
> -#define TRB_CR_EPID_SHIFT 16
> -#define TRB_CR_EPID_MASK 0x1f
> -
> -#define TRB_CR_BSR (1<<9)
> -#define TRB_CR_DC (1<<9)
> -
> -#define TRB_LK_TC (1<<1)
> -
> -#define TRB_INTR_SHIFT 22
> -#define TRB_INTR_MASK 0x3ff
> -#define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) &
> TRB_INTR_MASK)
> -
> -#define EP_TYPE_MASK 0x7
> -#define EP_TYPE_SHIFT 3
> -
> -#define EP_STATE_MASK 0x7
> -#define EP_DISABLED (0<<0)
> -#define EP_RUNNING (1<<0)
> -#define EP_HALTED (2<<0)
> -#define EP_STOPPED (3<<0)
> -#define EP_ERROR (4<<0)
> -
> -#define SLOT_STATE_MASK 0x1f
> -#define SLOT_STATE_SHIFT 27
> -#define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
> -#define SLOT_ENABLED 0
> -#define SLOT_DEFAULT 1
> -#define SLOT_ADDRESSED 2
> -#define SLOT_CONFIGURED 3
> -
> -#define SLOT_CONTEXT_ENTRIES_MASK 0x1f
> -#define SLOT_CONTEXT_ENTRIES_SHIFT 27
> -
> #define get_field(data, field) \
> (((data) >> field##_SHIFT) & field##_MASK)
>
> @@ -223,17 +75,6 @@ enum {
> *data = val_; \
> } while (0)
>
> -typedef enum EPType {
> - ET_INVALID = 0,
> - ET_ISO_OUT,
> - ET_BULK_OUT,
> - ET_INTR_OUT,
> - ET_CONTROL,
> - ET_ISO_IN,
> - ET_BULK_IN,
> - ET_INTR_IN,
> -} EPType;
> -
> typedef struct XHCITransfer {
> XHCIEPContext *epctx;
> USBPacket packet;
> @@ -2736,56 +2577,55 @@ static uint64_t xhci_cap_read(void *ptr, hwaddr
> reg, unsigned size)
> uint32_t ret;
>
> switch (reg) {
> - case 0x00: /* HCIVERSION, CAPLENGTH */
> + case XHCI_HCCAP_CAPLENGTH: /* Covers HCIVERSION and CAPLENGTH */
> ret = 0x01000000 | LEN_CAP;
> break;
> - case 0x04: /* HCSPARAMS 1 */
> + case XHCI_HCCAP_HCSPARAMS1:
> ret = ((xhci->numports_2+xhci->numports_3)<<24)
> | (xhci->numintrs<<8) | xhci->numslots;
> break;
> - case 0x08: /* HCSPARAMS 2 */
> + case XHCI_HCCAP_HCSPARAMS2:
> ret = 0x0000000f;
> break;
> - case 0x0c: /* HCSPARAMS 3 */
> + case XHCI_HCCAP_HCSPARAMS3:
> ret = 0x00000000;
> break;
> - case 0x10: /* HCCPARAMS */
> - if (sizeof(dma_addr_t) == 4) {
> - ret = 0x00080000 | (xhci->max_pstreams_mask << 12);
> - } else {
> - ret = 0x00080001 | (xhci->max_pstreams_mask << 12);
> + case XHCI_HCCAP_HCCPARAMS1:
> + ret = (XHCI_HCCAP_EXTCAP_START >> 2) | (xhci->max_pstreams_mask
> << 12);
>
This doesn't look like it's equivalent to the original code. I think you
want
((XHCI_HCCAP_EXTCAP_START >> 2) << 16) | (xhci->max_pstreams_mask << 12);
That's… not particularly readable either though, so if we're going to break
up the magic numbers here, how about something like:
ret = (XHCI_HCCAP_EXTCAP_START / 4) << XHCI_HCCPARAM_EXTPTR_SHIFT;
ret |= xhci->max_pstreams_mask << XHCI_HCCPARAM_MAXPSASIZE_SHIFT;
> + if (sizeof(dma_addr_t) == 8) {
> + ret |= 0x00000001; /* AC64 */
>
and then this can become
ret |= XHCI_HCCPARAM_AC64;
or something like that.
}
> break;
> - case 0x14: /* DBOFF */
> + case XHCI_HCCAP_DBOFF:
> ret = OFF_DOORBELL;
> break;
> - case 0x18: /* RTSOFF */
> + case XHCI_HCCAP_RTSOFF:
> ret = OFF_RUNTIME;
> break;
>
> /* extended capabilities */
> - case 0x20: /* Supported Protocol:00 */
> + case XHCI_HCCAP_EXTCAP_START + 0x00: /* Supported Protocol:00 */
> ret = 0x02000402; /* USB 2.0 */
> break;
> - case 0x24: /* Supported Protocol:04 */
> + case XHCI_HCCAP_EXTCAP_START + 0x04: /* Supported Protocol:04 */
> ret = 0x20425355; /* "USB " */
> break;
> - case 0x28: /* Supported Protocol:08 */
> + case XHCI_HCCAP_EXTCAP_START + 0x08: /* Supported Protocol:08 */
> ret = (xhci->numports_2 << 8) | (xhci->numports_3 + 1);
> break;
> - case 0x2c: /* Supported Protocol:0c */
> + case XHCI_HCCAP_EXTCAP_START + 0x0c: /* Supported Protocol:0c */
> ret = 0x00000000; /* reserved */
> break;
> - case 0x30: /* Supported Protocol:00 */
> + case XHCI_HCCAP_EXTCAP_START + 0x10: /* Supported Protocol:00 */
> ret = 0x03000002; /* USB 3.0 */
> break;
> - case 0x34: /* Supported Protocol:04 */
> + case XHCI_HCCAP_EXTCAP_START + 0x14: /* Supported Protocol:04 */
> ret = 0x20425355; /* "USB " */
> break;
> - case 0x38: /* Supported Protocol:08 */
> + case XHCI_HCCAP_EXTCAP_START + 0x18: /* Supported Protocol:08 */
> ret = (xhci->numports_3 << 8) | 1;
> break;
> - case 0x3c: /* Supported Protocol:0c */
> + case XHCI_HCCAP_EXTCAP_START + 0x1c: /* Supported Protocol:0c */
> ret = 0x00000000; /* reserved */
> break;
> default:
> @@ -2803,14 +2643,13 @@ static uint64_t xhci_port_read(void *ptr, hwaddr
> reg, unsigned size)
> uint32_t ret;
>
> switch (reg) {
> - case 0x00: /* PORTSC */
> + case XHCI_PORT_PORTSC:
> ret = port->portsc;
> break;
> - case 0x04: /* PORTPMSC */
> - case 0x08: /* PORTLI */
> + case XHCI_PORT_PORTPMSC:
> + case XHCI_PORT_PORTLI:
> ret = 0;
> break;
> - case 0x0c: /* reserved */
>
I think it's worth keeping explicitly unhandled case labels documented like
this. (This one appears to be XHCI_PORT_PORTHLPMC nowadays, I assume it was
reserved in an earlier spec version.)
default:
> trace_usb_xhci_unimplemented("port read", reg);
> ret = 0;
> @@ -2829,7 +2668,7 @@ static void xhci_port_write(void *ptr, hwaddr reg,
> trace_usb_xhci_port_write(port->portnr, reg, val);
>
> switch (reg) {
> - case 0x00: /* PORTSC */
> + case XHCI_PORT_PORTSC:
> /* write-1-to-start bits */
> if (val & PORTSC_WPR) {
> xhci_port_reset(port, true);
> @@ -2880,8 +2719,6 @@ static void xhci_port_write(void *ptr, hwaddr reg,
> xhci_port_notify(port, notify);
> }
> break;
> - case 0x04: /* PORTPMSC */
> - case 0x08: /* PORTLI */
>
Hmm. Looks like PORTLI is actually a read-only register, so writing this
ought to trigger a LOG_GUEST_ERROR. And I don't think it's a bad thing to
explicitly document PORTPMSC as unimplemented. (And I guess that ought to
be a LOG_UNIMP, not a trace, sigh.) The improved logging can be a separate
commit - in fact I don't mind tagging that fix onto my own pending XHCI
patch set, but I think for this commit we ought to keep the case labels
(with the new symbolic constants).
> default:
> trace_usb_xhci_unimplemented("port write", reg);
> }
> @@ -2893,31 +2730,31 @@ static uint64_t xhci_oper_read(void *ptr, hwaddr
> reg, unsigned size)
> uint32_t ret;
>
> switch (reg) {
> - case 0x00: /* USBCMD */
> + case XHCI_OPER_USBCMD:
> ret = xhci->usbcmd;
> break;
> - case 0x04: /* USBSTS */
> + case XHCI_OPER_USBSTS:
> ret = xhci->usbsts;
> break;
> - case 0x08: /* PAGESIZE */
> + case XHCI_OPER_PAGESIZE:
> ret = 1; /* 4KiB */
> break;
> - case 0x14: /* DNCTRL */
> + case XHCI_OPER_DNCTRL:
> ret = xhci->dnctrl;
> break;
> - case 0x18: /* CRCR low */
> + case XHCI_OPER_CRCR_LO:
> ret = xhci->crcr_low & ~0xe;
> break;
> - case 0x1c: /* CRCR high */
> + case XHCI_OPER_CRCR_HI:
> ret = xhci->crcr_high;
> break;
> - case 0x30: /* DCBAAP low */
> + case XHCI_OPER_DCBAAP_LO:
> ret = xhci->dcbaap_low;
> break;
> - case 0x34: /* DCBAAP high */
> + case XHCI_OPER_DCBAAP_HI:
> ret = xhci->dcbaap_high;
> break;
> - case 0x38: /* CONFIG */
> + case XHCI_OPER_CONFIG:
> ret = xhci->config;
> break;
> default:
> @@ -2937,7 +2774,7 @@ static void xhci_oper_write(void *ptr, hwaddr reg,
> trace_usb_xhci_oper_write(reg, val);
>
> switch (reg) {
> - case 0x00: /* USBCMD */
> + case XHCI_OPER_USBCMD:
> if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
> xhci_run(xhci);
> } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
> @@ -2959,19 +2796,19 @@ static void xhci_oper_write(void *ptr, hwaddr reg,
> xhci_intr_update(xhci, 0);
> break;
>
> - case 0x04: /* USBSTS */
> + case XHCI_OPER_USBSTS:
> /* these bits are write-1-to-clear */
> xhci->usbsts &= ~(val &
> (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
> xhci_intr_update(xhci, 0);
> break;
>
> - case 0x14: /* DNCTRL */
> + case XHCI_OPER_DNCTRL:
> xhci->dnctrl = val & 0xffff;
> break;
> - case 0x18: /* CRCR low */
> + case XHCI_OPER_CRCR_LO:
> xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
> break;
> - case 0x1c: /* CRCR high */
> + case XHCI_OPER_CRCR_HI:
> xhci->crcr_high = val;
> if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low &
> CRCR_CRR)) {
> XHCIEvent event = {ER_COMMAND_COMPLETE,
> CC_COMMAND_RING_STOPPED};
> @@ -2984,13 +2821,13 @@ static void xhci_oper_write(void *ptr, hwaddr reg,
> }
> xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
> break;
> - case 0x30: /* DCBAAP low */
> + case XHCI_OPER_DCBAAP_LO:
> xhci->dcbaap_low = val & 0xffffffc0;
> break;
> - case 0x34: /* DCBAAP high */
> + case XHCI_OPER_DCBAAP_HI:
> xhci->dcbaap_high = val;
> break;
> - case 0x38: /* CONFIG */
> + case XHCI_OPER_CONFIG:
> xhci->config = val & 0xff;
> break;
> default:
> @@ -3004,9 +2841,9 @@ static uint64_t xhci_runtime_read(void *ptr, hwaddr
> reg,
> XHCIState *xhci = ptr;
> uint32_t ret = 0;
>
> - if (reg < 0x20) {
> + if (reg < XHCI_OPER_IR0) {
> switch (reg) {
> - case 0x00: /* MFINDEX */
> + case XHCI_OPER_MFINDEX:
> ret = xhci_mfindex_get(xhci) & 0x3fff;
> break;
> default:
> @@ -3014,28 +2851,28 @@ static uint64_t xhci_runtime_read(void *ptr,
> hwaddr reg,
> break;
> }
> } else {
> - int v = (reg - 0x20) / 0x20;
> + int v = (reg - XHCI_OPER_IR0) / XHCI_OPER_IR_SZ;
> XHCIInterrupter *intr = &xhci->intr[v];
> - switch (reg & 0x1f) {
> - case 0x00: /* IMAN */
> + switch (reg & (XHCI_OPER_IR_SZ - 1)) {
> + case XHCI_INTR_IMAN:
> ret = intr->iman;
> break;
> - case 0x04: /* IMOD */
> + case XHCI_INTR_IMOD:
> ret = intr->imod;
> break;
> - case 0x08: /* ERSTSZ */
> + case XHCI_INTR_ERSTSZ:
> ret = intr->erstsz;
> break;
> - case 0x10: /* ERSTBA low */
> + case XHCI_INTR_ERSTBA_LO:
> ret = intr->erstba_low;
> break;
> - case 0x14: /* ERSTBA high */
> + case XHCI_INTR_ERSTBA_HI:
> ret = intr->erstba_high;
> break;
> - case 0x18: /* ERDP low */
> + case XHCI_INTR_ERDP_LO:
> ret = intr->erdp_low;
> break;
> - case 0x1c: /* ERDP high */
> + case XHCI_INTR_ERDP_HI:
> ret = intr->erdp_high;
> break;
> }
> @@ -3054,15 +2891,15 @@ static void xhci_runtime_write(void *ptr, hwaddr
> reg,
>
> trace_usb_xhci_runtime_write(reg, val);
>
> - if (reg < 0x20) {
> + if (reg < XHCI_OPER_IR0) {
> trace_usb_xhci_unimplemented("runtime write", reg);
> return;
> }
> - v = (reg - 0x20) / 0x20;
> + v = (reg - XHCI_OPER_IR0) / XHCI_OPER_IR_SZ;
> intr = &xhci->intr[v];
>
> - switch (reg & 0x1f) {
> - case 0x00: /* IMAN */
> + switch (reg & (XHCI_OPER_IR_SZ - 1)) {
> + case XHCI_INTR_IMAN:
> if (val & IMAN_IP) {
> intr->iman &= ~IMAN_IP;
> }
> @@ -3070,13 +2907,13 @@ static void xhci_runtime_write(void *ptr, hwaddr
> reg,
> intr->iman |= val & IMAN_IE;
> xhci_intr_update(xhci, v);
> break;
> - case 0x04: /* IMOD */
> + case XHCI_INTR_IMOD:
> intr->imod = val;
> break;
> - case 0x08: /* ERSTSZ */
> + case XHCI_INTR_ERSTSZ:
> intr->erstsz = val & 0xffff;
> break;
> - case 0x10: /* ERSTBA low */
> + case XHCI_INTR_ERSTBA_LO:
> if (xhci->nec_quirks) {
> /* NEC driver bug: it doesn't align this to 64 bytes */
> intr->erstba_low = val & 0xfffffff0;
> @@ -3084,11 +2921,11 @@ static void xhci_runtime_write(void *ptr, hwaddr
> reg,
> intr->erstba_low = val & 0xffffffc0;
> }
> break;
> - case 0x14: /* ERSTBA high */
> + case XHCI_INTR_ERSTBA_HI:
> intr->erstba_high = val;
> xhci_er_reset(xhci, v);
> break;
> - case 0x18: /* ERDP low */
> + case XHCI_INTR_ERDP_LO:
> if (val & ERDP_EHB) {
> intr->erdp_low &= ~ERDP_EHB;
> }
> @@ -3103,7 +2940,7 @@ static void xhci_runtime_write(void *ptr, hwaddr reg,
> }
> }
> break;
> - case 0x1c: /* ERDP high */
> + case XHCI_INTR_ERDP_HI:
> intr->erdp_high = val;
> break;
> default:
> --
> 2.45.2
>
>
>
[-- Attachment #2: Type: text/html, Size: 32704 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 5/8] hw/usb/xhci: Move HCD constants to a header and add register constants
2024-12-18 15:08 ` Phil Dennis-Jordan
@ 2024-12-19 1:50 ` Nicholas Piggin
2024-12-20 14:11 ` Phil Dennis-Jordan
0 siblings, 1 reply; 14+ messages in thread
From: Nicholas Piggin @ 2024-12-19 1:50 UTC (permalink / raw)
To: Phil Dennis-Jordan
Cc: qemu-devel, Michael S. Tsirkin, Marcel Apfelbaum, Fabiano Rosas,
Laurent Vivier, Paolo Bonzini, Dmitry Fleytman, Akihiko Odaki,
Sriram Yagnaraman
On Thu Dec 19, 2024 at 1:08 AM AEST, Phil Dennis-Jordan wrote:
> This looks sensible to me overall.
>
> For the new symbolic constants for MMIO register offsets such as
> XHCI_OPER_*, XHCI_INTR_* and so on, I'm wondering if it would be clearer to
> give them all an _OFFSET suffix. It's not perfectly consistent to do so
> across the code base, but quite a few device types do follow that
> convention. In my opinion it improves readability, especially in the header
> file, where these offset constants are frequently mixed in with constant
> values that can be written to or read from these registers.
I'm not strongly attached. I slightly prefer suffix, like
XHCI_HCCAP_REG_CAPLENGTH) for MMIO regs, so all the common
part of the name lines up.
Should the entire codebase have a guideline for memory offset
naming conventions? Or does it not matter that much.
[snip]
> > - case 0x0c: /* HCSPARAMS 3 */
> > + case XHCI_HCCAP_HCSPARAMS3:
> > ret = 0x00000000;
> > break;
> > - case 0x10: /* HCCPARAMS */
> > - if (sizeof(dma_addr_t) == 4) {
> > - ret = 0x00080000 | (xhci->max_pstreams_mask << 12);
> > - } else {
> > - ret = 0x00080001 | (xhci->max_pstreams_mask << 12);
> > + case XHCI_HCCAP_HCCPARAMS1:
> > + ret = (XHCI_HCCAP_EXTCAP_START >> 2) | (xhci->max_pstreams_mask
> > << 12);
> >
>
> This doesn't look like it's equivalent to the original code. I think you
> want
> ((XHCI_HCCAP_EXTCAP_START >> 2) << 16) | (xhci->max_pstreams_mask << 12);
Good catch.
>
> That's… not particularly readable either though, so if we're going to break
> up the magic numbers here, how about something like:
>
> ret = (XHCI_HCCAP_EXTCAP_START / 4) << XHCI_HCCPARAM_EXTPTR_SHIFT;
> ret |= xhci->max_pstreams_mask << XHCI_HCCPARAM_MAXPSASIZE_SHIFT;
>
>
> > + if (sizeof(dma_addr_t) == 8) {
> > + ret |= 0x00000001; /* AC64 */
> >
>
> and then this can become
> ret |= XHCI_HCCPARAM_AC64;
>
> or something like that.
Sure.
[snip]
> > switch (reg) {
> > - case 0x00: /* PORTSC */
> > + case XHCI_PORT_PORTSC:
> > ret = port->portsc;
> > break;
> > - case 0x04: /* PORTPMSC */
> > - case 0x08: /* PORTLI */
> > + case XHCI_PORT_PORTPMSC:
> > + case XHCI_PORT_PORTLI:
> > ret = 0;
> > break;
> > - case 0x0c: /* reserved */
> >
>
> I think it's worth keeping explicitly unhandled case labels documented like
> this. (This one appears to be XHCI_PORT_PORTHLPMC nowadays, I assume it was
> reserved in an earlier spec version.)
Okay.
> default:
> > trace_usb_xhci_unimplemented("port read", reg);
> > ret = 0;
> > @@ -2829,7 +2668,7 @@ static void xhci_port_write(void *ptr, hwaddr reg,
> > trace_usb_xhci_port_write(port->portnr, reg, val);
> >
> > switch (reg) {
> > - case 0x00: /* PORTSC */
> > + case XHCI_PORT_PORTSC:
> > /* write-1-to-start bits */
> > if (val & PORTSC_WPR) {
> > xhci_port_reset(port, true);
> > @@ -2880,8 +2719,6 @@ static void xhci_port_write(void *ptr, hwaddr reg,
> > xhci_port_notify(port, notify);
> > }
> > break;
> > - case 0x04: /* PORTPMSC */
> > - case 0x08: /* PORTLI */
> >
>
> Hmm. Looks like PORTLI is actually a read-only register, so writing this
> ought to trigger a LOG_GUEST_ERROR. And I don't think it's a bad thing to
> explicitly document PORTPMSC as unimplemented. (And I guess that ought to
> be a LOG_UNIMP, not a trace, sigh.) The improved logging can be a separate
> commit - in fact I don't mind tagging that fix onto my own pending XHCI
> patch set, but I think for this commit we ought to keep the case labels
> (with the new symbolic constants).
Okay I'll add back the reserved cases.
Yeah, memory access handling in drivers is really inconsistent all over
the tree. It would be nice if there was some helpers or something that
added common template for access tracing, unimp and guest error logs,
etc.
Thanks,
Nick
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 5/8] hw/usb/xhci: Move HCD constants to a header and add register constants
2024-12-19 1:50 ` Nicholas Piggin
@ 2024-12-20 14:11 ` Phil Dennis-Jordan
0 siblings, 0 replies; 14+ messages in thread
From: Phil Dennis-Jordan @ 2024-12-20 14:11 UTC (permalink / raw)
To: Nicholas Piggin
Cc: qemu-devel, Michael S. Tsirkin, Marcel Apfelbaum, Fabiano Rosas,
Laurent Vivier, Paolo Bonzini, Dmitry Fleytman, Akihiko Odaki,
Sriram Yagnaraman
[-- Attachment #1: Type: text/plain, Size: 5506 bytes --]
On Thu, 19 Dec 2024 at 02:50, Nicholas Piggin <npiggin@gmail.com> wrote:
> On Thu Dec 19, 2024 at 1:08 AM AEST, Phil Dennis-Jordan wrote:
> > This looks sensible to me overall.
> >
> > For the new symbolic constants for MMIO register offsets such as
> > XHCI_OPER_*, XHCI_INTR_* and so on, I'm wondering if it would be clearer
> to
> > give them all an _OFFSET suffix. It's not perfectly consistent to do so
> > across the code base, but quite a few device types do follow that
> > convention. In my opinion it improves readability, especially in the
> header
> > file, where these offset constants are frequently mixed in with constant
> > values that can be written to or read from these registers.
>
> I'm not strongly attached. I slightly prefer suffix, like
> XHCI_HCCAP_REG_CAPLENGTH) for MMIO regs, so all the common
> part of the name lines up.
>
I'm guessing you mean prefix? (_REG_ here) Works fine as well from my point
of view.
> Should the entire codebase have a guideline for memory offset
> naming conventions? Or does it not matter that much.
>
I'm not aware of a *documented* convention.
> [snip]
>
> > > - case 0x0c: /* HCSPARAMS 3 */
> > > + case XHCI_HCCAP_HCSPARAMS3:
> > > ret = 0x00000000;
> > > break;
> > > - case 0x10: /* HCCPARAMS */
> > > - if (sizeof(dma_addr_t) == 4) {
> > > - ret = 0x00080000 | (xhci->max_pstreams_mask << 12);
> > > - } else {
> > > - ret = 0x00080001 | (xhci->max_pstreams_mask << 12);
> > > + case XHCI_HCCAP_HCCPARAMS1:
> > > + ret = (XHCI_HCCAP_EXTCAP_START >> 2) |
> (xhci->max_pstreams_mask
> > > << 12);
> > >
> >
> > This doesn't look like it's equivalent to the original code. I think you
> > want
> > ((XHCI_HCCAP_EXTCAP_START >> 2) << 16) | (xhci->max_pstreams_mask << 12);
>
> Good catch.
>
> >
> > That's… not particularly readable either though, so if we're going to
> break
> > up the magic numbers here, how about something like:
> >
> > ret = (XHCI_HCCAP_EXTCAP_START / 4) << XHCI_HCCPARAM_EXTPTR_SHIFT;
> > ret |= xhci->max_pstreams_mask << XHCI_HCCPARAM_MAXPSASIZE_SHIFT;
> >
> >
> > > + if (sizeof(dma_addr_t) == 8) {
> > > + ret |= 0x00000001; /* AC64 */
> > >
> >
> > and then this can become
> > ret |= XHCI_HCCPARAM_AC64;
> >
> > or something like that.
>
> Sure.
>
> [snip]
>
> > > switch (reg) {
> > > - case 0x00: /* PORTSC */
> > > + case XHCI_PORT_PORTSC:
> > > ret = port->portsc;
> > > break;
> > > - case 0x04: /* PORTPMSC */
> > > - case 0x08: /* PORTLI */
> > > + case XHCI_PORT_PORTPMSC:
> > > + case XHCI_PORT_PORTLI:
> > > ret = 0;
> > > break;
> > > - case 0x0c: /* reserved */
> > >
> >
> > I think it's worth keeping explicitly unhandled case labels documented
> like
> > this. (This one appears to be XHCI_PORT_PORTHLPMC nowadays, I assume it
> was
> > reserved in an earlier spec version.)
>
> Okay.
>
> > default:
> > > trace_usb_xhci_unimplemented("port read", reg);
> > > ret = 0;
> > > @@ -2829,7 +2668,7 @@ static void xhci_port_write(void *ptr, hwaddr
> reg,
> > > trace_usb_xhci_port_write(port->portnr, reg, val);
> > >
> > > switch (reg) {
> > > - case 0x00: /* PORTSC */
> > > + case XHCI_PORT_PORTSC:
> > > /* write-1-to-start bits */
> > > if (val & PORTSC_WPR) {
> > > xhci_port_reset(port, true);
> > > @@ -2880,8 +2719,6 @@ static void xhci_port_write(void *ptr, hwaddr
> reg,
> > > xhci_port_notify(port, notify);
> > > }
> > > break;
> > > - case 0x04: /* PORTPMSC */
> > > - case 0x08: /* PORTLI */
> > >
> >
> > Hmm. Looks like PORTLI is actually a read-only register, so writing this
> > ought to trigger a LOG_GUEST_ERROR. And I don't think it's a bad thing to
> > explicitly document PORTPMSC as unimplemented. (And I guess that ought to
> > be a LOG_UNIMP, not a trace, sigh.) The improved logging can be a
> separate
> > commit - in fact I don't mind tagging that fix onto my own pending XHCI
> > patch set, but I think for this commit we ought to keep the case labels
> > (with the new symbolic constants).
>
> Okay I'll add back the reserved cases.
>
Thanks - I can only speak for myself, but I do tend to find those useful
when first getting into the code for a device. (Plus turning on GUEST_ERROR
and UNIMP logging is usually my first step when debugging issues in a
new-to-me device, and we can only really wire those up if all the labels
are there.)
I've put together a patch to wire up the correct logging for these cases,
and I'll add that to the next iteration of my pending XHCI patch set, so
don't need to bother with that. It'll cause merge conflicts with your patch
but that'll be easy to fix in whichever patch ends up getting merged second.
> Yeah, memory access handling in drivers is really inconsistent all over
> the tree. It would be nice if there was some helpers or something that
> added common template for access tracing, unimp and guest error logs,
> etc.
>
Yeah, it's a bit of a jungle out there in the code base, but there's also
tons of weird edge cases that need handling, so I guess setting hard rules
is just difficult. Still, calling out some positive examples in the
contributor docs might be useful.
> Thanks,
> Nick
>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 6/8] qtest/xhci: Add controller and device setup and ring tests
2024-12-12 8:34 [PATCH 0/8] Add XHCI TR NOOP support, plus PCI, MSIX changes Nicholas Piggin
` (4 preceding siblings ...)
2024-12-12 8:34 ` [PATCH 5/8] hw/usb/xhci: Move HCD constants to a header and add register constants Nicholas Piggin
@ 2024-12-12 8:34 ` Nicholas Piggin
2024-12-12 8:35 ` [PATCH 7/8] hw/usb/xhci: Support TR NOOP commands Nicholas Piggin
2024-12-12 8:35 ` [PATCH 8/8] qtest/xhci: add a test for " Nicholas Piggin
7 siblings, 0 replies; 14+ messages in thread
From: Nicholas Piggin @ 2024-12-12 8:34 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, Michael S. Tsirkin, Marcel Apfelbaum,
Fabiano Rosas, Laurent Vivier, Paolo Bonzini, Dmitry Fleytman,
Akihiko Odaki, Sriram Yagnaraman
Add tests which init the host controller registers to the point where
command and event rings, irqs are operational. Enumerate ports and set
up an attached device context that enables device transfer ring to be
set up and tested.
This test does a bunch of things at once and is not yet well librified,
but it allows testing basic mechanisms and gives a starting point for
further work.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/usb/hcd-xhci.h | 7 +
hw/usb/hcd-xhci.c | 7 -
tests/qtest/usb-hcd-xhci-test.c | 498 +++++++++++++++++++++++++++++++-
3 files changed, 499 insertions(+), 13 deletions(-)
diff --git a/hw/usb/hcd-xhci.h b/hw/usb/hcd-xhci.h
index 5781542f40e..36d8f4c8309 100644
--- a/hw/usb/hcd-xhci.h
+++ b/hw/usb/hcd-xhci.h
@@ -310,6 +310,13 @@ typedef struct XHCIRing {
bool ccs;
} XHCIRing;
+typedef struct XHCIEvRingSeg {
+ uint32_t addr_low;
+ uint32_t addr_high;
+ uint32_t size;
+ uint32_t rsvd;
+} XHCIEvRingSeg;
+
typedef struct XHCIPort {
XHCIState *xhci;
uint32_t portsc;
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index df0421ec326..90273cd317e 100644
--- a/hw/usb/hcd-xhci.c
+++ b/hw/usb/hcd-xhci.c
@@ -136,13 +136,6 @@ struct XHCIEPContext {
QEMUTimer *kick_timer;
};
-typedef struct XHCIEvRingSeg {
- uint32_t addr_low;
- uint32_t addr_high;
- uint32_t size;
- uint32_t rsvd;
-} XHCIEvRingSeg;
-
static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
unsigned int epid, unsigned int streamid);
static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid);
diff --git a/tests/qtest/usb-hcd-xhci-test.c b/tests/qtest/usb-hcd-xhci-test.c
index 0cccfd85a64..8733299e52f 100644
--- a/tests/qtest/usb-hcd-xhci-test.c
+++ b/tests/qtest/usb-hcd-xhci-test.c
@@ -8,17 +8,174 @@
*/
#include "qemu/osdep.h"
+#include "qemu/bswap.h"
+#include "libqtest.h"
+#include "libqos/libqos-pc.h"
#include "libqtest-single.h"
#include "libqos/usb.h"
+#include "hw/pci/pci_ids.h"
+#include "hw/pci/pci_regs.h"
+#include "hw/usb/hcd-xhci.h"
+
+/*** Test Setup & Teardown ***/
+typedef struct XHCIQSlotState {
+ /* In-memory arrays */
+ uint64_t device_context;
+ uint64_t transfer_ring;
+
+ uint32_t tr_trb_entries;
+ uint32_t tr_trb_idx;
+ uint32_t tr_trb_c;
+} XHCIQSlotState;
+
+typedef struct XHCIQState {
+ /* QEMU PCI variables */
+ QOSState *parent;
+ QPCIDevice *dev;
+ QPCIBar bar;
+ uint64_t barsize;
+ uint32_t fingerprint;
+
+ /* In-memory arrays */
+ uint64_t dc_base_array;
+ uint64_t command_ring;
+ uint64_t event_ring_seg;
+ uint64_t event_ring;
+
+ uint32_t cr_trb_entries;
+ uint32_t cr_trb_idx;
+ uint32_t cr_trb_c;
+ uint32_t er_trb_entries;
+ uint32_t er_trb_idx;
+ uint32_t er_trb_c;
+
+ /* Host controller properties */
+ uint32_t rtoff, dboff;
+ uint32_t maxports, maxslots, maxintrs;
+
+ XHCIQSlotState slots[32];
+} XHCIQState;
+
+#define XHCI_NEC_ID (PCI_DEVICE_ID_NEC_UPD720200 << 16 | \
+ PCI_VENDOR_ID_NEC)
+
+/**
+ * Locate, verify, and return a handle to the XHCI device.
+ */
+static QPCIDevice *get_xhci_device(QTestState *qts, uint32_t *fingerprint)
+{
+ QPCIDevice *xhci;
+ uint32_t xhci_fingerprint;
+ QPCIBus *pcibus;
+
+ pcibus = qpci_new_pc(qts, NULL);
+
+ /* Find the XHCI PCI device and verify it's the right one. */
+ xhci = qpci_device_find(pcibus, QPCI_DEVFN(0x1D, 0x0));
+ g_assert(xhci != NULL);
+
+ xhci_fingerprint = qpci_config_readl(xhci, PCI_VENDOR_ID);
+ switch (xhci_fingerprint) {
+ case XHCI_NEC_ID:
+ break;
+ default:
+ /* Unknown device. */
+ g_assert_not_reached();
+ }
+
+ if (fingerprint) {
+ *fingerprint = xhci_fingerprint;
+ }
+ return xhci;
+}
+
+static void free_xhci_device(QPCIDevice *dev)
+{
+ QPCIBus *pcibus = dev ? dev->bus : NULL;
+
+ /* libqos doesn't have a function for this, so free it manually */
+ g_free(dev);
+ qpci_free_pc(pcibus);
+}
+
+/**
+ * Start a Q35 machine and bookmark a handle to the XHCI device.
+ */
+G_GNUC_PRINTF(1, 0)
+static XHCIQState *xhci_vboot(const char *cli, va_list ap)
+{
+ XHCIQState *s;
+
+ s = g_new0(XHCIQState, 1);
+ s->parent = qtest_pc_vboot(cli, ap);
+ alloc_set_flags(&s->parent->alloc, ALLOC_LEAK_ASSERT);
+
+ /* Verify that we have an XHCI device present. */
+ s->dev = get_xhci_device(s->parent->qts, &s->fingerprint);
+ s->bar = qpci_iomap(s->dev, 0, &s->barsize);
+ /* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */
+ qpci_device_enable(s->dev);
+
+ return s;
+}
+
+/**
+ * Start a Q35 machine and bookmark a handle to the XHCI device.
+ */
+G_GNUC_PRINTF(1, 2)
+static XHCIQState *xhci_boot(const char *cli, ...)
+{
+ XHCIQState *s;
+ va_list ap;
+
+ if (cli) {
+ va_start(ap, cli);
+ s = xhci_vboot(cli, ap);
+ va_end(ap);
+ } else {
+ s = xhci_boot("-M q35 "
+ "-device nec-usb-xhci,id=xhci,bus=pcie.0,addr=1d.0 "
+ "-drive id=drive0,if=none,file=null-co://,"
+ "file.read-zeroes=on,format=raw");
+ }
+
+ return s;
+}
+
+/**
+ * Clean up the PCI device, then terminate the QEMU instance.
+ */
+static void xhci_shutdown(XHCIQState *xhci)
+{
+ QOSState *qs = xhci->parent;
+
+ free_xhci_device(xhci->dev);
+ g_free(xhci);
+ qtest_shutdown(qs);
+}
+
+/*** tests ***/
static void test_xhci_hotplug(void)
{
- usb_test_hotplug(global_qtest, "xhci", "1", NULL);
+ XHCIQState *s;
+ QTestState *qts;
+
+ s = xhci_boot(NULL);
+ qts = s->parent->qts;
+
+ usb_test_hotplug(qts, "xhci", "1", NULL);
+
+ xhci_shutdown(s);
}
static void test_usb_uas_hotplug(void)
{
- QTestState *qts = global_qtest;
+ XHCIQState *s;
+ QTestState *qts;
+
+ s = xhci_boot(NULL);
+ qts = s->parent->qts;
qtest_qmp_device_add(qts, "usb-uas", "uas", "{}");
qtest_qmp_device_add(qts, "scsi-hd", "scsihd", "{'drive': 'drive0'}");
@@ -30,25 +187,353 @@ static void test_usb_uas_hotplug(void)
qtest_qmp_device_del(qts, "scsihd");
qtest_qmp_device_del(qts, "uas");
+
+ xhci_shutdown(s);
}
static void test_usb_ccid_hotplug(void)
{
- QTestState *qts = global_qtest;
+ XHCIQState *s;
+ QTestState *qts;
+
+ s = xhci_boot(NULL);
+ qts = s->parent->qts;
qtest_qmp_device_add(qts, "usb-ccid", "ccid", "{}");
qtest_qmp_device_del(qts, "ccid");
/* check the device can be added again */
qtest_qmp_device_add(qts, "usb-ccid", "ccid", "{}");
qtest_qmp_device_del(qts, "ccid");
+
+ xhci_shutdown(s);
+}
+
+static uint64_t xhci_guest_zalloc(XHCIQState *s, uint64_t size)
+{
+ char mem[0x1000];
+ uint64_t ret;
+
+ g_assert(size <= 0x1000);
+
+ memset(mem, 0, size);
+
+ ret = guest_alloc(&s->parent->alloc, size);
+ qtest_memwrite(s->parent->qts, ret, mem, size);
+
+ return ret;
+}
+
+static uint32_t xhci_cap_readl(XHCIQState *s, uint64_t addr)
+{
+ return qpci_io_readl(s->dev, s->bar, addr);
+}
+
+static uint32_t xhci_op_readl(XHCIQState *s, uint64_t addr)
+{
+ return qpci_io_readl(s->dev, s->bar, 0x40 + addr);
+}
+
+static void xhci_op_writel(XHCIQState *s, uint64_t addr, uint32_t value)
+{
+ qpci_io_writel(s->dev, s->bar, 0x40 + addr, value);
+}
+
+static uint32_t xhci_port_readl(XHCIQState *s, uint32_t port, uint64_t addr)
+{
+ return xhci_op_readl(s, 0x400 + port * 0x10 + addr);
+}
+
+static uint32_t xhci_rt_readl(XHCIQState *s, uint64_t addr)
+{
+ return qpci_io_readl(s->dev, s->bar, s->rtoff + addr);
+}
+
+static void xhci_rt_writel(XHCIQState *s, uint64_t addr, uint32_t value)
+{
+ qpci_io_writel(s->dev, s->bar, s->rtoff + addr, value);
}
+static void xhci_db_writel(XHCIQState *s, uint32_t db, uint32_t value)
+{
+ qpci_io_writel(s->dev, s->bar, s->dboff + db * 4, value);
+}
+
+static void wait_event_trb(XHCIQState *s, XHCITRB *trb)
+{
+ XHCITRB t;
+ uint64_t er_addr = s->event_ring + s->er_trb_idx * sizeof(*trb);
+ uint32_t value;
+ guint64 end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND;
+
+ /* Wait for event interrupt */
+
+ do {
+ if (g_get_monotonic_time() >= end_time) {
+ g_error("Timeout expired");
+ }
+ qtest_clock_step(s->parent->qts, 10000);
+
+ value = xhci_op_readl(s, 0x4); /* USBSTS */
+ } while (!(value & USBSTS_EINT));
+
+ value = xhci_rt_readl(s, 0x20 + 0x0); /* IMAN */
+
+ /* With MSI-X enabled, IMAN IP is cleared after raising the interrupt */
+ g_assert(!(value & IMAN_IP));
+
+ /* Ensure MSI-X interrupt is pending */
+ assert(qpci_msix_test_clear_pending(s->dev, 0));
+ /* Then cleared */
+ assert(!qpci_msix_pending(s->dev, 0));
+
+ xhci_op_writel(s, 0x4, USBSTS_EINT); /* USBSTS clear EINT */
+
+ qtest_memread(s->parent->qts, er_addr, &t, sizeof(t));
+
+ trb->parameter = le64_to_cpu(t.parameter);
+ trb->status = le32_to_cpu(t.status);
+ trb->control = le32_to_cpu(t.control);
+
+ g_assert((trb->status >> 24) == CC_SUCCESS);
+ g_assert((trb->control & TRB_C) == s->er_trb_c); /* C bit has been set */
+
+ s->er_trb_idx++;
+ if (s->er_trb_idx == s->er_trb_entries) {
+ s->er_trb_idx = 0;
+ s->er_trb_c ^= 1;
+ }
+ /* Update ERDP to processed TRB addr and EHB bit, which clears EHB */
+ er_addr = s->event_ring + s->er_trb_idx * sizeof(*trb);
+ xhci_rt_writel(s, 0x38, (er_addr & 0xffffffff) | ERDP_EHB);
+}
+
+static void set_link_trb(XHCIQState *s, uint64_t ring, uint32_t c,
+ uint32_t entries)
+{
+ XHCITRB trb;
+
+ g_assert(entries > 1);
+
+ memset(&trb, 0, sizeof(trb));
+ trb.parameter = cpu_to_le64(ring);
+ trb.control = cpu_to_le32(c | /* C */
+ (TR_LINK << TRB_TYPE_SHIFT) |
+ TRB_LK_TC);
+ qtest_memwrite(s->parent->qts, ring + sizeof(trb) * (entries - 1),
+ &trb, sizeof(trb));
+}
+
+static void submit_cr_trb(XHCIQState *s, XHCITRB *trb)
+{
+ XHCITRB t;
+ uint64_t cr_addr = s->command_ring + s->cr_trb_idx * sizeof(*trb);
+
+ trb->control |= s->cr_trb_c; /* C */
+
+ t.parameter = cpu_to_le64(trb->parameter);
+ t.status = cpu_to_le32(trb->status);
+ t.control = cpu_to_le32(trb->control);
+
+ qtest_memwrite(s->parent->qts, cr_addr, &t, sizeof(t));
+ s->cr_trb_idx++;
+ /* Last entry contains the link, so wrap back */
+ if (s->cr_trb_idx == s->cr_trb_entries - 1) {
+ set_link_trb(s, s->command_ring, s->cr_trb_c, s->cr_trb_entries);
+ s->cr_trb_idx = 0;
+ s->cr_trb_c ^= 1;
+ }
+ xhci_db_writel(s, 0, 0); /* doorbell 0 */
+}
+
+/*
+ * This test brings up an endpoint and runs some noops through its command
+ * ring and gets responses back on the event ring.
+ *
+ * This could be librified in future (like AHCI0 to have a way to bring up
+ * an endpoint to test device protocols.
+ */
+static void pci_xhci_stress_rings(void)
+{
+ XHCIQState *s;
+ uint32_t value;
+ uint64_t input_context;
+ XHCIEvRingSeg ev_seg;
+ XHCITRB trb;
+ uint32_t hcsparams1;
+ uint32_t slotid;
+ g_autofree void *mem = g_malloc0(0x1000); /* buffer for writing to guest */
+ int i;
+
+ s = xhci_boot("-M q35 "
+ "-device nec-usb-xhci,id=xhci,bus=pcie.0,addr=1d.0 "
+ "-device usb-storage,bus=xhci.0,drive=drive0 "
+ "-drive id=drive0,if=none,file=null-co://,"
+ "file.read-zeroes=on,format=raw "
+ );
+
+ hcsparams1 = xhci_cap_readl(s, 0x4); /* HCSPARAMS1 */
+ s->maxports = (hcsparams1 >> 24) & 0xff;
+ s->maxintrs = (hcsparams1 >> 8) & 0x3ff;
+ s->maxslots = hcsparams1 & 0xff;
+
+ s->dboff = xhci_cap_readl(s, 0x14); /* DBOFF */
+ s->rtoff = xhci_cap_readl(s, 0x18); /* RTOFF */
+
+ s->dc_base_array = xhci_guest_zalloc(s, 0x800);
+ s->command_ring = xhci_guest_zalloc(s, 0x1000);
+ s->event_ring = xhci_guest_zalloc(s, 0x1000);
+ s->event_ring_seg = xhci_guest_zalloc(s, 0x100);
+
+ /* Arbitrary small sizes so we can make them wrap */
+ s->cr_trb_entries = 0x20;
+ s->cr_trb_c = 1;
+ s->er_trb_entries = 0x10;
+ s->er_trb_c = 1;
+
+ ev_seg.addr_low = cpu_to_le32(s->event_ring & 0xffffffff);
+ ev_seg.addr_high = cpu_to_le32(s->event_ring >> 32);
+ ev_seg.size = cpu_to_le32(0x10);
+ ev_seg.rsvd = 0;
+ qtest_memwrite(s->parent->qts, s->event_ring_seg, &ev_seg, sizeof(ev_seg));
+
+ xhci_op_writel(s, 0x0, USBCMD_HCRST); /* USBCMD */
+ do {
+ value = xhci_op_readl(s, 0x4); /* USBSTS */
+ } while (value & (1 << 11)); /* CNR */
+
+ xhci_op_writel(s, 0x38, s->maxslots); /* CONFIG */
+
+ /* DCBAAP */
+ xhci_op_writel(s, 0x30, s->dc_base_array & 0xffffffff);
+ xhci_op_writel(s, 0x34, s->dc_base_array >> 32);
+
+ /* CRCR */
+ xhci_op_writel(s, 0x18, (s->command_ring & 0xffffffff) | s->cr_trb_c);
+ xhci_op_writel(s, 0x1c, s->command_ring >> 32);
+
+ xhci_rt_writel(s, 0x28, 1); /* ERSTSZ */
+
+ /* ERSTBA */
+ xhci_rt_writel(s, 0x30, s->event_ring_seg & 0xffffffff);
+ xhci_rt_writel(s, 0x34, s->event_ring_seg >> 32);
+
+ /* ERDP */
+ xhci_rt_writel(s, 0x38, s->event_ring & 0xffffffff);
+ xhci_rt_writel(s, 0x3c, s->event_ring >> 32);
+
+ qpci_msix_enable(s->dev);
+ xhci_op_writel(s, 0x0, USBCMD_RS | USBCMD_INTE); /* RUN + INTE */
+
+ /* Enable interrupts on ER IMAN */
+ xhci_rt_writel(s, 0x20, IMAN_IE);
+
+ assert(!qpci_msix_pending(s->dev, 0));
+
+ /* Wrap the command and event rings with no-ops a few times */
+ for (i = 0; i < 100; i++) {
+ /* Issue a command ring no-op */
+ memset(&trb, 0, sizeof(trb));
+ trb.control |= CR_NOOP << TRB_TYPE_SHIFT;
+ trb.control |= TRB_TR_IOC;
+ submit_cr_trb(s, &trb);
+ wait_event_trb(s, &trb);
+ }
+
+ /* Query ports */
+ for (i = 0; i < s->maxports; i++) {
+ value = xhci_port_readl(s, i, 0); /* PORTSC */
+
+ /* Only first port should be attached and enabled */
+ if (i == 0) {
+ g_assert(value & PORTSC_CCS);
+ g_assert(value & PORTSC_PED);
+ /* Port Speed must be identified (non-zero) */
+ g_assert(((value >> PORTSC_SPEED_SHIFT) & PORTSC_SPEED_MASK) != 0);
+ } else {
+ g_assert(!(value & PORTSC_CCS));
+ g_assert(!(value & PORTSC_PED));
+ g_assert(((value >> PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK) == 5);
+ }
+ }
+
+ /* Issue a command ring enable slot */
+ memset(&trb, 0, sizeof(trb));
+ trb.control |= CR_ENABLE_SLOT << TRB_TYPE_SHIFT;
+ trb.control |= TRB_TR_IOC;
+ submit_cr_trb(s, &trb);
+ wait_event_trb(s, &trb);
+ slotid = (trb.control >> TRB_CR_SLOTID_SHIFT) & 0xff;
+
+ s->slots[slotid].transfer_ring = xhci_guest_zalloc(s, 0x1000);
+ s->slots[slotid].tr_trb_entries = 0x10;
+ s->slots[slotid].tr_trb_c = 1;
+
+ /* 32-byte input context size, should check HCCPARAMS1 for 64-byte size */
+ input_context = xhci_guest_zalloc(s, 0x420);
+
+ /* Set input control context */
+ ((uint32_t *)mem)[1] = cpu_to_le32(0x3); /* Add device contexts 0 and 1 */
+ ((uint32_t *)mem)[8] = cpu_to_le32(1 << 27); /* 1 context entry */
+ ((uint32_t *)mem)[9] = cpu_to_le32(1 << 16); /* 1 port number */
+
+ /* Set endpoint 0 context */
+ ((uint32_t *)mem)[16] = 0;
+ ((uint32_t *)mem)[17] = cpu_to_le32((ET_CONTROL << EP_TYPE_SHIFT) |
+ (0x200 << 16)); /* max packet sz XXX? */
+ ((uint32_t *)mem)[18] = cpu_to_le32((s->slots[slotid].transfer_ring &
+ 0xffffffff) | 1); /* DCS=1 */
+ ((uint32_t *)mem)[19] = cpu_to_le32(s->slots[slotid].transfer_ring >> 32);
+ ((uint32_t *)mem)[20] = cpu_to_le32(0x200); /* Average TRB length */
+ qtest_memwrite(s->parent->qts, input_context, mem, 0x420);
+
+ s->slots[slotid].device_context = xhci_guest_zalloc(s, 0x400);
+
+ ((uint64_t *)mem)[0] = cpu_to_le64(s->slots[slotid].device_context);
+ qtest_memwrite(s->parent->qts, s->dc_base_array + 8 * slotid, mem, 8);
+
+ /* Issue a command ring address device */
+ memset(&trb, 0, sizeof(trb));
+ trb.parameter = input_context;
+ trb.control |= CR_ADDRESS_DEVICE << TRB_TYPE_SHIFT;
+ trb.control |= slotid << TRB_CR_SLOTID_SHIFT;
+ submit_cr_trb(s, &trb);
+ wait_event_trb(s, &trb);
+
+ /* XXX: Could check EP state is running */
+
+ /* Shut it down */
+ qpci_msix_disable(s->dev);
+
+ guest_free(&s->parent->alloc, s->slots[slotid].device_context);
+ guest_free(&s->parent->alloc, s->slots[slotid].transfer_ring);
+ guest_free(&s->parent->alloc, input_context);
+ guest_free(&s->parent->alloc, s->event_ring);
+ guest_free(&s->parent->alloc, s->event_ring_seg);
+ guest_free(&s->parent->alloc, s->command_ring);
+ guest_free(&s->parent->alloc, s->dc_base_array);
+
+ xhci_shutdown(s);
+}
+
+/* tests */
int main(int argc, char **argv)
{
int ret;
+ const char *arch;
g_test_init(&argc, &argv, NULL);
+ /* Check architecture */
+ arch = qtest_get_arch();
+ if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
+ g_test_message("Skipping test for non-x86");
+ return 0;
+ }
+
+ if (!qtest_has_device("nec-usb-xhci")) {
+ return 0;
+ }
+
qtest_add_func("/xhci/pci/hotplug", test_xhci_hotplug);
if (qtest_has_device("usb-uas")) {
qtest_add_func("/xhci/pci/hotplug/usb-uas", test_usb_uas_hotplug);
@@ -56,11 +541,12 @@ int main(int argc, char **argv)
if (qtest_has_device("usb-ccid")) {
qtest_add_func("/xhci/pci/hotplug/usb-ccid", test_usb_ccid_hotplug);
}
+ if (qtest_has_device("usb-storage")) {
+ qtest_add_func("/xhci/pci/xhci-stress-rings", pci_xhci_stress_rings);
+ }
- qtest_start("-device nec-usb-xhci,id=xhci"
- " -drive id=drive0,if=none,file=null-co://,"
- "file.read-zeroes=on,format=raw");
ret = g_test_run();
+
qtest_end();
return ret;
--
2.45.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 7/8] hw/usb/xhci: Support TR NOOP commands
2024-12-12 8:34 [PATCH 0/8] Add XHCI TR NOOP support, plus PCI, MSIX changes Nicholas Piggin
` (5 preceding siblings ...)
2024-12-12 8:34 ` [PATCH 6/8] qtest/xhci: Add controller and device setup and ring tests Nicholas Piggin
@ 2024-12-12 8:35 ` Nicholas Piggin
2024-12-12 8:35 ` [PATCH 8/8] qtest/xhci: add a test for " Nicholas Piggin
7 siblings, 0 replies; 14+ messages in thread
From: Nicholas Piggin @ 2024-12-12 8:35 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, Michael S. Tsirkin, Marcel Apfelbaum,
Fabiano Rosas, Laurent Vivier, Paolo Bonzini, Dmitry Fleytman,
Akihiko Odaki, Sriram Yagnaraman
Implement XHCI TR NOOP commands by setting up then immediately
completing the packet.
The IBM AIX XHCI HCD driver uses NOOP commands to check driver and
hardware health, which works after this change.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/usb/hcd-xhci.c | 28 +++++++++++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index 90273cd317e..844521e10f5 100644
--- a/hw/usb/hcd-xhci.c
+++ b/hw/usb/hcd-xhci.c
@@ -1666,6 +1666,20 @@ static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext
return xhci_submit(xhci, xfer, epctx);
}
+static int xhci_noop_transfer(XHCIState *xhci, XHCITransfer *xfer)
+{
+ /*
+ * TR NOOP conceptually probably better not call into USB subsystem
+ * (usb_packet_setup() via xhci_setup_packet()). In practice it
+ * works and avoids code duplication.
+ */
+ if (xhci_setup_packet(xfer) < 0) {
+ return -1;
+ }
+ xhci_try_complete_packet(xfer);
+ return 0;
+}
+
static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
unsigned int epid, unsigned int streamid)
{
@@ -1788,6 +1802,8 @@ static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid)
epctx->kick_active++;
while (1) {
+ bool noop = false;
+
length = xhci_ring_chain_length(xhci, ring);
if (length <= 0) {
if (epctx->type == ET_ISO_OUT || epctx->type == ET_ISO_IN) {
@@ -1816,10 +1832,20 @@ static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid)
epctx->kick_active--;
return;
}
+ if (type == TR_NOOP) {
+ noop = true;
+ }
}
xfer->streamid = streamid;
- if (epctx->epid == 1) {
+ if (noop) {
+ if (length != 1) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: NOOP TR TRB within TRB chain!\n", __func__);
+ /* Undefined behavior, we no-op the entire chain */
+ }
+ xhci_noop_transfer(xhci, xfer);
+ } else if (epctx->epid == 1) {
xhci_fire_ctl_transfer(xhci, xfer);
} else {
xhci_fire_transfer(xhci, xfer, epctx);
--
2.45.2
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 8/8] qtest/xhci: add a test for TR NOOP commands
2024-12-12 8:34 [PATCH 0/8] Add XHCI TR NOOP support, plus PCI, MSIX changes Nicholas Piggin
` (6 preceding siblings ...)
2024-12-12 8:35 ` [PATCH 7/8] hw/usb/xhci: Support TR NOOP commands Nicholas Piggin
@ 2024-12-12 8:35 ` Nicholas Piggin
7 siblings, 0 replies; 14+ messages in thread
From: Nicholas Piggin @ 2024-12-12 8:35 UTC (permalink / raw)
To: qemu-devel
Cc: Nicholas Piggin, Michael S. Tsirkin, Marcel Apfelbaum,
Fabiano Rosas, Laurent Vivier, Paolo Bonzini, Dmitry Fleytman,
Akihiko Odaki, Sriram Yagnaraman
Run some TR NOOP commands through the transfer ring.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
tests/qtest/usb-hcd-xhci-test.c | 41 +++++++++++++++++++++++++++++++--
1 file changed, 39 insertions(+), 2 deletions(-)
diff --git a/tests/qtest/usb-hcd-xhci-test.c b/tests/qtest/usb-hcd-xhci-test.c
index 8733299e52f..93614e55461 100644
--- a/tests/qtest/usb-hcd-xhci-test.c
+++ b/tests/qtest/usb-hcd-xhci-test.c
@@ -326,7 +326,8 @@ static void set_link_trb(XHCIQState *s, uint64_t ring, uint32_t c,
static void submit_cr_trb(XHCIQState *s, XHCITRB *trb)
{
XHCITRB t;
- uint64_t cr_addr = s->command_ring + s->cr_trb_idx * sizeof(*trb);
+ uint64_t cr_addr = s->command_ring +
+ s->cr_trb_idx * sizeof(*trb);
trb->control |= s->cr_trb_c; /* C */
@@ -345,9 +346,35 @@ static void submit_cr_trb(XHCIQState *s, XHCITRB *trb)
xhci_db_writel(s, 0, 0); /* doorbell 0 */
}
+static void submit_tr_trb(XHCIQState *s, int slot, XHCITRB *trb)
+{
+ XHCITRB t;
+ uint64_t tr_addr = s->slots[slot].transfer_ring +
+ s->slots[slot].tr_trb_idx * sizeof(*trb);
+
+ trb->control |= s->slots[slot].tr_trb_c; /* C */
+
+ t.parameter = cpu_to_le64(trb->parameter);
+ t.status = cpu_to_le32(trb->status);
+ t.control = cpu_to_le32(trb->control);
+
+ qtest_memwrite(s->parent->qts, tr_addr, &t, sizeof(t));
+ s->slots[slot].tr_trb_idx++;
+ /* Last entry contains the link, so wrap back */
+ if (s->slots[slot].tr_trb_idx == s->slots[slot].tr_trb_entries - 1) {
+ set_link_trb(s, s->slots[slot].transfer_ring,
+ s->slots[slot].tr_trb_c,
+ s->slots[slot].tr_trb_entries);
+ s->slots[slot].tr_trb_idx = 0;
+ s->slots[slot].tr_trb_c ^= 1;
+ }
+ xhci_db_writel(s, slot, 1); /* doorbell slot, EP0 target */
+}
+
/*
* This test brings up an endpoint and runs some noops through its command
- * ring and gets responses back on the event ring.
+ * ring and gets responses back on the event ring, then brings up a device
+ * context and runs some noops through its transfer ring.
*
* This could be librified in future (like AHCI0 to have a way to bring up
* an endpoint to test device protocols.
@@ -501,6 +528,16 @@ static void pci_xhci_stress_rings(void)
/* XXX: Could check EP state is running */
+ /* Wrap the transfer ring a few times */
+ for (i = 0; i < 100; i++) {
+ /* Issue a transfer ring slot 0 noop */
+ memset(&trb, 0, sizeof(trb));
+ trb.control |= TR_NOOP << TRB_TYPE_SHIFT;
+ trb.control |= TRB_TR_IOC;
+ submit_tr_trb(s, slotid, &trb);
+ wait_event_trb(s, &trb);
+ }
+
/* Shut it down */
qpci_msix_disable(s->dev);
--
2.45.2
^ permalink raw reply related [flat|nested] 14+ messages in thread