From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Atish Patra" <atishp@rivosinc.com>,
"Anup Patel" <anup@brainfault.org>,
"Atish Patra" <atishp@atishpatra.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alexandre Ghiti" <alex@ghiti.fr>
Cc: <kvm@vger.kernel.org>, <kvm-riscv@lists.infradead.org>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
"linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH 1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit
Date: Thu, 08 May 2025 15:31:07 +0200 [thread overview]
Message-ID: <D9QTEAUN0RNE.11G3ZW4IBGL5M@ventanamicro.com> (raw)
In-Reply-To: <20250505-kvm_lazy_enable_stateen-v1-1-3bfc4008373c@rivosinc.com>
2025-05-05T14:39:26-07:00, Atish Patra <atishp@rivosinc.com>:
> Currently, we enable the smstateen bit at vcpu configure time by
> only checking the presence of required ISA extensions.
>
> These bits are not required to be enabled if the guest never uses
> the corresponding architectural state. Enable the smstaeen bits
> at runtime lazily upon first access.
What is the advantage of enabling them lazily?
To make the trap useful, we would have to lazily perform initialization
of the AIA. I think it would require notable changes to AIA, though...
Thanks.
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WARNING: multiple messages have this Message-ID (diff)
From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Atish Patra" <atishp@rivosinc.com>,
"Anup Patel" <anup@brainfault.org>,
"Atish Patra" <atishp@atishpatra.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alexandre Ghiti" <alex@ghiti.fr>
Cc: <kvm@vger.kernel.org>, <kvm-riscv@lists.infradead.org>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
"linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH 1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit
Date: Thu, 08 May 2025 15:31:07 +0200 [thread overview]
Message-ID: <D9QTEAUN0RNE.11G3ZW4IBGL5M@ventanamicro.com> (raw)
In-Reply-To: <20250505-kvm_lazy_enable_stateen-v1-1-3bfc4008373c@rivosinc.com>
2025-05-05T14:39:26-07:00, Atish Patra <atishp@rivosinc.com>:
> Currently, we enable the smstateen bit at vcpu configure time by
> only checking the presence of required ISA extensions.
>
> These bits are not required to be enabled if the guest never uses
> the corresponding architectural state. Enable the smstaeen bits
> at runtime lazily upon first access.
What is the advantage of enabling them lazily?
To make the trap useful, we would have to lazily perform initialization
of the AIA. I think it would require notable changes to AIA, though...
Thanks.
WARNING: multiple messages have this Message-ID (diff)
From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Atish Patra" <atishp@rivosinc.com>,
"Anup Patel" <anup@brainfault.org>,
"Atish Patra" <atishp@atishpatra.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alexandre Ghiti" <alex@ghiti.fr>
Cc: <kvm@vger.kernel.org>, <kvm-riscv@lists.infradead.org>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
"linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH 1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit
Date: Thu, 08 May 2025 15:31:07 +0200 [thread overview]
Message-ID: <D9QTEAUN0RNE.11G3ZW4IBGL5M@ventanamicro.com> (raw)
In-Reply-To: <20250505-kvm_lazy_enable_stateen-v1-1-3bfc4008373c@rivosinc.com>
2025-05-05T14:39:26-07:00, Atish Patra <atishp@rivosinc.com>:
> Currently, we enable the smstateen bit at vcpu configure time by
> only checking the presence of required ISA extensions.
>
> These bits are not required to be enabled if the guest never uses
> the corresponding architectural state. Enable the smstaeen bits
> at runtime lazily upon first access.
What is the advantage of enabling them lazily?
To make the trap useful, we would have to lazily perform initialization
of the AIA. I think it would require notable changes to AIA, though...
Thanks.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2025-05-08 14:19 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-05 21:39 [PATCH 0/5] Enable hstateen bits lazily for the KVM RISC-V Guests Atish Patra
2025-05-05 21:39 ` Atish Patra
2025-05-05 21:39 ` Atish Patra
2025-05-05 21:39 ` [PATCH 1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit Atish Patra
2025-05-05 21:39 ` Atish Patra
2025-05-05 21:39 ` Atish Patra
2025-05-08 13:31 ` Radim Krčmář [this message]
2025-05-08 13:31 ` Radim Krčmář
2025-05-08 13:31 ` Radim Krčmář
2025-05-05 21:39 ` [PATCH 2/5] RISC-V: KVM: Add a hstateen lazy enabler helper function Atish Patra
2025-05-05 21:39 ` Atish Patra
2025-05-05 21:39 ` Atish Patra
2025-05-05 21:39 ` [PATCH 3/5] RISC-V: KVM: Support lazy enabling of siselect and aia bits Atish Patra
2025-05-05 21:39 ` Atish Patra
2025-05-05 21:39 ` Atish Patra
2025-05-05 21:39 ` [PATCH 4/5] RISC-V: KVM: Enable envcfg and sstateen bits lazily Atish Patra
2025-05-05 21:39 ` Atish Patra
2025-05-05 21:39 ` Atish Patra
2025-05-08 13:32 ` Radim Krčmář
2025-05-08 13:32 ` Radim Krčmář
2025-05-08 13:32 ` Radim Krčmář
2025-05-09 22:38 ` Atish Patra
2025-05-09 22:38 ` Atish Patra
2025-05-09 22:38 ` Atish Patra
2025-05-12 10:25 ` Radim Krčmář
2025-05-12 10:25 ` Radim Krčmář
2025-05-12 10:25 ` Radim Krčmář
2025-05-05 21:39 ` [PATCH 5/5] RISC-V: KVM: Remove the boot time enabling of hstateen bits Atish Patra
2025-05-05 21:39 ` Atish Patra
2025-05-05 21:39 ` Atish Patra
2025-05-06 9:24 ` [PATCH 0/5] Enable hstateen bits lazily for the KVM RISC-V Guests Radim Krčmář
2025-05-06 9:24 ` Radim Krčmář
2025-05-06 9:24 ` Radim Krčmář
2025-05-06 18:24 ` Atish Patra
2025-05-06 18:24 ` Atish Patra
2025-05-06 18:24 ` Atish Patra
2025-05-07 14:36 ` Radim Krčmář
2025-05-07 14:36 ` Radim Krčmář
2025-05-07 14:36 ` Radim Krčmář
2025-05-08 0:34 ` Atish Patra
2025-05-08 0:34 ` Atish Patra
2025-05-08 0:34 ` Atish Patra
2025-05-08 13:45 ` Radim Krčmář
2025-05-08 13:45 ` Radim Krčmář
2025-05-08 13:45 ` Radim Krčmář
2025-05-09 22:26 ` Atish Patra
2025-05-09 22:26 ` Atish Patra
2025-05-09 22:26 ` Atish Patra
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