From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Clément Léger" <cleger@rivosinc.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Anup Patel" <anup@brainfault.org>,
"Atish Patra" <atishp@atishpatra.org>,
"Shuah Khan" <shuah@kernel.org>,
"Jonathan Corbet" <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org
Cc: "Samuel Holland" <samuel.holland@sifive.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Deepak Gupta" <debug@rivosinc.com>,
"Charlie Jenkins" <charlie@rivosinc.com>,
"Atish Patra" <atishp@rivosinc.com>,
"linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH v8 14/14] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG
Date: Fri, 23 May 2025 15:08:04 +0200 [thread overview]
Message-ID: <DA3KATTIZQ99.2M1SWQ64M9WX8@ventanamicro.com> (raw)
In-Reply-To: <20250523101932.1594077-15-cleger@rivosinc.com>
2025-05-23T12:19:31+02:00, Clément Léger <cleger@rivosinc.com>:
> SBI_FWFT_MISALIGNED_DELEG needs hedeleg to be modified to delegate
> misaligned load/store exceptions. Save and restore it during CPU
> load/put.
How do you plan to access the value of hedeleg & MIS_DELEG from
userspace?
(I think that modeling medeleg in ONE_REG is a clean solution.)
Thanks.
--
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv
WARNING: multiple messages have this Message-ID (diff)
From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Clément Léger" <cleger@rivosinc.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Anup Patel" <anup@brainfault.org>,
"Atish Patra" <atishp@atishpatra.org>,
"Shuah Khan" <shuah@kernel.org>,
"Jonathan Corbet" <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org
Cc: "Samuel Holland" <samuel.holland@sifive.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Deepak Gupta" <debug@rivosinc.com>,
"Charlie Jenkins" <charlie@rivosinc.com>,
"Atish Patra" <atishp@rivosinc.com>,
"linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH v8 14/14] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG
Date: Fri, 23 May 2025 15:08:04 +0200 [thread overview]
Message-ID: <DA3KATTIZQ99.2M1SWQ64M9WX8@ventanamicro.com> (raw)
In-Reply-To: <20250523101932.1594077-15-cleger@rivosinc.com>
2025-05-23T12:19:31+02:00, Clément Léger <cleger@rivosinc.com>:
> SBI_FWFT_MISALIGNED_DELEG needs hedeleg to be modified to delegate
> misaligned load/store exceptions. Save and restore it during CPU
> load/put.
How do you plan to access the value of hedeleg & MIS_DELEG from
userspace?
(I think that modeling medeleg in ONE_REG is a clean solution.)
Thanks.
WARNING: multiple messages have this Message-ID (diff)
From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Clément Léger" <cleger@rivosinc.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Anup Patel" <anup@brainfault.org>,
"Atish Patra" <atishp@atishpatra.org>,
"Shuah Khan" <shuah@kernel.org>,
"Jonathan Corbet" <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org
Cc: "Samuel Holland" <samuel.holland@sifive.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Deepak Gupta" <debug@rivosinc.com>,
"Charlie Jenkins" <charlie@rivosinc.com>,
"Atish Patra" <atishp@rivosinc.com>,
"linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH v8 14/14] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG
Date: Fri, 23 May 2025 15:08:04 +0200 [thread overview]
Message-ID: <DA3KATTIZQ99.2M1SWQ64M9WX8@ventanamicro.com> (raw)
In-Reply-To: <20250523101932.1594077-15-cleger@rivosinc.com>
2025-05-23T12:19:31+02:00, Clément Léger <cleger@rivosinc.com>:
> SBI_FWFT_MISALIGNED_DELEG needs hedeleg to be modified to delegate
> misaligned load/store exceptions. Save and restore it during CPU
> load/put.
How do you plan to access the value of hedeleg & MIS_DELEG from
userspace?
(I think that modeling medeleg in ONE_REG is a clean solution.)
Thanks.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2025-05-23 13:22 UTC|newest]
Thread overview: 123+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-23 10:19 [PATCH v8 00/14] riscv: add SBI FWFT misaligned exception delegation support Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` [PATCH v8 01/14] riscv: sbi: add Firmware Feature (FWFT) SBI extensions definitions Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` [PATCH v8 02/14] riscv: sbi: remove useless parenthesis Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` [PATCH v8 03/14] riscv: sbi: add new SBI error mappings Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` [PATCH v8 04/14] riscv: sbi: add FWFT extension interface Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` [PATCH v8 05/14] riscv: sbi: add SBI FWFT extension calls Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` [PATCH v8 06/14] riscv: misaligned: request misaligned exception from SBI Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-12-25 10:14 ` Vivian Wang
2025-12-25 10:14 ` Vivian Wang
2025-12-25 10:14 ` Vivian Wang
2025-12-28 13:46 ` Clément Léger
2025-12-28 13:46 ` Clément Léger
2025-12-28 13:46 ` Clément Léger
2025-05-23 10:19 ` [PATCH v8 07/14] riscv: misaligned: use on_each_cpu() for scalar misaligned access probing Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 18:37 ` Charlie Jenkins
2025-05-23 18:37 ` Charlie Jenkins
2025-05-23 18:37 ` Charlie Jenkins
2025-05-23 10:19 ` [PATCH v8 08/14] riscv: misaligned: declare misaligned_access_speed under CONFIG_RISCV_MISALIGNED Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 18:36 ` Charlie Jenkins
2025-05-23 18:36 ` Charlie Jenkins
2025-05-23 18:36 ` Charlie Jenkins
2025-05-29 12:43 ` Andrew Jones
2025-05-29 12:43 ` Andrew Jones
2025-05-29 12:43 ` Andrew Jones
2025-05-23 10:19 ` [PATCH v8 09/14] riscv: misaligned: move emulated access uniformity check in a function Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 18:30 ` Charlie Jenkins
2025-05-23 18:30 ` Charlie Jenkins
2025-05-23 18:30 ` Charlie Jenkins
2025-05-23 19:21 ` Clément Léger
2025-05-23 19:21 ` Clément Léger
2025-05-23 19:21 ` Clément Léger
2025-05-26 8:41 ` Andrew Jones
2025-05-26 8:41 ` Andrew Jones
2025-05-26 8:41 ` Andrew Jones
2025-05-26 9:38 ` Clément Léger
2025-05-26 9:38 ` Clément Léger
2025-05-26 9:38 ` Clément Léger
2025-05-23 10:19 ` [PATCH v8 10/14] riscv: misaligned: add a function to check misalign trap delegability Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 18:39 ` Charlie Jenkins
2025-05-23 18:39 ` Charlie Jenkins
2025-05-23 18:39 ` Charlie Jenkins
2025-05-23 10:19 ` [PATCH v8 11/14] RISC-V: KVM: add SBI extension init()/deinit() functions Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-06-12 13:24 ` Anup Patel
2025-06-12 13:24 ` Anup Patel
2025-06-12 13:24 ` Anup Patel
2025-05-23 10:19 ` [PATCH v8 12/14] RISC-V: KVM: add SBI extension reset callback Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-06-12 13:24 ` Anup Patel
2025-06-12 13:24 ` Anup Patel
2025-06-12 13:24 ` Anup Patel
2025-05-23 10:19 ` [PATCH v8 13/14] RISC-V: KVM: add support for FWFT SBI extension Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 13:05 ` Radim Krčmář
2025-05-23 13:05 ` Radim Krčmář
2025-05-23 13:05 ` Radim Krčmář
2025-05-23 15:29 ` Clément Léger
2025-05-23 15:29 ` Clément Léger
2025-05-23 15:29 ` Clément Léger
2025-05-23 16:27 ` Radim Krčmář
2025-05-23 16:27 ` Radim Krčmář
2025-05-23 16:27 ` Radim Krčmář
2025-05-23 18:02 ` Atish Patra
2025-05-23 18:02 ` Atish Patra
2025-05-23 18:02 ` Atish Patra
2025-05-23 19:23 ` Clément Léger
2025-05-23 19:23 ` Clément Léger
2025-05-23 19:23 ` Clément Léger
2025-05-26 8:58 ` Radim Krčmář
2025-05-26 8:58 ` Radim Krčmář
2025-05-26 8:58 ` Radim Krčmář
2025-06-12 13:25 ` Anup Patel
2025-06-12 13:25 ` Anup Patel
2025-06-12 13:25 ` Anup Patel
2025-05-23 10:19 ` [PATCH v8 14/14] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 10:19 ` Clément Léger
2025-05-23 13:08 ` Radim Krčmář [this message]
2025-05-23 13:08 ` Radim Krčmář
2025-05-23 13:08 ` Radim Krčmář
2025-06-12 13:26 ` Anup Patel
2025-06-12 13:26 ` Anup Patel
2025-06-12 13:26 ` Anup Patel
2025-06-04 18:02 ` [PATCH v8 00/14] riscv: add SBI FWFT misaligned exception delegation support Palmer Dabbelt
2025-06-04 18:02 ` Palmer Dabbelt
2025-06-04 18:02 ` Palmer Dabbelt
2025-06-04 19:32 ` Charlie Jenkins
2025-06-04 19:32 ` Charlie Jenkins
2025-06-04 19:32 ` Charlie Jenkins
2025-06-05 7:12 ` Alexandre Ghiti
2025-06-05 7:12 ` Alexandre Ghiti
2025-06-05 7:12 ` Alexandre Ghiti
2025-06-05 1:30 ` patchwork-bot+linux-riscv
2025-06-05 1:30 ` patchwork-bot+linux-riscv
2025-06-05 1:30 ` patchwork-bot+linux-riscv
2025-08-10 21:12 ` patchwork-bot+linux-riscv
2025-08-10 21:12 ` patchwork-bot+linux-riscv
2025-08-10 21:12 ` patchwork-bot+linux-riscv
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=DA3KATTIZQ99.2M1SWQ64M9WX8@ventanamicro.com \
--to=rkrcmar@ventanamicro.com \
--cc=ajones@ventanamicro.com \
--cc=anup@brainfault.org \
--cc=atishp@atishpatra.org \
--cc=atishp@rivosinc.com \
--cc=charlie@rivosinc.com \
--cc=cleger@rivosinc.com \
--cc=corbet@lwn.net \
--cc=debug@rivosinc.com \
--cc=kvm-riscv@lists.infradead.org \
--cc=kvm@vger.kernel.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-kselftest@vger.kernel.org \
--cc=linux-riscv-bounces@lists.infradead.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=samuel.holland@sifive.com \
--cc=shuah@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.