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From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Anup Patel" <apatel@ventanamicro.com>,
	"Atish Patra" <atish.patra@linux.dev>
Cc: "Palmer Dabbelt" <palmer@dabbelt.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Alexandre Ghiti" <alex@ghiti.fr>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Anup Patel" <anup@brainfault.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Shuah Khan" <shuah@kernel.org>, <kvm@vger.kernel.org>,
	<kvm-riscv@lists.infradead.org>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<linux-kselftest@vger.kernel.org>,
	"linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH 0/6] ONE_REG interface for SBI FWFT extension
Date: Mon, 18 Aug 2025 12:29:10 +0200	[thread overview]
Message-ID: <DC5HEJRMZ84K.34OPU922A7XBE@ventanamicro.com> (raw)
In-Reply-To: <20250814155548.457172-1-apatel@ventanamicro.com>

2025-08-14T21:25:42+05:30, Anup Patel <apatel@ventanamicro.com>:
> This series adds ONE_REG interface for SBI FWFT extension implemented
> by KVM RISC-V.

I think it would be better to ONE_REG the CSRs (medeleg/menvcfg), or at
least expose their CSR fields (each sensible medeleg bit, PMM, ...)
through kvm_riscv_config, than to couple this with SBI/FWFT.

The controlled behavior is defined by the ISA, and userspace might want
to configure the S-mode execution environment even when SBI/FWFT is not
present, which is not possible with the current design.

Is there a benefit in expressing the ISA model through SBI/FWFT?

Thanks.

-- 
kvm-riscv mailing list
kvm-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/kvm-riscv

WARNING: multiple messages have this Message-ID (diff)
From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Anup Patel" <apatel@ventanamicro.com>,
	"Atish Patra" <atish.patra@linux.dev>
Cc: "Palmer Dabbelt" <palmer@dabbelt.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Alexandre Ghiti" <alex@ghiti.fr>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Anup Patel" <anup@brainfault.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Shuah Khan" <shuah@kernel.org>, <kvm@vger.kernel.org>,
	<kvm-riscv@lists.infradead.org>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<linux-kselftest@vger.kernel.org>,
	"linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH 0/6] ONE_REG interface for SBI FWFT extension
Date: Mon, 18 Aug 2025 12:29:10 +0200	[thread overview]
Message-ID: <DC5HEJRMZ84K.34OPU922A7XBE@ventanamicro.com> (raw)
In-Reply-To: <20250814155548.457172-1-apatel@ventanamicro.com>

2025-08-14T21:25:42+05:30, Anup Patel <apatel@ventanamicro.com>:
> This series adds ONE_REG interface for SBI FWFT extension implemented
> by KVM RISC-V.

I think it would be better to ONE_REG the CSRs (medeleg/menvcfg), or at
least expose their CSR fields (each sensible medeleg bit, PMM, ...)
through kvm_riscv_config, than to couple this with SBI/FWFT.

The controlled behavior is defined by the ISA, and userspace might want
to configure the S-mode execution environment even when SBI/FWFT is not
present, which is not possible with the current design.

Is there a benefit in expressing the ISA model through SBI/FWFT?

Thanks.

WARNING: multiple messages have this Message-ID (diff)
From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Anup Patel" <apatel@ventanamicro.com>,
	"Atish Patra" <atish.patra@linux.dev>
Cc: "Palmer Dabbelt" <palmer@dabbelt.com>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Alexandre Ghiti" <alex@ghiti.fr>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Anup Patel" <anup@brainfault.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Shuah Khan" <shuah@kernel.org>, <kvm@vger.kernel.org>,
	<kvm-riscv@lists.infradead.org>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<linux-kselftest@vger.kernel.org>,
	"linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH 0/6] ONE_REG interface for SBI FWFT extension
Date: Mon, 18 Aug 2025 12:29:10 +0200	[thread overview]
Message-ID: <DC5HEJRMZ84K.34OPU922A7XBE@ventanamicro.com> (raw)
In-Reply-To: <20250814155548.457172-1-apatel@ventanamicro.com>

2025-08-14T21:25:42+05:30, Anup Patel <apatel@ventanamicro.com>:
> This series adds ONE_REG interface for SBI FWFT extension implemented
> by KVM RISC-V.

I think it would be better to ONE_REG the CSRs (medeleg/menvcfg), or at
least expose their CSR fields (each sensible medeleg bit, PMM, ...)
through kvm_riscv_config, than to couple this with SBI/FWFT.

The controlled behavior is defined by the ISA, and userspace might want
to configure the S-mode execution environment even when SBI/FWFT is not
present, which is not possible with the current design.

Is there a benefit in expressing the ISA model through SBI/FWFT?

Thanks.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2025-08-18 14:48 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-14 15:55 [PATCH 0/6] ONE_REG interface for SBI FWFT extension Anup Patel
2025-08-14 15:55 ` Anup Patel
2025-08-14 15:55 ` Anup Patel
2025-08-14 15:55 ` [PATCH 1/6] RISC-V: KVM: Set initial value of hedeleg in kvm_arch_vcpu_create() Anup Patel
2025-08-14 15:55   ` Anup Patel
2025-08-14 15:55   ` Anup Patel
2025-08-15 20:04   ` Andrew Jones
2025-08-15 20:04     ` Andrew Jones
2025-08-15 20:04     ` Andrew Jones
2025-08-19  9:01   ` Nutty.Liu
2025-08-19  9:01     ` Nutty.Liu
2025-08-19  9:01     ` Nutty.Liu
2025-08-14 15:55 ` [PATCH 2/6] RISC-V: KVM: Introduce feature specific reset for SBI FWFT Anup Patel
2025-08-14 15:55   ` Anup Patel
2025-08-14 15:55   ` Anup Patel
2025-08-15 20:14   ` Andrew Jones
2025-08-15 20:14     ` Andrew Jones
2025-08-15 20:14     ` Andrew Jones
2025-08-19  9:02   ` Nutty.Liu
2025-08-19  9:02     ` Nutty.Liu
2025-08-19  9:02     ` Nutty.Liu
2025-08-14 15:55 ` [PATCH 3/6] RISC-V: KVM: Introduce optional ONE_REG callbacks for SBI extensions Anup Patel
2025-08-14 15:55   ` Anup Patel
2025-08-14 15:55   ` Anup Patel
2025-08-15 21:00   ` Andrew Jones
2025-08-15 21:00     ` Andrew Jones
2025-08-15 21:00     ` Andrew Jones
2025-08-17 12:04     ` Anup Patel
2025-08-17 12:04       ` Anup Patel
2025-08-17 12:04       ` Anup Patel
2025-08-14 15:55 ` [PATCH 4/6] RISC-V: KVM: Move copy_sbi_ext_reg_indices() to SBI implementation Anup Patel
2025-08-14 15:55   ` Anup Patel
2025-08-14 15:55   ` Anup Patel
2025-08-15 21:04   ` Andrew Jones
2025-08-15 21:04     ` Andrew Jones
2025-08-15 21:04     ` Andrew Jones
2025-08-14 15:55 ` [PATCH 5/6] RISC-V: KVM: Implement ONE_REG interface for SBI FWFT state Anup Patel
2025-08-14 15:55   ` Anup Patel
2025-08-14 15:55   ` Anup Patel
2025-08-14 15:55 ` [PATCH 6/6] KVM: riscv: selftests: Add SBI FWFT to get-reg-list test Anup Patel
2025-08-14 15:55   ` Anup Patel
2025-08-14 15:55   ` Anup Patel
2025-08-18 10:29 ` Radim Krčmář [this message]
2025-08-18 10:29   ` [PATCH 0/6] ONE_REG interface for SBI FWFT extension Radim Krčmář
2025-08-18 10:29   ` Radim Krčmář
2025-08-19  6:30   ` Anup Patel
2025-08-19  6:30     ` Anup Patel
2025-08-19  6:30     ` Anup Patel
2025-08-19 11:43     ` Radim Krčmář
2025-08-19 11:43       ` Radim Krčmář
2025-08-19 11:43       ` Radim Krčmář
2025-08-19 15:52       ` Anup Patel
2025-08-19 15:52         ` Anup Patel
2025-08-19 15:52         ` Anup Patel
2025-08-19 17:35         ` Radim Krčmář
2025-08-19 17:35           ` Radim Krčmář
2025-08-19 17:35           ` Radim Krčmář
2025-08-21  6:26           ` Anup Patel
2025-08-21  6:26             ` Anup Patel
2025-08-21  6:26             ` Anup Patel

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