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From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Conor Dooley" <conor@kernel.org>,
	"Yunhui Cui" <cuiyunhui@bytedance.com>
Cc: <paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
	<aou@eecs.berkeley.edu>, <alex@ghiti.fr>,
	<luxu.kernel@bytedance.com>, <atishp@rivosinc.com>,
	<cleger@rivosinc.com>, <ajones@ventanamicro.com>,
	<apatel@ventanamicro.com>, <linux-kernel@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <songshuaishuai@tinylab.org>,
	<bjorn@rivosinc.com>, <charlie@rivosinc.com>,
	<masahiroy@kernel.org>, <valentina.fernandezalanis@microchip.com>,
	<jassisinghbrar@gmail.com>, <conor.dooley@microchip.com>,
	"linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH 3/3] riscv: crash: use NMI to stop the CPU
Date: Tue, 28 Oct 2025 13:36:20 +0100	[thread overview]
Message-ID: <DDTYKLFUE3M0.17GD0S4OSQG16@ventanamicro.com> (raw)
In-Reply-To: <20251028-scallion-list-c8aa5f350286@spud>

2025-10-28T10:42:12+00:00, Conor Dooley <conor@kernel.org>:
> On Mon, Oct 27, 2025 at 09:34:31PM +0800, Yunhui Cui wrote:
>> NMI is more robust than IPI for stopping CPUs during crashes,
>> especially with interrupts disabled. Add SBI_SSE_EVENT_LOCAL_CRASH_NMI
>> eventid to implement NMI for stopping CPUs.
>> 
>> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
>> ---
>> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
>> @@ -487,6 +487,7 @@ enum sbi_sse_attr_id {
>>  #define SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS	0x00108000
>>  #define SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED	0xffff0000
>>  #define SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI		0xffff0001
>> +#define SBI_SSE_EVENT_LOCAL_CRASH_NMI		0xffff0002

This event isn't defined in the SBI pull request.

I assume it's a pure software event that the platform shouldn't inject.
If we want to reserve more events for software use, why not make them
generic, like SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED?

Thanks.

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http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Conor Dooley" <conor@kernel.org>,
	"Yunhui Cui" <cuiyunhui@bytedance.com>
Cc: <paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
	<aou@eecs.berkeley.edu>, <alex@ghiti.fr>,
	<luxu.kernel@bytedance.com>, <atishp@rivosinc.com>,
	<cleger@rivosinc.com>, <ajones@ventanamicro.com>,
	<apatel@ventanamicro.com>, <linux-kernel@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <songshuaishuai@tinylab.org>,
	<bjorn@rivosinc.com>, <charlie@rivosinc.com>,
	<masahiroy@kernel.org>, <valentina.fernandezalanis@microchip.com>,
	<jassisinghbrar@gmail.com>, <conor.dooley@microchip.com>,
	"linux-riscv" <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH 3/3] riscv: crash: use NMI to stop the CPU
Date: Tue, 28 Oct 2025 13:36:20 +0100	[thread overview]
Message-ID: <DDTYKLFUE3M0.17GD0S4OSQG16@ventanamicro.com> (raw)
In-Reply-To: <20251028-scallion-list-c8aa5f350286@spud>

2025-10-28T10:42:12+00:00, Conor Dooley <conor@kernel.org>:
> On Mon, Oct 27, 2025 at 09:34:31PM +0800, Yunhui Cui wrote:
>> NMI is more robust than IPI for stopping CPUs during crashes,
>> especially with interrupts disabled. Add SBI_SSE_EVENT_LOCAL_CRASH_NMI
>> eventid to implement NMI for stopping CPUs.
>> 
>> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
>> ---
>> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
>> @@ -487,6 +487,7 @@ enum sbi_sse_attr_id {
>>  #define SBI_SSE_EVENT_GLOBAL_LOW_PRIO_RAS	0x00108000
>>  #define SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED	0xffff0000
>>  #define SBI_SSE_EVENT_LOCAL_UNKNOWN_NMI		0xffff0001
>> +#define SBI_SSE_EVENT_LOCAL_CRASH_NMI		0xffff0002

This event isn't defined in the SBI pull request.

I assume it's a pure software event that the platform shouldn't inject.
If we want to reserve more events for software use, why not make them
generic, like SBI_SSE_EVENT_LOCAL_SOFTWARE_INJECTED?

Thanks.

  reply	other threads:[~2025-10-28 12:36 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-27 13:34 [PATCH 0/3] Add NMI Support to RISC-V via SSE Yunhui Cui
2025-10-27 13:34 ` Yunhui Cui
2025-10-27 13:34 ` [PATCH 1/3] drivers: firmware: riscv: add SSE NMI support Yunhui Cui
2025-10-27 13:34   ` Yunhui Cui
2025-10-28 10:53   ` Conor Dooley
2025-10-28 10:53     ` Conor Dooley
2025-10-27 13:34 ` [PATCH 2/3] riscv: crash: move IPI crash handling logic to crash.c Yunhui Cui
2025-10-27 13:34   ` Yunhui Cui
2025-10-27 13:34 ` [PATCH 3/3] riscv: crash: use NMI to stop the CPU Yunhui Cui
2025-10-27 13:34   ` Yunhui Cui
2025-10-28 10:42   ` Conor Dooley
2025-10-28 10:42     ` Conor Dooley
2025-10-28 12:36     ` Radim Krčmář [this message]
2025-10-28 12:36       ` Radim Krčmář
2025-11-03 14:10       ` [External] " yunhui cui
2025-11-03 14:10         ` yunhui cui
2025-11-03 17:23         ` Radim Krčmář
2025-11-03 17:23           ` Radim Krčmář
2025-11-03 13:36     ` yunhui cui
2025-11-03 13:36       ` yunhui cui
2025-10-30  8:46   ` Atish Patra
2025-10-30  8:46     ` Atish Patra
2025-10-31  1:24     ` Bagas Sanjaya
2025-10-31  1:24       ` Bagas Sanjaya

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