From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: <frank.chang@sifive.com>, <qemu-devel@nongnu.org>
Cc: "Palmer Dabbelt" <palmer@dabbelt.com>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Weiwei Li" <liwei1518@gmail.com>,
"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
"open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>,
<qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org>
Subject: Re: [PATCH v2 2/6] target/riscv: Add a helper to return the current effective priv mode
Date: Tue, 25 Nov 2025 15:59:00 +0100 [thread overview]
Message-ID: <DEHV52Y49XZ0.1VF1MA5VMXMCV@ventanamicro.com> (raw)
In-Reply-To: <20251121050413.3718427-3-frank.chang@sifive.com>
2025-11-21T13:04:09+08:00, <frank.chang@sifive.com>:
> From: Frank Chang <frank.chang@sifive.com>
>
> This helper returns the current effective privilege mode.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> @@ -38,6 +38,46 @@
> +bool riscv_cpu_eff_priv(CPURISCVState *env, int *priv, bool *virt)
I wonder if this function shouldn't be defined in a header file, so it
can be inlined, because returning values through pointers is quite
inefficient,
> +{
> +#ifndef CONFIG_USER_ONLY
> + int mode = env->priv;
> + bool virt_enabled = env->virt_enabled;
> + bool mode_modified = false;
> +
> +#ifndef CONFIG_USER_ONLY
We know CONFIG_USER_ONLY is not defined at this point.
> + if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) {
> + mode = get_field(env->mstatus, MSTATUS_MPP);
> + virt_enabled = get_field(env->mstatus, MSTATUS_MPV) && (mode != PRV_M);
> + mode_modified = true;
> + }
> +#endif
> +
> + if (priv) {
> + *priv = mode;
> + }
> +
> + if (virt) {
> + *virt = virt_enabled;
> + }
> +
> + return mode_modified;
> +#else
> + *priv = env->priv;
Since it's #ifdef CONFIG_USER_ONLY, we can just say
*priv = PRV_U;
> + *virt = false;
> + return false;
> +#endif
> +}
> +
> int riscv_env_mmu_index(CPURISCVState *env, bool ifetch)
> {
> #ifdef CONFIG_USER_ONLY
> @@ -45,19 +85,14 @@ int riscv_env_mmu_index(CPURISCVState *env, bool ifetch)
> #else
> bool virt = env->virt_enabled;
> int mode = env->priv;
> + bool mode_modified = false;
>
> /* All priv -> mmu_idx mapping are here */
> if (!ifetch) {
> - uint64_t status = env->mstatus;
> -
> - if (mode == PRV_M && get_field(status, MSTATUS_MPRV)) {
> - mode = get_field(env->mstatus, MSTATUS_MPP);
> - virt = get_field(env->mstatus, MSTATUS_MPV) &&
> - (mode != PRV_M);
> - if (virt) {
> - status = env->vsstatus;
> - }
> - }
> + mode_modified = riscv_cpu_eff_priv(env, &mode, &virt);
> + uint64_t status = (mode_modified && virt) ? env->vsstatus :
> + env->mstatus;
It is likely a bug that MPRV=1+MPV=1 behaves differently from virt=1,
but your patch preserves the current behavior, as it should.
I had a few nitpicks, but important parts seem fine
Reviewed-by: Radim Krčmář <rkrcmar@ventanamicro.com>
Thanks.
next prev parent reply other threads:[~2025-11-25 15:00 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-21 5:04 [PATCH v2 0/6] Fix Zjpm implementation frank.chang
2025-11-21 5:04 ` [PATCH v2 1/6] target/riscv: fix address masking frank.chang
2025-11-21 5:04 ` [PATCH v2 2/6] target/riscv: Add a helper to return the current effective priv mode frank.chang
2025-11-25 14:59 ` Radim Krčmář [this message]
2025-12-11 16:39 ` Frank Chang
2025-11-21 5:04 ` [PATCH v2 3/6] target/riscv: Fix pointer masking PMM field selection logic frank.chang
2025-11-25 15:25 ` Radim Krčmář
2025-12-11 16:41 ` Frank Chang
2025-11-21 5:04 ` [PATCH v2 4/6] target/riscv: Fix pointer masking for virtual-machine load/store insns frank.chang
2025-11-25 15:28 ` Radim Krčmář
2025-11-21 5:04 ` [PATCH v2 5/6] target/riscv: Rename riscv_pm_get_virt_pmm() to riscv_pm_get_vm_ldst_pmm() frank.chang
2025-11-21 5:04 ` [PATCH v2 6/6] target/riscv: Fix pointer masking translation mode check bug frank.chang
2025-11-25 15:41 ` Radim Krčmář
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