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From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: <frank.chang@sifive.com>, <qemu-devel@nongnu.org>
Cc: "Palmer Dabbelt" <palmer@dabbelt.com>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Weiwei Li" <liwei1518@gmail.com>,
	"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
	"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
	"open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>,
	<qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org>
Subject: Re: [PATCH v2 3/6] target/riscv: Fix pointer masking PMM field selection logic
Date: Tue, 25 Nov 2025 16:25:45 +0100	[thread overview]
Message-ID: <DEHVPKNHJOPC.2TGKLMGEUF617@ventanamicro.com> (raw)
In-Reply-To: <20251121050413.3718427-4-frank.chang@sifive.com>

2025-11-21T13:04:10+08:00, <frank.chang@sifive.com>:
> From: Frank Chang <frank.chang@sifive.com>
>
> mstatus.MPV only records the previous virtualization state, and does not
> affect pointer masking according to the Zjpm specification.
>
> This patch rewrites riscv_pm_get_pmm() to follow the architectural
> definition of Smmpm, Smnpm, and Ssnpm.
>
> The resulting PMM selection logic for each mode is summarized below:
>
>   * mstatus.MXR = 1: pointer masking disabled
>
>   * Smmpm + Smnpm + Ssnpm:
>       M-mode:  mseccfg.PMM
>       S-mode:  menvcfg.PMM
>       U-mode:  senvcfg.PMM
>       VS-mode: henvcfg.PMM
>       VU-mode: senvcfg.PMM
>
>   * Smmpm + Smnpm (RVS implemented):
>       M-mode:  mseccfg.PMM
>       S-mode:  menvcfg.PMM
>       U/VS/VU: disabled (Ssnpm not present)
>
>   * Smmpm + Smnpm (RVS not implemented):
>       M-mode:  mseccfg.PMM
>       U-mode:  menvcfg.PMM
>       S/VS/VU: disabled (no S-mode)
>
>   * Smmpm only:
>       M-mode:  mseccfg.PMM
>       Other existing modes: pointer masking disabled
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>  RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)
>  {
>  #ifndef CONFIG_USER_ONLY
> -    int priv_mode = cpu_address_mode(env);
> +    int priv_mode;
> +    bool virt;
>  
> -    if (get_field(env->mstatus, MSTATUS_MPRV) &&
> -        get_field(env->mstatus, MSTATUS_MXR)) {
> +    if (get_field(env->mstatus, MSTATUS_MXR)) {
>          return PMM_FIELD_DISABLED;
>      }

MSTATUS_MXR doesn't disable Pointer masking in M-mode, and we also need
to consider virt, where vsstatus.MXR is in effect as well.

>  
> +    riscv_cpu_eff_priv(env, &priv_mode, &virt);

I think you could put something like this here:

      if ((mode != PRV_M && get_field(env->mstatus, MSTATUS_MXR)) ||
          (virt && get_field(env->vsstatus, MSTATUS_MXR))) {
          return PMM_FIELD_DISABLED;
      }

>      /* Get current PMM field */
>      switch (priv_mode) {
>      case PRV_M:
> @@ -189,22 +222,30 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)
>      case PRV_U:
> -        if (riscv_has_ext(env, RVS)) {
> +        if (!virt) {
>              if (riscv_cpu_cfg(env)->ext_ssnpm) {
>                  return get_field(env->senvcfg, SENVCFG_PMM);
>              }
> -        } else {
> +
>              if (riscv_cpu_cfg(env)->ext_smnpm) {
> -                return get_field(env->menvcfg, MENVCFG_PMM);
> +                if (!riscv_has_ext(env, RVS)) {
> +                    return get_field(env->menvcfg, MENVCFG_PMM);
> +                }
> +            }
> +        } else {
> +            if (riscv_cpu_cfg(env)->ext_ssnpm) {
> +                return get_field(env->senvcfg, SENVCFG_PMM);
>              }
>          }

virt doesn't really matter, the original code was correct.

Thanks.


  reply	other threads:[~2025-11-25 15:27 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-21  5:04 [PATCH v2 0/6] Fix Zjpm implementation frank.chang
2025-11-21  5:04 ` [PATCH v2 1/6] target/riscv: fix address masking frank.chang
2025-11-21  5:04 ` [PATCH v2 2/6] target/riscv: Add a helper to return the current effective priv mode frank.chang
2025-11-25 14:59   ` Radim Krčmář
2025-12-11 16:39     ` Frank Chang
2025-11-21  5:04 ` [PATCH v2 3/6] target/riscv: Fix pointer masking PMM field selection logic frank.chang
2025-11-25 15:25   ` Radim Krčmář [this message]
2025-12-11 16:41     ` Frank Chang
2025-11-21  5:04 ` [PATCH v2 4/6] target/riscv: Fix pointer masking for virtual-machine load/store insns frank.chang
2025-11-25 15:28   ` Radim Krčmář
2025-11-21  5:04 ` [PATCH v2 5/6] target/riscv: Rename riscv_pm_get_virt_pmm() to riscv_pm_get_vm_ldst_pmm() frank.chang
2025-11-21  5:04 ` [PATCH v2 6/6] target/riscv: Fix pointer masking translation mode check bug frank.chang
2025-11-25 15:41   ` Radim Krčmář

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