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From: Rick Bronson <rick@efn.org>
To: linux-omap@vger.kernel.org
Subject: Re: ARM: OMAP3: Fix get_irqnr_and_base to clear spurious interrupt bits
Date: Wed, 22 Oct 2008 10:48:37 -0700	[thread overview]
Message-ID: <E1Kshoz-0002rO-61@amazonia.comcast.net> (raw)


  Sorry if I'm late in the game for changes to entry-macro.S but I
worked on this code a bit ago and have been testing it.  What I have,
I think, is a little more straight forward.  Note that it doesn't have
the added mask for the spurious bits, but it does check for
spurious interrupts and handles them.

  Rick



--- linux-omap-2.6/arch/arm/plat-omap/include/mach/entry-macro.S.~1~	2008-10-16 13:33:31.000000000 -0700
+++ linux-omap-2.6/arch/arm/plat-omap/include/mach/entry-macro.S	2008-10-17 11:38:18.000000000 -0700
@@ -65,7 +65,11 @@
 #include <mach/omap34xx.h>
 #endif
 
-#define INTCPS_SIR_IRQ_OFFSET	0x0040		/* Active interrupt number */
+#define INTCPS_SIR_IRQ_OFFSET	0x0040	/* Active interrupt number */
+#define INTCPS_CONTROL		0x0048	/* new interrupt agreement bits */
+#define INTCPS_PENDING_IRQ_1	0x0098	/* IRQ pending reg 1 */
+#define INTCPS_PENDING_IRQ_2	0x00b8	/* IRQ pending reg 2 */
+#define INTCPS_PENDING_IRQ_3	0x00d8	/* IRQ pending reg 3 */
 
 		.macro	disable_fiq
 		.endm
@@ -78,17 +82,19 @@
 
 		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
 		ldr	\base, =OMAP2_VA_IC_BASE
-		ldr	\irqnr, [\base, #0x98] /* IRQ pending reg 1 */
-		cmp	\irqnr, #0x0
-		bne	2222f
-		ldr	\irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
-		cmp	\irqnr, #0x0
-		bne	2222f
-		ldr	\irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
-		cmp	\irqnr, #0x0
-2222:
-		ldrne	\irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
-
+		ldr	\irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
+		cmp	\irqnr, #0  /* check for negative */
+		movmi	\tmp, #0x1 /* Ack the spurious irq, this lets it
+					* generate a bad irq error message,
+					* but prevents infinitely repeating
+					* irq.
+					*/
+		strmi	\tmp, [\base, #INTCPS_CONTROL]
+		ldr	\irqstat, [\base, #INTCPS_PENDING_IRQ_1] /* IRQ pending reg 1 */
+		ldr	\tmp, [\base, #INTCPS_PENDING_IRQ_2] /* IRQ pending reg 2 */
+		orr	\irqstat, \irqstat, \tmp  /* or them all together */
+		ldr	\tmp, [\base, #INTCPS_PENDING_IRQ_3] /* IRQ pending reg 3 */
+		orrs	\irqstat, \irqstat, \tmp  /* set condition code Z if interrupt */
 		.endm
 
 		.macro	irq_prio_table

             reply	other threads:[~2008-10-22 17:48 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2008-10-22 17:48 Rick Bronson [this message]
2008-10-22 18:30 ` ARM: OMAP3: Fix get_irqnr_and_base to clear spurious interrupt bits Tony Lindgren
  -- strict thread matches above, loose matches on Subject: below --
2008-10-28 16:10 Rick Bronson
2008-10-28 16:31 ` Tony Lindgren
2008-10-31 19:27 ` Tony Lindgren
2008-10-24  4:14 Rick Bronson
2008-10-23 18:13 Rick Bronson
2008-10-23 18:21 ` Tony Lindgren
2008-10-23 17:54 Rick Bronson
2008-10-23  3:29 Rick Bronson
2008-10-23 15:43 ` Tony Lindgren
2008-10-21  4:58 Tony Lindgren
2008-10-21 20:09 ` Felipe Contreras
2008-10-21 20:37   ` Tony Lindgren
2008-10-21 21:34     ` Felipe Contreras
2008-10-21 22:02       ` Tony Lindgren
2008-10-21 23:25         ` Tony Lindgren
2008-10-22 14:46         ` Felipe Contreras
2008-10-22 21:30           ` Nathan Monson
2008-10-22 21:40             ` Felipe Contreras

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