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From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
To: Catalin Marinas <catalin.marinas@arm.com>,
	Jonathan Corbet <corbet@lwn.net>, Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org
Subject: [PATCH v2 01/16] arm64: provide cpu_replace_ttbr1_phys()
Date: Thu, 27 Jul 2023 16:30:00 +0100	[thread overview]
Message-ID: <E1qP2wC-001CWc-DF@rmk-PC.armlinux.org.uk> (raw)
In-Reply-To: <ZMKNYEkM7YnrDtOt@shell.armlinux.org.uk>

Provide a version of cpu_replace_ttbr1_phys() which operates using a
physical address rather than the virtual address of the page tables.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
 arch/arm64/include/asm/mmu_context.h | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index a6fb325424e7..42085b2b1d92 100644
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -152,7 +152,7 @@ static inline void cpu_install_ttbr0(phys_addr_t ttbr0, unsigned long t0sz)
  * Atomically replaces the active TTBR1_EL1 PGD with a new VA-compatible PGD,
  * avoiding the possibility of conflicting TLB entries being allocated.
  */
-static inline void cpu_replace_ttbr1(pgd_t *pgdp, pgd_t *idmap)
+static inline void cpu_replace_ttbr1_phys(phys_addr_t pgd_phys, pgd_t *idmap)
 {
 	typedef void (ttbr_replace_func)(phys_addr_t);
 	extern ttbr_replace_func idmap_cpu_replace_ttbr1;
@@ -160,9 +160,10 @@ static inline void cpu_replace_ttbr1(pgd_t *pgdp, pgd_t *idmap)
 	unsigned long daif;
 
 	/* phys_to_ttbr() zeros lower 2 bits of ttbr with 52-bit PA */
-	phys_addr_t ttbr1 = phys_to_ttbr(virt_to_phys(pgdp));
+	phys_addr_t ttbr1 = phys_to_ttbr(pgd_phys);
 
-	if (system_supports_cnp() && !WARN_ON(pgdp != lm_alias(swapper_pg_dir))) {
+	if (system_supports_cnp() &&
+	    !WARN_ON(pgd_phys != virt_to_phys(lm_alias(swapper_pg_dir)))) {
 		/*
 		 * cpu_replace_ttbr1() is used when there's a boot CPU
 		 * up (i.e. cpufeature framework is not up yet) and
@@ -189,6 +190,11 @@ static inline void cpu_replace_ttbr1(pgd_t *pgdp, pgd_t *idmap)
 	cpu_uninstall_idmap();
 }
 
+static inline void __nocfi cpu_replace_ttbr1(pgd_t *pgdp, pgd_t *idmap)
+{
+	cpu_replace_ttbr1_phys(virt_to_phys(pgdp), idmap);
+}
+
 /*
  * It would be nice to return ASIDs back to the allocator, but unfortunately
  * that introduces a race with a generation rollover where we could erroneously
-- 
2.30.2


WARNING: multiple messages have this Message-ID (diff)
From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
To: Catalin Marinas <catalin.marinas@arm.com>,
	Jonathan Corbet <corbet@lwn.net>, Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org
Subject: [PATCH v2 01/16] arm64: provide cpu_replace_ttbr1_phys()
Date: Thu, 27 Jul 2023 16:30:00 +0100	[thread overview]
Message-ID: <E1qP2wC-001CWc-DF@rmk-PC.armlinux.org.uk> (raw)
In-Reply-To: <ZMKNYEkM7YnrDtOt@shell.armlinux.org.uk>

Provide a version of cpu_replace_ttbr1_phys() which operates using a
physical address rather than the virtual address of the page tables.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
 arch/arm64/include/asm/mmu_context.h | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index a6fb325424e7..42085b2b1d92 100644
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -152,7 +152,7 @@ static inline void cpu_install_ttbr0(phys_addr_t ttbr0, unsigned long t0sz)
  * Atomically replaces the active TTBR1_EL1 PGD with a new VA-compatible PGD,
  * avoiding the possibility of conflicting TLB entries being allocated.
  */
-static inline void cpu_replace_ttbr1(pgd_t *pgdp, pgd_t *idmap)
+static inline void cpu_replace_ttbr1_phys(phys_addr_t pgd_phys, pgd_t *idmap)
 {
 	typedef void (ttbr_replace_func)(phys_addr_t);
 	extern ttbr_replace_func idmap_cpu_replace_ttbr1;
@@ -160,9 +160,10 @@ static inline void cpu_replace_ttbr1(pgd_t *pgdp, pgd_t *idmap)
 	unsigned long daif;
 
 	/* phys_to_ttbr() zeros lower 2 bits of ttbr with 52-bit PA */
-	phys_addr_t ttbr1 = phys_to_ttbr(virt_to_phys(pgdp));
+	phys_addr_t ttbr1 = phys_to_ttbr(pgd_phys);
 
-	if (system_supports_cnp() && !WARN_ON(pgdp != lm_alias(swapper_pg_dir))) {
+	if (system_supports_cnp() &&
+	    !WARN_ON(pgd_phys != virt_to_phys(lm_alias(swapper_pg_dir)))) {
 		/*
 		 * cpu_replace_ttbr1() is used when there's a boot CPU
 		 * up (i.e. cpufeature framework is not up yet) and
@@ -189,6 +190,11 @@ static inline void cpu_replace_ttbr1(pgd_t *pgdp, pgd_t *idmap)
 	cpu_uninstall_idmap();
 }
 
+static inline void __nocfi cpu_replace_ttbr1(pgd_t *pgdp, pgd_t *idmap)
+{
+	cpu_replace_ttbr1_phys(virt_to_phys(pgdp), idmap);
+}
+
 /*
  * It would be nice to return ASIDs back to the allocator, but unfortunately
  * that introduces a race with a generation rollover where we could erroneously
-- 
2.30.2


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  reply	other threads:[~2023-07-27 15:30 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-27 15:29 [PATCH v2 00/17] arm64 kernel text replication Russell King (Oracle)
2023-07-27 15:29 ` Russell King (Oracle)
2023-07-27 15:30 ` Russell King (Oracle) [this message]
2023-07-27 15:30   ` [PATCH v2 01/16] arm64: provide cpu_replace_ttbr1_phys() Russell King (Oracle)
2023-07-27 15:30 ` [PATCH v2 02/16] arm64: make clean_dcache_range_nopatch() visible Russell King (Oracle)
2023-07-27 15:30   ` Russell King (Oracle)
2023-07-27 15:30 ` [PATCH v2 03/16] arm64: place kernel in its own L0 page table entry Russell King (Oracle)
2023-07-27 15:30   ` Russell King (Oracle)
2023-07-27 15:30 ` [PATCH v2 04/16] arm64: text replication: add init function Russell King (Oracle)
2023-07-27 15:30   ` Russell King (Oracle)
2023-07-27 15:30 ` [PATCH v2 05/16] arm64: text replication: add sanity checks Russell King (Oracle)
2023-07-27 15:30   ` Russell King (Oracle)
2023-07-27 15:30 ` [PATCH v2 06/16] arm64: text replication: copy initial kernel text Russell King (Oracle)
2023-07-27 15:30   ` Russell King (Oracle)
2023-07-27 15:30 ` [PATCH v2 07/16] arm64: text replication: add node text patching Russell King (Oracle)
2023-07-27 15:30   ` Russell King (Oracle)
2023-07-27 15:30 ` [PATCH v2 08/16] arm64: text replication: add node 0 page table definitions Russell King (Oracle)
2023-07-27 15:30   ` Russell King (Oracle)
2023-07-27 15:30 ` [PATCH v2 09/16] arm64: text replication: add swapper page directory helpers Russell King (Oracle)
2023-07-27 15:30   ` Russell King (Oracle)
2023-07-27 15:30 ` [PATCH v2 10/16] arm64: text replication: create per-node kernel page tables Russell King (Oracle)
2023-07-27 15:30   ` Russell King (Oracle)
2023-07-27 15:30 ` [PATCH v2 11/16] arm64: text replication: boot secondary CPUs with appropriate TTBR1 Russell King (Oracle)
2023-07-27 15:30   ` Russell King (Oracle)
2023-07-27 15:30 ` [PATCH v2 12/16] arm64: text replication: update cnp support Russell King (Oracle)
2023-07-27 15:30   ` Russell King (Oracle)
2023-07-27 15:31 ` [PATCH v2 13/16] arm64: text replication: setup page tables for copied kernel Russell King (Oracle)
2023-07-27 15:31   ` Russell King (Oracle)
2023-07-27 15:31 ` [PATCH v2 14/16] arm64: text replication: include most of read-only data as well Russell King (Oracle)
2023-07-27 15:31   ` Russell King (Oracle)
2023-07-27 15:31 ` [PATCH v2 15/16] arm64: text replication: early kernel option to enable replication Russell King (Oracle)
2023-07-27 15:31   ` Russell King (Oracle)
2023-07-27 15:31 ` [PATCH v2 16/16] arm64: text replication: add Kconfig Russell King (Oracle)
2023-07-27 15:31   ` Russell King (Oracle)
2023-07-27 15:36   ` Randy Dunlap
2023-07-27 15:36     ` Randy Dunlap

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