From: Conor Dooley <conor@kernel.org>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH -next v14 10/19] riscv: Allocate user's vector context in the first-use trap
Date: Wed, 1 Mar 2023 16:53:58 +0000 [thread overview]
Message-ID: <Y/+DJmmZSFIgmEem@spud> (raw)
In-Reply-To: <20230224170118.16766-11-andy.chiu@sifive.com>
Hey Andy,
On Fri, Feb 24, 2023 at 05:01:09PM +0000, Andy Chiu wrote:
> Vector unit is disabled by default for all user processes. Thus, a
> process will take a trap (illegal instruction) into kernel at the first
> time when it uses Vector. Only after then, the kernel allocates V
> context and starts take care of the context for that user process.
>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Link: https://lore.kernel.org/r/3923eeee-e4dc-0911-40bf-84c34aee962d at linaro.org
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> ---
> diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
> index 082baf2a061f..585e2c51b28e 100644
> --- a/arch/riscv/kernel/vector.c
> +++ b/arch/riscv/kernel/vector.c
> @@ -4,9 +4,19 @@
> * Author: Andy Chiu <andy.chiu@sifive.com>
> */
> #include <linux/export.h>
> +#include <linux/sched/signal.h>
> +#include <linux/types.h>
> +#include <linux/slab.h>
> +#include <linux/sched.h>
> +#include <linux/uaccess.h>
>
> +#include <asm/thread_info.h>
> +#include <asm/processor.h>
> +#include <asm/insn.h>
> #include <asm/vector.h>
> #include <asm/csr.h>
> +#include <asm/ptrace.h>
> +#include <asm/bug.h>
>
> unsigned long riscv_v_vsize __read_mostly;
> EXPORT_SYMBOL_GPL(riscv_v_vsize);
> @@ -19,3 +29,84 @@ void riscv_v_setup_vsize(void)
> riscv_v_disable();
> }
>
> +static bool insn_is_vector(u32 insn_buf)
> +{
> + u32 opcode = insn_buf & __INSN_OPCODE_MASK;
> + bool is_vector = false;
> +
> + /*
> + * All V-related instructions, including CSR operations are 4-Byte. So,
> + * do not handle if the instruction length is not 4-Byte.
> + */
> + if (unlikely(GET_INSN_LENGTH(insn_buf) != 4))
> + return false;
> +
> + switch (opcode) {
> + case RVV_OPCODE_VECTOR:
> + is_vector = true;
> + break;
> + case RVV_OPCODE_VL:
> + case RVV_OPCODE_VS:
> + u32 width = RVV_EXRACT_VL_VS_WIDTH(insn_buf);
> +
> + if (width == RVV_VL_VS_WIDTH_8 || width == RVV_VL_VS_WIDTH_16 ||
> + width == RVV_VL_VS_WIDTH_32 || width == RVV_VL_VS_WIDTH_64)
> + is_vector = true;
> + break;
> + case RVG_OPCODE_SYSTEM:
> + u32 csr = RVG_EXTRACT_SYSTEM_CSR(insn_buf);
> +
> + if ((csr >= CSR_VSTART && csr <= CSR_VCSR) ||
> + (csr >= CSR_VL && csr <= CSR_VLENB))
> + is_vector = true;
> + break;
> + }
Unfortunately, this is not valid code:
/stuff/linux/arch/riscv/kernel/vector.c:50:3: error: expected expression
u32 width = RVV_EXRACT_VL_VS_WIDTH(insn_buf);
^
/stuff/linux/arch/riscv/kernel/vector.c:52:7: error: use of undeclared identifier 'width'
if (width == RVV_VL_VS_WIDTH_8 || width == RVV_VL_VS_WIDTH_16 ||
^
/stuff/linux/arch/riscv/kernel/vector.c:52:37: error: use of undeclared identifier 'width'
if (width == RVV_VL_VS_WIDTH_8 || width == RVV_VL_VS_WIDTH_16 ||
^
/stuff/linux/arch/riscv/kernel/vector.c:53:7: error: use of undeclared identifier 'width'
width == RVV_VL_VS_WIDTH_32 || width == RVV_VL_VS_WIDTH_64)
^
/stuff/linux/arch/riscv/kernel/vector.c:53:38: error: use of undeclared identifier 'width'
width == RVV_VL_VS_WIDTH_32 || width == RVV_VL_VS_WIDTH_64)
^
/stuff/linux/arch/riscv/kernel/vector.c:57:3: error: expected expression
u32 csr = RVG_EXTRACT_SYSTEM_CSR(insn_buf);
^
/stuff/linux/arch/riscv/kernel/vector.c:59:8: error: use of undeclared identifier 'csr'
if ((csr >= CSR_VSTART && csr <= CSR_VCSR) ||
^
/stuff/linux/arch/riscv/kernel/vector.c:59:29: error: use of undeclared identifier 'csr'
if ((csr >= CSR_VSTART && csr <= CSR_VCSR) ||
^
/stuff/linux/arch/riscv/kernel/vector.c:60:8: error: use of undeclared identifier 'csr'
(csr >= CSR_VL && csr <= CSR_VLENB))
^
/stuff/linux/arch/riscv/kernel/vector.c:60:25: error: use of undeclared identifier 'csr'
(csr >= CSR_VL && csr <= CSR_VLENB))
^
10 errors generated.
make[5]: *** [/stuff/linux/scripts/Makefile.build:252: arch/riscv/kernel/vector.o] Error 1
:/
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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Andy Chiu <andy.chiu@sifive.com>
Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
anup@brainfault.org, atishp@atishpatra.org,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
vineetg@rivosinc.com, greentime.hu@sifive.com,
guoren@linux.alibaba.com,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Heiko Stuebner" <heiko.stuebner@vrull.eu>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Lad Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
"Liao Chang" <liaochang1@huawei.com>,
"Jisheng Zhang" <jszhang@kernel.org>,
"Guo Ren" <guoren@kernel.org>,
"Vincent Chen" <vincent.chen@sifive.com>,
"Björn Töpel" <bjorn@rivosinc.com>,
"Xianting Tian" <xianting.tian@linux.alibaba.com>,
"Mattias Nissler" <mnissler@rivosinc.com>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: Re: [PATCH -next v14 10/19] riscv: Allocate user's vector context in the first-use trap
Date: Wed, 1 Mar 2023 16:53:58 +0000 [thread overview]
Message-ID: <Y/+DJmmZSFIgmEem@spud> (raw)
In-Reply-To: <20230224170118.16766-11-andy.chiu@sifive.com>
[-- Attachment #1.1: Type: text/plain, Size: 4418 bytes --]
Hey Andy,
On Fri, Feb 24, 2023 at 05:01:09PM +0000, Andy Chiu wrote:
> Vector unit is disabled by default for all user processes. Thus, a
> process will take a trap (illegal instruction) into kernel at the first
> time when it uses Vector. Only after then, the kernel allocates V
> context and starts take care of the context for that user process.
>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Link: https://lore.kernel.org/r/3923eeee-e4dc-0911-40bf-84c34aee962d@linaro.org
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> ---
> diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
> index 082baf2a061f..585e2c51b28e 100644
> --- a/arch/riscv/kernel/vector.c
> +++ b/arch/riscv/kernel/vector.c
> @@ -4,9 +4,19 @@
> * Author: Andy Chiu <andy.chiu@sifive.com>
> */
> #include <linux/export.h>
> +#include <linux/sched/signal.h>
> +#include <linux/types.h>
> +#include <linux/slab.h>
> +#include <linux/sched.h>
> +#include <linux/uaccess.h>
>
> +#include <asm/thread_info.h>
> +#include <asm/processor.h>
> +#include <asm/insn.h>
> #include <asm/vector.h>
> #include <asm/csr.h>
> +#include <asm/ptrace.h>
> +#include <asm/bug.h>
>
> unsigned long riscv_v_vsize __read_mostly;
> EXPORT_SYMBOL_GPL(riscv_v_vsize);
> @@ -19,3 +29,84 @@ void riscv_v_setup_vsize(void)
> riscv_v_disable();
> }
>
> +static bool insn_is_vector(u32 insn_buf)
> +{
> + u32 opcode = insn_buf & __INSN_OPCODE_MASK;
> + bool is_vector = false;
> +
> + /*
> + * All V-related instructions, including CSR operations are 4-Byte. So,
> + * do not handle if the instruction length is not 4-Byte.
> + */
> + if (unlikely(GET_INSN_LENGTH(insn_buf) != 4))
> + return false;
> +
> + switch (opcode) {
> + case RVV_OPCODE_VECTOR:
> + is_vector = true;
> + break;
> + case RVV_OPCODE_VL:
> + case RVV_OPCODE_VS:
> + u32 width = RVV_EXRACT_VL_VS_WIDTH(insn_buf);
> +
> + if (width == RVV_VL_VS_WIDTH_8 || width == RVV_VL_VS_WIDTH_16 ||
> + width == RVV_VL_VS_WIDTH_32 || width == RVV_VL_VS_WIDTH_64)
> + is_vector = true;
> + break;
> + case RVG_OPCODE_SYSTEM:
> + u32 csr = RVG_EXTRACT_SYSTEM_CSR(insn_buf);
> +
> + if ((csr >= CSR_VSTART && csr <= CSR_VCSR) ||
> + (csr >= CSR_VL && csr <= CSR_VLENB))
> + is_vector = true;
> + break;
> + }
Unfortunately, this is not valid code:
/stuff/linux/arch/riscv/kernel/vector.c:50:3: error: expected expression
u32 width = RVV_EXRACT_VL_VS_WIDTH(insn_buf);
^
/stuff/linux/arch/riscv/kernel/vector.c:52:7: error: use of undeclared identifier 'width'
if (width == RVV_VL_VS_WIDTH_8 || width == RVV_VL_VS_WIDTH_16 ||
^
/stuff/linux/arch/riscv/kernel/vector.c:52:37: error: use of undeclared identifier 'width'
if (width == RVV_VL_VS_WIDTH_8 || width == RVV_VL_VS_WIDTH_16 ||
^
/stuff/linux/arch/riscv/kernel/vector.c:53:7: error: use of undeclared identifier 'width'
width == RVV_VL_VS_WIDTH_32 || width == RVV_VL_VS_WIDTH_64)
^
/stuff/linux/arch/riscv/kernel/vector.c:53:38: error: use of undeclared identifier 'width'
width == RVV_VL_VS_WIDTH_32 || width == RVV_VL_VS_WIDTH_64)
^
/stuff/linux/arch/riscv/kernel/vector.c:57:3: error: expected expression
u32 csr = RVG_EXTRACT_SYSTEM_CSR(insn_buf);
^
/stuff/linux/arch/riscv/kernel/vector.c:59:8: error: use of undeclared identifier 'csr'
if ((csr >= CSR_VSTART && csr <= CSR_VCSR) ||
^
/stuff/linux/arch/riscv/kernel/vector.c:59:29: error: use of undeclared identifier 'csr'
if ((csr >= CSR_VSTART && csr <= CSR_VCSR) ||
^
/stuff/linux/arch/riscv/kernel/vector.c:60:8: error: use of undeclared identifier 'csr'
(csr >= CSR_VL && csr <= CSR_VLENB))
^
/stuff/linux/arch/riscv/kernel/vector.c:60:25: error: use of undeclared identifier 'csr'
(csr >= CSR_VL && csr <= CSR_VLENB))
^
10 errors generated.
make[5]: *** [/stuff/linux/scripts/Makefile.build:252: arch/riscv/kernel/vector.o] Error 1
:/
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_______________________________________________
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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Andy Chiu <andy.chiu@sifive.com>
Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
anup@brainfault.org, atishp@atishpatra.org,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
vineetg@rivosinc.com, greentime.hu@sifive.com,
guoren@linux.alibaba.com,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Heiko Stuebner" <heiko.stuebner@vrull.eu>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Lad Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
"Liao Chang" <liaochang1@huawei.com>,
"Jisheng Zhang" <jszhang@kernel.org>,
"Guo Ren" <guoren@kernel.org>,
"Vincent Chen" <vincent.chen@sifive.com>,
"Björn Töpel" <bjorn@rivosinc.com>,
"Xianting Tian" <xianting.tian@linux.alibaba.com>,
"Mattias Nissler" <mnissler@rivosinc.com>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: Re: [PATCH -next v14 10/19] riscv: Allocate user's vector context in the first-use trap
Date: Wed, 1 Mar 2023 16:53:58 +0000 [thread overview]
Message-ID: <Y/+DJmmZSFIgmEem@spud> (raw)
In-Reply-To: <20230224170118.16766-11-andy.chiu@sifive.com>
[-- Attachment #1: Type: text/plain, Size: 4418 bytes --]
Hey Andy,
On Fri, Feb 24, 2023 at 05:01:09PM +0000, Andy Chiu wrote:
> Vector unit is disabled by default for all user processes. Thus, a
> process will take a trap (illegal instruction) into kernel at the first
> time when it uses Vector. Only after then, the kernel allocates V
> context and starts take care of the context for that user process.
>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Link: https://lore.kernel.org/r/3923eeee-e4dc-0911-40bf-84c34aee962d@linaro.org
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> ---
> diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
> index 082baf2a061f..585e2c51b28e 100644
> --- a/arch/riscv/kernel/vector.c
> +++ b/arch/riscv/kernel/vector.c
> @@ -4,9 +4,19 @@
> * Author: Andy Chiu <andy.chiu@sifive.com>
> */
> #include <linux/export.h>
> +#include <linux/sched/signal.h>
> +#include <linux/types.h>
> +#include <linux/slab.h>
> +#include <linux/sched.h>
> +#include <linux/uaccess.h>
>
> +#include <asm/thread_info.h>
> +#include <asm/processor.h>
> +#include <asm/insn.h>
> #include <asm/vector.h>
> #include <asm/csr.h>
> +#include <asm/ptrace.h>
> +#include <asm/bug.h>
>
> unsigned long riscv_v_vsize __read_mostly;
> EXPORT_SYMBOL_GPL(riscv_v_vsize);
> @@ -19,3 +29,84 @@ void riscv_v_setup_vsize(void)
> riscv_v_disable();
> }
>
> +static bool insn_is_vector(u32 insn_buf)
> +{
> + u32 opcode = insn_buf & __INSN_OPCODE_MASK;
> + bool is_vector = false;
> +
> + /*
> + * All V-related instructions, including CSR operations are 4-Byte. So,
> + * do not handle if the instruction length is not 4-Byte.
> + */
> + if (unlikely(GET_INSN_LENGTH(insn_buf) != 4))
> + return false;
> +
> + switch (opcode) {
> + case RVV_OPCODE_VECTOR:
> + is_vector = true;
> + break;
> + case RVV_OPCODE_VL:
> + case RVV_OPCODE_VS:
> + u32 width = RVV_EXRACT_VL_VS_WIDTH(insn_buf);
> +
> + if (width == RVV_VL_VS_WIDTH_8 || width == RVV_VL_VS_WIDTH_16 ||
> + width == RVV_VL_VS_WIDTH_32 || width == RVV_VL_VS_WIDTH_64)
> + is_vector = true;
> + break;
> + case RVG_OPCODE_SYSTEM:
> + u32 csr = RVG_EXTRACT_SYSTEM_CSR(insn_buf);
> +
> + if ((csr >= CSR_VSTART && csr <= CSR_VCSR) ||
> + (csr >= CSR_VL && csr <= CSR_VLENB))
> + is_vector = true;
> + break;
> + }
Unfortunately, this is not valid code:
/stuff/linux/arch/riscv/kernel/vector.c:50:3: error: expected expression
u32 width = RVV_EXRACT_VL_VS_WIDTH(insn_buf);
^
/stuff/linux/arch/riscv/kernel/vector.c:52:7: error: use of undeclared identifier 'width'
if (width == RVV_VL_VS_WIDTH_8 || width == RVV_VL_VS_WIDTH_16 ||
^
/stuff/linux/arch/riscv/kernel/vector.c:52:37: error: use of undeclared identifier 'width'
if (width == RVV_VL_VS_WIDTH_8 || width == RVV_VL_VS_WIDTH_16 ||
^
/stuff/linux/arch/riscv/kernel/vector.c:53:7: error: use of undeclared identifier 'width'
width == RVV_VL_VS_WIDTH_32 || width == RVV_VL_VS_WIDTH_64)
^
/stuff/linux/arch/riscv/kernel/vector.c:53:38: error: use of undeclared identifier 'width'
width == RVV_VL_VS_WIDTH_32 || width == RVV_VL_VS_WIDTH_64)
^
/stuff/linux/arch/riscv/kernel/vector.c:57:3: error: expected expression
u32 csr = RVG_EXTRACT_SYSTEM_CSR(insn_buf);
^
/stuff/linux/arch/riscv/kernel/vector.c:59:8: error: use of undeclared identifier 'csr'
if ((csr >= CSR_VSTART && csr <= CSR_VCSR) ||
^
/stuff/linux/arch/riscv/kernel/vector.c:59:29: error: use of undeclared identifier 'csr'
if ((csr >= CSR_VSTART && csr <= CSR_VCSR) ||
^
/stuff/linux/arch/riscv/kernel/vector.c:60:8: error: use of undeclared identifier 'csr'
(csr >= CSR_VL && csr <= CSR_VLENB))
^
/stuff/linux/arch/riscv/kernel/vector.c:60:25: error: use of undeclared identifier 'csr'
(csr >= CSR_VL && csr <= CSR_VLENB))
^
10 errors generated.
make[5]: *** [/stuff/linux/scripts/Makefile.build:252: arch/riscv/kernel/vector.o] Error 1
:/
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
next prev parent reply other threads:[~2023-03-01 16:53 UTC|newest]
Thread overview: 162+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-24 17:00 [PATCH -next v14 00/19] riscv: Add vector ISA support Andy Chiu
2023-02-24 17:00 ` Andy Chiu
2023-02-24 17:00 ` Andy Chiu
2023-02-24 17:01 ` [PATCH -next v14 01/19] riscv: Rename __switch_to_aux -> fpu Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-28 21:56 ` Conor Dooley
2023-02-28 21:56 ` Conor Dooley
2023-02-28 21:56 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-28 22:07 ` Conor Dooley
2023-02-28 22:07 ` Conor Dooley
2023-02-28 22:07 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 03/19] riscv: Add new csr defines related to vector extension Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-28 22:31 ` Conor Dooley
2023-02-28 22:31 ` Conor Dooley
2023-02-28 22:31 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 04/19] riscv: Clear vector regfile on bootup Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-28 22:17 ` Conor Dooley
2023-02-28 22:17 ` Conor Dooley
2023-02-28 22:17 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 05/19] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` [PATCH -next v14 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-28 22:36 ` Conor Dooley
2023-02-28 22:36 ` Conor Dooley
2023-02-28 22:36 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 07/19] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-28 22:38 ` Conor Dooley
2023-02-28 22:39 ` Conor Dooley
2023-02-28 22:38 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-28 23:00 ` Conor Dooley
2023-02-28 23:00 ` Conor Dooley
2023-02-28 23:00 ` Conor Dooley
2023-03-15 4:00 ` Andy Chiu
2023-03-15 4:00 ` Andy Chiu
2023-03-15 4:00 ` Andy Chiu
2023-03-02 11:12 ` Björn Töpel
2023-03-02 11:12 ` Björn Töpel
2023-03-02 11:12 ` Björn Töpel
2023-03-15 4:05 ` Andy Chiu
2023-03-15 4:05 ` Andy Chiu
2023-03-15 4:05 ` Andy Chiu
2023-02-24 17:01 ` [PATCH -next v14 09/19] riscv: Add task switch support for vector Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-03-01 16:41 ` Conor Dooley
2023-03-01 16:41 ` Conor Dooley
2023-03-01 16:41 ` Conor Dooley
2023-03-01 16:57 ` Björn Töpel
2023-03-01 16:57 ` Björn Töpel
2023-03-01 16:57 ` Björn Töpel
2023-03-02 11:07 ` Björn Töpel
2023-03-02 11:07 ` Björn Töpel
2023-03-02 11:07 ` Björn Töpel
2023-02-24 17:01 ` [PATCH -next v14 10/19] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-03-01 16:53 ` Conor Dooley [this message]
2023-03-01 16:53 ` Conor Dooley
2023-03-01 16:53 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 11/19] riscv: Add ptrace vector support Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-03-01 17:29 ` Conor Dooley
2023-03-01 17:29 ` Conor Dooley
2023-03-01 17:29 ` Conor Dooley
2023-03-02 11:27 ` Björn Töpel
2023-03-02 11:27 ` Björn Töpel
2023-03-02 11:27 ` Björn Töpel
2023-03-14 10:39 ` Andy Chiu
2023-03-14 10:39 ` Andy Chiu
2023-03-14 10:39 ` Andy Chiu
2023-03-14 10:44 ` Conor Dooley
2023-03-14 10:44 ` Conor Dooley
2023-03-14 10:44 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-03-01 17:56 ` Conor Dooley
2023-03-01 17:56 ` Conor Dooley
2023-03-01 17:56 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-03-01 18:27 ` Conor Dooley
2023-03-01 18:27 ` Conor Dooley
2023-03-01 18:27 ` Conor Dooley
2023-03-02 12:42 ` Björn Töpel
2023-03-02 12:42 ` Björn Töpel
2023-03-02 12:42 ` Björn Töpel
2023-02-24 17:01 ` [PATCH -next v14 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-03-01 19:21 ` Conor Dooley
2023-03-01 19:21 ` Conor Dooley
2023-03-01 19:21 ` Conor Dooley
2023-03-02 12:47 ` Björn Töpel
2023-03-02 12:47 ` Björn Töpel
2023-03-02 12:47 ` Björn Töpel
2023-02-24 17:01 ` [PATCH -next v14 15/19] riscv: signal: validate altstack to reflect Vector Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-03-01 21:00 ` Conor Dooley
2023-03-01 21:00 ` Conor Dooley
2023-03-01 21:00 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 16/19] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-03-01 21:34 ` Conor Dooley
2023-03-01 21:34 ` Conor Dooley
2023-03-01 21:34 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 17/19] riscv: kvm: Add V extension to KVM ISA Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-03-01 21:38 ` Conor Dooley
2023-03-01 21:38 ` Conor Dooley
2023-03-01 21:38 ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 18/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` [PATCH -next v14 19/19] riscv: Enable Vector code to be built Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 17:01 ` Andy Chiu
2023-02-24 21:35 ` kernel test robot
2023-02-24 21:35 ` kernel test robot
2023-02-24 21:35 ` kernel test robot
2023-02-25 1:33 ` kernel test robot
2023-02-25 1:34 ` kernel test robot
2023-02-25 1:33 ` kernel test robot
2023-03-01 18:00 ` Nathan Chancellor
2023-03-01 18:00 ` Nathan Chancellor
2023-03-01 18:00 ` Nathan Chancellor
2023-03-01 18:44 ` Conor Dooley
2023-03-01 18:44 ` Conor Dooley
2023-03-01 18:44 ` Conor Dooley
2023-02-25 8:28 ` kernel test robot
2023-02-25 8:28 ` kernel test robot
2023-02-25 8:28 ` kernel test robot
2023-02-27 10:18 ` Conor Dooley
2023-02-27 10:19 ` Conor Dooley
2023-02-27 10:18 ` Conor Dooley
2023-02-27 13:40 ` Darius Rad
2023-02-27 13:40 ` Darius Rad
2023-02-27 13:40 ` Darius Rad
2023-02-27 13:58 ` Conor Dooley
2023-02-27 13:59 ` Conor Dooley
2023-02-27 13:58 ` Conor Dooley
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