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From: Conor Dooley <conor@kernel.org>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH -next v14 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state
Date: Tue, 28 Feb 2023 23:00:50 -0000	[thread overview]
Message-ID: <Y/6HmORLbsFWsEbu@spud> (raw)
In-Reply-To: <20230224170118.16766-9-andy.chiu@sifive.com>

On Fri, Feb 24, 2023 at 05:01:07PM +0000, Andy Chiu wrote:
> From: Greentime Hu <greentime.hu@sifive.com>
> 
> Add vector state context struct to be added later in thread_struct. And
> prepare low-level helper functions to save/restore vector contexts.
> 
> This include Vector Regfile and CSRs holding dynamic configuration state
> (vstart, vl, vtype, vcsr). The Vec Register width could be implementation
> defined, but same for all processes, so that is saved separately.
> 
> This is not yet wired into final thread_struct - will be done when
> __switch_to actually starts doing this in later patches.
> 
> Given the variable (and potentially large) size of regfile, they are
> saved in dynamically allocated memory, pointed to by datap pointer in
> __riscv_v_ext_state.
> 
> Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
> [vineetg: merged bits from 2 different patches]
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> [andy.chiu: use inline asm to save/restore context, remove asm vaiant]
> ---
>  arch/riscv/include/asm/vector.h      | 84 ++++++++++++++++++++++++++++
>  arch/riscv/include/uapi/asm/ptrace.h | 17 ++++++
>  2 files changed, 101 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> index 692d3ee2d2d3..9c025f2efdc3 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -12,6 +12,9 @@
>  
>  #include <asm/hwcap.h>
>  #include <asm/csr.h>
> +#include <asm/asm.h>
> +
> +#define CSR_STR(x) __ASM_STR(x)

TBH, I'm not really sure what this definition adds.

>  extern unsigned long riscv_v_vsize;
>  void riscv_v_setup_vsize(void);
> @@ -21,6 +24,26 @@ static __always_inline bool has_vector(void)
>  	return riscv_has_extension_likely(RISCV_ISA_EXT_v);
>  }
>  
> +static inline void __riscv_v_vstate_clean(struct pt_regs *regs)
> +{
> +	regs->status = (regs->status & ~(SR_VS)) | SR_VS_CLEAN;
> +}
> +
> +static inline void riscv_v_vstate_off(struct pt_regs *regs)
> +{
> +	regs->status = (regs->status & ~SR_VS) | SR_VS_OFF;

Inconsistent use of brackets here compared to the other items.
They're not actually needed anywhere here, are they?

> +}
> +
> +static inline void riscv_v_vstate_on(struct pt_regs *regs)
> +{
> +	regs->status = (regs->status & ~(SR_VS)) | SR_VS_INITIAL;
> +}

Other than that, this seems fine? I only really had a quick check of the
asm though, so with the brackets thing fixed up:
Acked-by: Conor Dooley <conor.dooley@microchip.com>
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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Andy Chiu <andy.chiu@sifive.com>
Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
	anup@brainfault.org, atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
	vineetg@rivosinc.com, greentime.hu@sifive.com,
	guoren@linux.alibaba.com, Vincent Chen <vincent.chen@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>,
	Richard Henderson <richard.henderson@linaro.org>
Subject: Re: [PATCH -next v14 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state
Date: Tue, 28 Feb 2023 23:00:40 +0000	[thread overview]
Message-ID: <Y/6HmORLbsFWsEbu@spud> (raw)
In-Reply-To: <20230224170118.16766-9-andy.chiu@sifive.com>


[-- Attachment #1.1: Type: text/plain, Size: 2718 bytes --]

On Fri, Feb 24, 2023 at 05:01:07PM +0000, Andy Chiu wrote:
> From: Greentime Hu <greentime.hu@sifive.com>
> 
> Add vector state context struct to be added later in thread_struct. And
> prepare low-level helper functions to save/restore vector contexts.
> 
> This include Vector Regfile and CSRs holding dynamic configuration state
> (vstart, vl, vtype, vcsr). The Vec Register width could be implementation
> defined, but same for all processes, so that is saved separately.
> 
> This is not yet wired into final thread_struct - will be done when
> __switch_to actually starts doing this in later patches.
> 
> Given the variable (and potentially large) size of regfile, they are
> saved in dynamically allocated memory, pointed to by datap pointer in
> __riscv_v_ext_state.
> 
> Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
> [vineetg: merged bits from 2 different patches]
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> [andy.chiu: use inline asm to save/restore context, remove asm vaiant]
> ---
>  arch/riscv/include/asm/vector.h      | 84 ++++++++++++++++++++++++++++
>  arch/riscv/include/uapi/asm/ptrace.h | 17 ++++++
>  2 files changed, 101 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> index 692d3ee2d2d3..9c025f2efdc3 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -12,6 +12,9 @@
>  
>  #include <asm/hwcap.h>
>  #include <asm/csr.h>
> +#include <asm/asm.h>
> +
> +#define CSR_STR(x) __ASM_STR(x)

TBH, I'm not really sure what this definition adds.

>  extern unsigned long riscv_v_vsize;
>  void riscv_v_setup_vsize(void);
> @@ -21,6 +24,26 @@ static __always_inline bool has_vector(void)
>  	return riscv_has_extension_likely(RISCV_ISA_EXT_v);
>  }
>  
> +static inline void __riscv_v_vstate_clean(struct pt_regs *regs)
> +{
> +	regs->status = (regs->status & ~(SR_VS)) | SR_VS_CLEAN;
> +}
> +
> +static inline void riscv_v_vstate_off(struct pt_regs *regs)
> +{
> +	regs->status = (regs->status & ~SR_VS) | SR_VS_OFF;

Inconsistent use of brackets here compared to the other items.
They're not actually needed anywhere here, are they?

> +}
> +
> +static inline void riscv_v_vstate_on(struct pt_regs *regs)
> +{
> +	regs->status = (regs->status & ~(SR_VS)) | SR_VS_INITIAL;
> +}

Other than that, this seems fine? I only really had a quick check of the
asm though, so with the brackets thing fixed up:
Acked-by: Conor Dooley <conor.dooley@microchip.com>

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_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Andy Chiu <andy.chiu@sifive.com>
Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
	anup@brainfault.org, atishp@atishpatra.org,
	kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
	vineetg@rivosinc.com, greentime.hu@sifive.com,
	guoren@linux.alibaba.com, Vincent Chen <vincent.chen@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>,
	Richard Henderson <richard.henderson@linaro.org>
Subject: Re: [PATCH -next v14 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state
Date: Tue, 28 Feb 2023 23:00:40 +0000	[thread overview]
Message-ID: <Y/6HmORLbsFWsEbu@spud> (raw)
In-Reply-To: <20230224170118.16766-9-andy.chiu@sifive.com>

[-- Attachment #1: Type: text/plain, Size: 2718 bytes --]

On Fri, Feb 24, 2023 at 05:01:07PM +0000, Andy Chiu wrote:
> From: Greentime Hu <greentime.hu@sifive.com>
> 
> Add vector state context struct to be added later in thread_struct. And
> prepare low-level helper functions to save/restore vector contexts.
> 
> This include Vector Regfile and CSRs holding dynamic configuration state
> (vstart, vl, vtype, vcsr). The Vec Register width could be implementation
> defined, but same for all processes, so that is saved separately.
> 
> This is not yet wired into final thread_struct - will be done when
> __switch_to actually starts doing this in later patches.
> 
> Given the variable (and potentially large) size of regfile, they are
> saved in dynamically allocated memory, pointed to by datap pointer in
> __riscv_v_ext_state.
> 
> Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
> [vineetg: merged bits from 2 different patches]
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> [andy.chiu: use inline asm to save/restore context, remove asm vaiant]
> ---
>  arch/riscv/include/asm/vector.h      | 84 ++++++++++++++++++++++++++++
>  arch/riscv/include/uapi/asm/ptrace.h | 17 ++++++
>  2 files changed, 101 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
> index 692d3ee2d2d3..9c025f2efdc3 100644
> --- a/arch/riscv/include/asm/vector.h
> +++ b/arch/riscv/include/asm/vector.h
> @@ -12,6 +12,9 @@
>  
>  #include <asm/hwcap.h>
>  #include <asm/csr.h>
> +#include <asm/asm.h>
> +
> +#define CSR_STR(x) __ASM_STR(x)

TBH, I'm not really sure what this definition adds.

>  extern unsigned long riscv_v_vsize;
>  void riscv_v_setup_vsize(void);
> @@ -21,6 +24,26 @@ static __always_inline bool has_vector(void)
>  	return riscv_has_extension_likely(RISCV_ISA_EXT_v);
>  }
>  
> +static inline void __riscv_v_vstate_clean(struct pt_regs *regs)
> +{
> +	regs->status = (regs->status & ~(SR_VS)) | SR_VS_CLEAN;
> +}
> +
> +static inline void riscv_v_vstate_off(struct pt_regs *regs)
> +{
> +	regs->status = (regs->status & ~SR_VS) | SR_VS_OFF;

Inconsistent use of brackets here compared to the other items.
They're not actually needed anywhere here, are they?

> +}
> +
> +static inline void riscv_v_vstate_on(struct pt_regs *regs)
> +{
> +	regs->status = (regs->status & ~(SR_VS)) | SR_VS_INITIAL;
> +}

Other than that, this seems fine? I only really had a quick check of the
asm though, so with the brackets thing fixed up:
Acked-by: Conor Dooley <conor.dooley@microchip.com>

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  reply	other threads:[~2023-02-28 23:00 UTC|newest]

Thread overview: 162+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-24 17:00 [PATCH -next v14 00/19] riscv: Add vector ISA support Andy Chiu
2023-02-24 17:00 ` Andy Chiu
2023-02-24 17:00 ` Andy Chiu
2023-02-24 17:01 ` [PATCH -next v14 01/19] riscv: Rename __switch_to_aux -> fpu Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-28 21:56   ` Conor Dooley
2023-02-28 21:56     ` Conor Dooley
2023-02-28 21:56     ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-28 22:07   ` Conor Dooley
2023-02-28 22:07     ` Conor Dooley
2023-02-28 22:07     ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 03/19] riscv: Add new csr defines related to vector extension Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-28 22:31   ` Conor Dooley
2023-02-28 22:31     ` Conor Dooley
2023-02-28 22:31     ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 04/19] riscv: Clear vector regfile on bootup Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-28 22:17   ` Conor Dooley
2023-02-28 22:17     ` Conor Dooley
2023-02-28 22:17     ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 05/19] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01 ` [PATCH -next v14 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-28 22:36   ` Conor Dooley
2023-02-28 22:36     ` Conor Dooley
2023-02-28 22:36     ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 07/19] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-28 22:38   ` Conor Dooley
2023-02-28 22:39     ` Conor Dooley
2023-02-28 22:38     ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-28 23:00   ` Conor Dooley [this message]
2023-02-28 23:00     ` Conor Dooley
2023-02-28 23:00     ` Conor Dooley
2023-03-15  4:00     ` Andy Chiu
2023-03-15  4:00       ` Andy Chiu
2023-03-15  4:00       ` Andy Chiu
2023-03-02 11:12   ` Björn Töpel
2023-03-02 11:12     ` Björn Töpel
2023-03-02 11:12     ` Björn Töpel
2023-03-15  4:05     ` Andy Chiu
2023-03-15  4:05       ` Andy Chiu
2023-03-15  4:05       ` Andy Chiu
2023-02-24 17:01 ` [PATCH -next v14 09/19] riscv: Add task switch support for vector Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-03-01 16:41   ` Conor Dooley
2023-03-01 16:41     ` Conor Dooley
2023-03-01 16:41     ` Conor Dooley
2023-03-01 16:57     ` Björn Töpel
2023-03-01 16:57       ` Björn Töpel
2023-03-01 16:57       ` Björn Töpel
2023-03-02 11:07   ` Björn Töpel
2023-03-02 11:07     ` Björn Töpel
2023-03-02 11:07     ` Björn Töpel
2023-02-24 17:01 ` [PATCH -next v14 10/19] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-03-01 16:53   ` Conor Dooley
2023-03-01 16:53     ` Conor Dooley
2023-03-01 16:53     ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 11/19] riscv: Add ptrace vector support Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-03-01 17:29   ` Conor Dooley
2023-03-01 17:29     ` Conor Dooley
2023-03-01 17:29     ` Conor Dooley
2023-03-02 11:27   ` Björn Töpel
2023-03-02 11:27     ` Björn Töpel
2023-03-02 11:27     ` Björn Töpel
2023-03-14 10:39     ` Andy Chiu
2023-03-14 10:39       ` Andy Chiu
2023-03-14 10:39       ` Andy Chiu
2023-03-14 10:44       ` Conor Dooley
2023-03-14 10:44         ` Conor Dooley
2023-03-14 10:44         ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-03-01 17:56   ` Conor Dooley
2023-03-01 17:56     ` Conor Dooley
2023-03-01 17:56     ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-03-01 18:27   ` Conor Dooley
2023-03-01 18:27     ` Conor Dooley
2023-03-01 18:27     ` Conor Dooley
2023-03-02 12:42   ` Björn Töpel
2023-03-02 12:42     ` Björn Töpel
2023-03-02 12:42     ` Björn Töpel
2023-02-24 17:01 ` [PATCH -next v14 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-03-01 19:21   ` Conor Dooley
2023-03-01 19:21     ` Conor Dooley
2023-03-01 19:21     ` Conor Dooley
2023-03-02 12:47   ` Björn Töpel
2023-03-02 12:47     ` Björn Töpel
2023-03-02 12:47     ` Björn Töpel
2023-02-24 17:01 ` [PATCH -next v14 15/19] riscv: signal: validate altstack to reflect Vector Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-03-01 21:00   ` Conor Dooley
2023-03-01 21:00     ` Conor Dooley
2023-03-01 21:00     ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 16/19] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-03-01 21:34   ` Conor Dooley
2023-03-01 21:34     ` Conor Dooley
2023-03-01 21:34     ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 17/19] riscv: kvm: Add V extension to KVM ISA Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-03-01 21:38   ` Conor Dooley
2023-03-01 21:38     ` Conor Dooley
2023-03-01 21:38     ` Conor Dooley
2023-02-24 17:01 ` [PATCH -next v14 18/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01 ` [PATCH -next v14 19/19] riscv: Enable Vector code to be built Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 17:01   ` Andy Chiu
2023-02-24 21:35   ` kernel test robot
2023-02-24 21:35     ` kernel test robot
2023-02-24 21:35     ` kernel test robot
2023-02-25  1:33   ` kernel test robot
2023-02-25  1:34     ` kernel test robot
2023-02-25  1:33     ` kernel test robot
2023-03-01 18:00     ` Nathan Chancellor
2023-03-01 18:00       ` Nathan Chancellor
2023-03-01 18:00       ` Nathan Chancellor
2023-03-01 18:44       ` Conor Dooley
2023-03-01 18:44         ` Conor Dooley
2023-03-01 18:44         ` Conor Dooley
2023-02-25  8:28   ` kernel test robot
2023-02-25  8:28     ` kernel test robot
2023-02-25  8:28     ` kernel test robot
2023-02-27 10:18   ` Conor Dooley
2023-02-27 10:19     ` Conor Dooley
2023-02-27 10:18     ` Conor Dooley
2023-02-27 13:40     ` Darius Rad
2023-02-27 13:40       ` Darius Rad
2023-02-27 13:40       ` Darius Rad
2023-02-27 13:58       ` Conor Dooley
2023-02-27 13:59         ` Conor Dooley
2023-02-27 13:58         ` Conor Dooley

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