* [Intel-gfx] [PATCH 0/4] i915: CAGF and RC6 changes for MTL
@ 2022-10-19 5:20 ` Ashutosh Dixit
0 siblings, 0 replies; 26+ messages in thread
From: Ashutosh Dixit @ 2022-10-19 5:20 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi
This series includes the code changes to get CAGF, RC State and C6
Residency of MTL.
v3: Included "Use GEN12 RPSTAT register" patch
v4:
- Rebased
- Dropped "Use GEN12 RPSTAT register" patch from this series
going to send separate series for it
v5:
- Included "drm/i915/gt: Change RC6 residency functions to accept register
ID's" based on code review feedback
v6:
- Addressed Jani N's review comments on "drm/i915/gt: Change RC6 residency
functions to accept register ID's"
- Minor changes to other patches, please see individual patches for changelogs
Ashutosh Dixit (1):
drm/i915/gt: Use RC6 residency types as arguments to residency
functions
Badal Nilawar (2):
drm/i915/mtl: Modify CAGF functions for MTL
drm/i915/mtl: C6 residency and C state type for MTL SAMedia
Don Hiatt (1):
drm/i915: Use GEN12_RPSTAT register for GT freq
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 87 ++++++++++++++-----
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 11 +++
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 +--
drivers/gpu/drm/i915/gt/intel_rc6.c | 64 +++++++++-----
drivers/gpu/drm/i915/gt/intel_rc6.h | 8 +-
drivers/gpu/drm/i915/gt/intel_rc6_types.h | 15 +++-
drivers/gpu/drm/i915/gt/intel_rps.c | 40 ++++++++-
drivers/gpu/drm/i915/gt/intel_rps.h | 2 +
drivers/gpu/drm/i915/gt/selftest_rc6.c | 6 +-
drivers/gpu/drm/i915/i915_pmu.c | 9 +-
10 files changed, 188 insertions(+), 66 deletions(-)
--
2.38.0
^ permalink raw reply [flat|nested] 26+ messages in thread* [PATCH 0/4] i915: CAGF and RC6 changes for MTL @ 2022-10-19 5:20 ` Ashutosh Dixit 0 siblings, 0 replies; 26+ messages in thread From: Ashutosh Dixit @ 2022-10-19 5:20 UTC (permalink / raw) To: intel-gfx; +Cc: Anshuman Gupta, Badal Nilawar, dri-devel, Rodrigo Vivi This series includes the code changes to get CAGF, RC State and C6 Residency of MTL. v3: Included "Use GEN12 RPSTAT register" patch v4: - Rebased - Dropped "Use GEN12 RPSTAT register" patch from this series going to send separate series for it v5: - Included "drm/i915/gt: Change RC6 residency functions to accept register ID's" based on code review feedback v6: - Addressed Jani N's review comments on "drm/i915/gt: Change RC6 residency functions to accept register ID's" - Minor changes to other patches, please see individual patches for changelogs Ashutosh Dixit (1): drm/i915/gt: Use RC6 residency types as arguments to residency functions Badal Nilawar (2): drm/i915/mtl: Modify CAGF functions for MTL drm/i915/mtl: C6 residency and C state type for MTL SAMedia Don Hiatt (1): drm/i915: Use GEN12_RPSTAT register for GT freq drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 87 ++++++++++++++----- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 11 +++ drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 +-- drivers/gpu/drm/i915/gt/intel_rc6.c | 64 +++++++++----- drivers/gpu/drm/i915/gt/intel_rc6.h | 8 +- drivers/gpu/drm/i915/gt/intel_rc6_types.h | 15 +++- drivers/gpu/drm/i915/gt/intel_rps.c | 40 ++++++++- drivers/gpu/drm/i915/gt/intel_rps.h | 2 + drivers/gpu/drm/i915/gt/selftest_rc6.c | 6 +- drivers/gpu/drm/i915/i915_pmu.c | 9 +- 10 files changed, 188 insertions(+), 66 deletions(-) -- 2.38.0 ^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 1/4] drm/i915: Use GEN12_RPSTAT register for GT freq 2022-10-19 5:20 ` Ashutosh Dixit @ 2022-10-19 5:20 ` Ashutosh Dixit -1 siblings, 0 replies; 26+ messages in thread From: Ashutosh Dixit @ 2022-10-19 5:20 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi From: Don Hiatt <don.hiatt@intel.com> On GEN12+ use GEN12_RPSTAT register to get actual resolved GT freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if GT is in RC6. v2: - Fixed review comments(Ashutosh) - Added function intel_rps_read_rpstat_fw to read RPSTAT without forcewake, required especially for GEN6_RPSTAT1 (Ashutosh, Tvrtko) v3: - Updated commit title and message for more clarity (Ashutosh) - Replaced intel_rps_read_rpstat with direct read to GEN12_RPSTAT1 in read_cagf (Ashutosh) Cc: Don Hiatt <donhiatt@gmail.com> Cc: Andi Shyti <andi.shyti@intel.com> Signed-off-by: Don Hiatt <don.hiatt@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ drivers/gpu/drm/i915/gt/intel_rps.c | 32 +++++++++++++++++++++---- drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++ drivers/gpu/drm/i915/i915_pmu.c | 3 +-- 4 files changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 36d95b79022c0..a7a0129d0e3fc 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1543,6 +1543,8 @@ #define GEN12_RPSTAT1 _MMIO(0x1381b4) #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0) +#define GEN12_CAGF_SHIFT 11 +#define GEN12_CAGF_MASK REG_GENMASK(19, 11) #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) #define GEN11_CSME (31) diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index fc23c562d9b2a..df21258976d86 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -2068,12 +2068,34 @@ void intel_rps_sanitize(struct intel_rps *rps) rps_disable_interrupts(rps); } +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps) +{ + struct drm_i915_private *i915 = rps_to_i915(rps); + i915_reg_t rpstat; + + rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1; + + return intel_uncore_read_fw(rps_to_gt(rps)->uncore, rpstat); +} + +u32 intel_rps_read_rpstat(struct intel_rps *rps) +{ + struct drm_i915_private *i915 = rps_to_i915(rps); + i915_reg_t rpstat; + + rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1; + + return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat); +} + u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) { struct drm_i915_private *i915 = rps_to_i915(rps); u32 cagf; - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) + if (GRAPHICS_VER(i915) >= 12) + cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) cagf = (rpstat >> 8) & 0xff; else if (GRAPHICS_VER(i915) >= 9) cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; @@ -2094,7 +2116,9 @@ static u32 read_cagf(struct intel_rps *rps) struct intel_uncore *uncore = rps_to_uncore(rps); u32 freq; - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { + if (GRAPHICS_VER(i915) >= 12) { + freq = intel_uncore_read(uncore, GEN12_RPSTAT1); + } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { vlv_punit_get(i915); freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); vlv_punit_put(i915); @@ -2260,7 +2284,7 @@ static void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p) rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD); rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD); - rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1); + rpstat = intel_rps_read_rpstat(rps); rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; @@ -2395,7 +2419,7 @@ static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p) drm_printf(p, "PM MASK=0x%08x\n", pm_mask); drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n", rps->pm_intrmsk_mbz); - drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, GEN6_RPSTAT1)); + drm_printf(p, "RPSTAT1: 0x%08x\n", intel_rps_read_rpstat(rps)); drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps)); drm_printf(p, "Lowest (RPN) frequency: %dMHz\n", intel_gpu_freq(rps, caps.min_freq)); diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h index 110300dfd4383..9e1cad9ba0e9c 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.h +++ b/drivers/gpu/drm/i915/gt/intel_rps.h @@ -48,6 +48,8 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps); u32 intel_rps_get_rpn_frequency(struct intel_rps *rps); u32 intel_rps_read_punit_req(struct intel_rps *rps); u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps); +u32 intel_rps_read_rpstat(struct intel_rps *rps); +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps); void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps); void intel_rps_raise_unslice(struct intel_rps *rps); void intel_rps_lower_unslice(struct intel_rps *rps); diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 958b37123bf12..67140a87182f8 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -371,7 +371,6 @@ static void frequency_sample(struct intel_gt *gt, unsigned int period_ns) { struct drm_i915_private *i915 = gt->i915; - struct intel_uncore *uncore = gt->uncore; struct i915_pmu *pmu = &i915->pmu; struct intel_rps *rps = >->rps; @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns) * case we assume the system is running at the intended * frequency. Fortunately, the read should rarely fail! */ - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1); + val = intel_rps_read_rpstat_fw(rps); if (val) val = intel_rps_get_cagf(rps, val); else -- 2.38.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 1/4] drm/i915: Use GEN12_RPSTAT register for GT freq @ 2022-10-19 5:20 ` Ashutosh Dixit 0 siblings, 0 replies; 26+ messages in thread From: Ashutosh Dixit @ 2022-10-19 5:20 UTC (permalink / raw) To: intel-gfx; +Cc: Anshuman Gupta, Badal Nilawar, dri-devel, Rodrigo Vivi From: Don Hiatt <don.hiatt@intel.com> On GEN12+ use GEN12_RPSTAT register to get actual resolved GT freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if GT is in RC6. v2: - Fixed review comments(Ashutosh) - Added function intel_rps_read_rpstat_fw to read RPSTAT without forcewake, required especially for GEN6_RPSTAT1 (Ashutosh, Tvrtko) v3: - Updated commit title and message for more clarity (Ashutosh) - Replaced intel_rps_read_rpstat with direct read to GEN12_RPSTAT1 in read_cagf (Ashutosh) Cc: Don Hiatt <donhiatt@gmail.com> Cc: Andi Shyti <andi.shyti@intel.com> Signed-off-by: Don Hiatt <don.hiatt@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ drivers/gpu/drm/i915/gt/intel_rps.c | 32 +++++++++++++++++++++---- drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++ drivers/gpu/drm/i915/i915_pmu.c | 3 +-- 4 files changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 36d95b79022c0..a7a0129d0e3fc 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1543,6 +1543,8 @@ #define GEN12_RPSTAT1 _MMIO(0x1381b4) #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0) +#define GEN12_CAGF_SHIFT 11 +#define GEN12_CAGF_MASK REG_GENMASK(19, 11) #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) #define GEN11_CSME (31) diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index fc23c562d9b2a..df21258976d86 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -2068,12 +2068,34 @@ void intel_rps_sanitize(struct intel_rps *rps) rps_disable_interrupts(rps); } +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps) +{ + struct drm_i915_private *i915 = rps_to_i915(rps); + i915_reg_t rpstat; + + rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1; + + return intel_uncore_read_fw(rps_to_gt(rps)->uncore, rpstat); +} + +u32 intel_rps_read_rpstat(struct intel_rps *rps) +{ + struct drm_i915_private *i915 = rps_to_i915(rps); + i915_reg_t rpstat; + + rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1; + + return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat); +} + u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) { struct drm_i915_private *i915 = rps_to_i915(rps); u32 cagf; - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) + if (GRAPHICS_VER(i915) >= 12) + cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) cagf = (rpstat >> 8) & 0xff; else if (GRAPHICS_VER(i915) >= 9) cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; @@ -2094,7 +2116,9 @@ static u32 read_cagf(struct intel_rps *rps) struct intel_uncore *uncore = rps_to_uncore(rps); u32 freq; - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { + if (GRAPHICS_VER(i915) >= 12) { + freq = intel_uncore_read(uncore, GEN12_RPSTAT1); + } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { vlv_punit_get(i915); freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); vlv_punit_put(i915); @@ -2260,7 +2284,7 @@ static void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p) rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD); rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD); - rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1); + rpstat = intel_rps_read_rpstat(rps); rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; @@ -2395,7 +2419,7 @@ static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p) drm_printf(p, "PM MASK=0x%08x\n", pm_mask); drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n", rps->pm_intrmsk_mbz); - drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, GEN6_RPSTAT1)); + drm_printf(p, "RPSTAT1: 0x%08x\n", intel_rps_read_rpstat(rps)); drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps)); drm_printf(p, "Lowest (RPN) frequency: %dMHz\n", intel_gpu_freq(rps, caps.min_freq)); diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h index 110300dfd4383..9e1cad9ba0e9c 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.h +++ b/drivers/gpu/drm/i915/gt/intel_rps.h @@ -48,6 +48,8 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps); u32 intel_rps_get_rpn_frequency(struct intel_rps *rps); u32 intel_rps_read_punit_req(struct intel_rps *rps); u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps); +u32 intel_rps_read_rpstat(struct intel_rps *rps); +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps); void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps); void intel_rps_raise_unslice(struct intel_rps *rps); void intel_rps_lower_unslice(struct intel_rps *rps); diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 958b37123bf12..67140a87182f8 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -371,7 +371,6 @@ static void frequency_sample(struct intel_gt *gt, unsigned int period_ns) { struct drm_i915_private *i915 = gt->i915; - struct intel_uncore *uncore = gt->uncore; struct i915_pmu *pmu = &i915->pmu; struct intel_rps *rps = >->rps; @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns) * case we assume the system is running at the intended * frequency. Fortunately, the read should rarely fail! */ - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1); + val = intel_rps_read_rpstat_fw(rps); if (val) val = intel_rps_get_cagf(rps, val); else -- 2.38.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915: Use GEN12_RPSTAT register for GT freq 2022-10-19 5:20 ` Ashutosh Dixit @ 2022-10-19 15:06 ` Rodrigo Vivi -1 siblings, 0 replies; 26+ messages in thread From: Rodrigo Vivi @ 2022-10-19 15:06 UTC (permalink / raw) To: Ashutosh Dixit; +Cc: intel-gfx, dri-devel On Tue, Oct 18, 2022 at 10:20:40PM -0700, Ashutosh Dixit wrote: > From: Don Hiatt <don.hiatt@intel.com> > > On GEN12+ use GEN12_RPSTAT register to get actual resolved GT > freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if > GT is in RC6. > > v2: > - Fixed review comments(Ashutosh) > - Added function intel_rps_read_rpstat_fw to read RPSTAT without > forcewake, required especially for GEN6_RPSTAT1 (Ashutosh, Tvrtko) > v3: > - Updated commit title and message for more clarity (Ashutosh) > - Replaced intel_rps_read_rpstat with direct read to GEN12_RPSTAT1 in > read_cagf (Ashutosh) > > Cc: Don Hiatt <donhiatt@gmail.com> > Cc: Andi Shyti <andi.shyti@intel.com> > Signed-off-by: Don Hiatt <don.hiatt@intel.com> > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> > Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ > drivers/gpu/drm/i915/gt/intel_rps.c | 32 +++++++++++++++++++++---- > drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++ > drivers/gpu/drm/i915/i915_pmu.c | 3 +-- > 4 files changed, 33 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 36d95b79022c0..a7a0129d0e3fc 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1543,6 +1543,8 @@ > > #define GEN12_RPSTAT1 _MMIO(0x1381b4) > #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0) > +#define GEN12_CAGF_SHIFT 11 we don't need to define the shift if we use the REG_FIELD_GET > +#define GEN12_CAGF_MASK REG_GENMASK(19, 11) ah, cool, this is already right and in place (ignore my comment about this in the other patch) > > #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) > #define GEN11_CSME (31) > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > index fc23c562d9b2a..df21258976d86 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > @@ -2068,12 +2068,34 @@ void intel_rps_sanitize(struct intel_rps *rps) > rps_disable_interrupts(rps); > } > > +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps) > +{ > + struct drm_i915_private *i915 = rps_to_i915(rps); > + i915_reg_t rpstat; > + > + rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1; > + > + return intel_uncore_read_fw(rps_to_gt(rps)->uncore, rpstat); > +} > + > +u32 intel_rps_read_rpstat(struct intel_rps *rps) > +{ > + struct drm_i915_private *i915 = rps_to_i915(rps); > + i915_reg_t rpstat; > + > + rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1; > + > + return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat); > +} > + > u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) > { > struct drm_i915_private *i915 = rps_to_i915(rps); > u32 cagf; > > - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > + if (GRAPHICS_VER(i915) >= 12) > + cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat); > + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > cagf = (rpstat >> 8) & 0xff; > else if (GRAPHICS_VER(i915) >= 9) > cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; > @@ -2094,7 +2116,9 @@ static u32 read_cagf(struct intel_rps *rps) > struct intel_uncore *uncore = rps_to_uncore(rps); > u32 freq; > > - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > + if (GRAPHICS_VER(i915) >= 12) { > + freq = intel_uncore_read(uncore, GEN12_RPSTAT1); > + } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > vlv_punit_get(i915); > freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); > vlv_punit_put(i915); > @@ -2260,7 +2284,7 @@ static void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p) > rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD); > rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD); > > - rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1); > + rpstat = intel_rps_read_rpstat(rps); > rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; > rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; > rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; > @@ -2395,7 +2419,7 @@ static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p) > drm_printf(p, "PM MASK=0x%08x\n", pm_mask); > drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n", > rps->pm_intrmsk_mbz); > - drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, GEN6_RPSTAT1)); > + drm_printf(p, "RPSTAT1: 0x%08x\n", intel_rps_read_rpstat(rps)); > drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps)); > drm_printf(p, "Lowest (RPN) frequency: %dMHz\n", > intel_gpu_freq(rps, caps.min_freq)); > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h > index 110300dfd4383..9e1cad9ba0e9c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.h > +++ b/drivers/gpu/drm/i915/gt/intel_rps.h > @@ -48,6 +48,8 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps); > u32 intel_rps_get_rpn_frequency(struct intel_rps *rps); > u32 intel_rps_read_punit_req(struct intel_rps *rps); > u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps); > +u32 intel_rps_read_rpstat(struct intel_rps *rps); > +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps); > void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps); > void intel_rps_raise_unslice(struct intel_rps *rps); > void intel_rps_lower_unslice(struct intel_rps *rps); > diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c > index 958b37123bf12..67140a87182f8 100644 > --- a/drivers/gpu/drm/i915/i915_pmu.c > +++ b/drivers/gpu/drm/i915/i915_pmu.c > @@ -371,7 +371,6 @@ static void > frequency_sample(struct intel_gt *gt, unsigned int period_ns) > { > struct drm_i915_private *i915 = gt->i915; > - struct intel_uncore *uncore = gt->uncore; > struct i915_pmu *pmu = &i915->pmu; > struct intel_rps *rps = >->rps; > > @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns) > * case we assume the system is running at the intended > * frequency. Fortunately, the read should rarely fail! > */ > - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1); > + val = intel_rps_read_rpstat_fw(rps); > if (val) > val = intel_rps_get_cagf(rps, val); > else > -- > 2.38.0 > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 1/4] drm/i915: Use GEN12_RPSTAT register for GT freq @ 2022-10-19 15:06 ` Rodrigo Vivi 0 siblings, 0 replies; 26+ messages in thread From: Rodrigo Vivi @ 2022-10-19 15:06 UTC (permalink / raw) To: Ashutosh Dixit; +Cc: Anshuman Gupta, intel-gfx, Badal Nilawar, dri-devel On Tue, Oct 18, 2022 at 10:20:40PM -0700, Ashutosh Dixit wrote: > From: Don Hiatt <don.hiatt@intel.com> > > On GEN12+ use GEN12_RPSTAT register to get actual resolved GT > freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if > GT is in RC6. > > v2: > - Fixed review comments(Ashutosh) > - Added function intel_rps_read_rpstat_fw to read RPSTAT without > forcewake, required especially for GEN6_RPSTAT1 (Ashutosh, Tvrtko) > v3: > - Updated commit title and message for more clarity (Ashutosh) > - Replaced intel_rps_read_rpstat with direct read to GEN12_RPSTAT1 in > read_cagf (Ashutosh) > > Cc: Don Hiatt <donhiatt@gmail.com> > Cc: Andi Shyti <andi.shyti@intel.com> > Signed-off-by: Don Hiatt <don.hiatt@intel.com> > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> > Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++ > drivers/gpu/drm/i915/gt/intel_rps.c | 32 +++++++++++++++++++++---- > drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++ > drivers/gpu/drm/i915/i915_pmu.c | 3 +-- > 4 files changed, 33 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 36d95b79022c0..a7a0129d0e3fc 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1543,6 +1543,8 @@ > > #define GEN12_RPSTAT1 _MMIO(0x1381b4) > #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0) > +#define GEN12_CAGF_SHIFT 11 we don't need to define the shift if we use the REG_FIELD_GET > +#define GEN12_CAGF_MASK REG_GENMASK(19, 11) ah, cool, this is already right and in place (ignore my comment about this in the other patch) > > #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) > #define GEN11_CSME (31) > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > index fc23c562d9b2a..df21258976d86 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > @@ -2068,12 +2068,34 @@ void intel_rps_sanitize(struct intel_rps *rps) > rps_disable_interrupts(rps); > } > > +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps) > +{ > + struct drm_i915_private *i915 = rps_to_i915(rps); > + i915_reg_t rpstat; > + > + rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1; > + > + return intel_uncore_read_fw(rps_to_gt(rps)->uncore, rpstat); > +} > + > +u32 intel_rps_read_rpstat(struct intel_rps *rps) > +{ > + struct drm_i915_private *i915 = rps_to_i915(rps); > + i915_reg_t rpstat; > + > + rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1; > + > + return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat); > +} > + > u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) > { > struct drm_i915_private *i915 = rps_to_i915(rps); > u32 cagf; > > - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > + if (GRAPHICS_VER(i915) >= 12) > + cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat); > + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > cagf = (rpstat >> 8) & 0xff; > else if (GRAPHICS_VER(i915) >= 9) > cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; > @@ -2094,7 +2116,9 @@ static u32 read_cagf(struct intel_rps *rps) > struct intel_uncore *uncore = rps_to_uncore(rps); > u32 freq; > > - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > + if (GRAPHICS_VER(i915) >= 12) { > + freq = intel_uncore_read(uncore, GEN12_RPSTAT1); > + } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > vlv_punit_get(i915); > freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); > vlv_punit_put(i915); > @@ -2260,7 +2284,7 @@ static void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p) > rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD); > rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD); > > - rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1); > + rpstat = intel_rps_read_rpstat(rps); > rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; > rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; > rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; > @@ -2395,7 +2419,7 @@ static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p) > drm_printf(p, "PM MASK=0x%08x\n", pm_mask); > drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n", > rps->pm_intrmsk_mbz); > - drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, GEN6_RPSTAT1)); > + drm_printf(p, "RPSTAT1: 0x%08x\n", intel_rps_read_rpstat(rps)); > drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps)); > drm_printf(p, "Lowest (RPN) frequency: %dMHz\n", > intel_gpu_freq(rps, caps.min_freq)); > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h > index 110300dfd4383..9e1cad9ba0e9c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.h > +++ b/drivers/gpu/drm/i915/gt/intel_rps.h > @@ -48,6 +48,8 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps); > u32 intel_rps_get_rpn_frequency(struct intel_rps *rps); > u32 intel_rps_read_punit_req(struct intel_rps *rps); > u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps); > +u32 intel_rps_read_rpstat(struct intel_rps *rps); > +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps); > void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps); > void intel_rps_raise_unslice(struct intel_rps *rps); > void intel_rps_lower_unslice(struct intel_rps *rps); > diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c > index 958b37123bf12..67140a87182f8 100644 > --- a/drivers/gpu/drm/i915/i915_pmu.c > +++ b/drivers/gpu/drm/i915/i915_pmu.c > @@ -371,7 +371,6 @@ static void > frequency_sample(struct intel_gt *gt, unsigned int period_ns) > { > struct drm_i915_private *i915 = gt->i915; > - struct intel_uncore *uncore = gt->uncore; > struct i915_pmu *pmu = &i915->pmu; > struct intel_rps *rps = >->rps; > > @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns) > * case we assume the system is running at the intended > * frequency. Fortunately, the read should rarely fail! > */ > - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1); > + val = intel_rps_read_rpstat_fw(rps); > if (val) > val = intel_rps_get_cagf(rps, val); > else > -- > 2.38.0 > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915: Use GEN12_RPSTAT register for GT freq 2022-10-19 15:06 ` Rodrigo Vivi @ 2022-10-19 23:42 ` Dixit, Ashutosh -1 siblings, 0 replies; 26+ messages in thread From: Dixit, Ashutosh @ 2022-10-19 23:42 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-gfx, dri-devel On Wed, 19 Oct 2022 08:06:26 -0700, Rodrigo Vivi wrote: > Hi Rodrigo, > On Tue, Oct 18, 2022 at 10:20:40PM -0700, Ashutosh Dixit wrote: > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > index 36d95b79022c0..a7a0129d0e3fc 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > @@ -1543,6 +1543,8 @@ > > > > #define GEN12_RPSTAT1 _MMIO(0x1381b4) > > #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0) > > +#define GEN12_CAGF_SHIFT 11 > > we don't need to define the shift if we use the REG_FIELD_GET Yes I was also suggesting this but then went ahead with the mask/shift based code to match previous style in the function. In any case based on your suggestions I have added a new patch is series version v8 which converts all previous branches in intel_rps_get_cagf to REG_FIELD_GET so that the new code can also consistently use REG_FIELD_GET. > > > +#define GEN12_CAGF_MASK REG_GENMASK(19, 11) > > ah, cool, this is already right and in place > (ignore my comment about this in the other patch) > > u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) > > { > > struct drm_i915_private *i915 = rps_to_i915(rps); > > u32 cagf; > > > > - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > > + if (GRAPHICS_VER(i915) >= 12) > > + cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; > > cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat); > > > + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > > cagf = (rpstat >> 8) & 0xff; > > else if (GRAPHICS_VER(i915) >= 9) > > cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; Thanks. -- Ashutosh ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 1/4] drm/i915: Use GEN12_RPSTAT register for GT freq @ 2022-10-19 23:42 ` Dixit, Ashutosh 0 siblings, 0 replies; 26+ messages in thread From: Dixit, Ashutosh @ 2022-10-19 23:42 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: Anshuman Gupta, intel-gfx, Badal Nilawar, dri-devel On Wed, 19 Oct 2022 08:06:26 -0700, Rodrigo Vivi wrote: > Hi Rodrigo, > On Tue, Oct 18, 2022 at 10:20:40PM -0700, Ashutosh Dixit wrote: > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > index 36d95b79022c0..a7a0129d0e3fc 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > @@ -1543,6 +1543,8 @@ > > > > #define GEN12_RPSTAT1 _MMIO(0x1381b4) > > #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0) > > +#define GEN12_CAGF_SHIFT 11 > > we don't need to define the shift if we use the REG_FIELD_GET Yes I was also suggesting this but then went ahead with the mask/shift based code to match previous style in the function. In any case based on your suggestions I have added a new patch is series version v8 which converts all previous branches in intel_rps_get_cagf to REG_FIELD_GET so that the new code can also consistently use REG_FIELD_GET. > > > +#define GEN12_CAGF_MASK REG_GENMASK(19, 11) > > ah, cool, this is already right and in place > (ignore my comment about this in the other patch) > > u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) > > { > > struct drm_i915_private *i915 = rps_to_i915(rps); > > u32 cagf; > > > > - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > > + if (GRAPHICS_VER(i915) >= 12) > > + cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; > > cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat); > > > + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > > cagf = (rpstat >> 8) & 0xff; > > else if (GRAPHICS_VER(i915) >= 9) > > cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; Thanks. -- Ashutosh ^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 2/4] drm/i915/mtl: Modify CAGF functions for MTL 2022-10-19 5:20 ` Ashutosh Dixit @ 2022-10-19 5:20 ` Ashutosh Dixit -1 siblings, 0 replies; 26+ messages in thread From: Ashutosh Dixit @ 2022-10-19 5:20 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi From: Badal Nilawar <badal.nilawar@intel.com> Update CAGF functions for MTL to get actual resolved frequency of 3D and SAMedia. v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR) Move MTL branches in cagf functions to top (MattR) Fix commit message (Andi) v3: Added comment about registers not needing forcewake for Gen12+ and returning 0 freq in RC6 Bspec: 66300 Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++++ drivers/gpu/drm/i915/gt/intel_rps.c | 12 ++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index a7a0129d0e3fc..b4b1b54ad738f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -21,6 +21,10 @@ */ #define PERF_REG(offset) _MMIO(offset) +/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */ +#define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60) +#define MTL_CAGF_MASK REG_GENMASK(8, 0) + /* RPM unit config (Gen8+) */ #define RPM_CONFIG0 _MMIO(0xd00) #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index df21258976d86..5a743ae4dd11e 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -2093,7 +2093,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) struct drm_i915_private *i915 = rps_to_i915(rps); u32 cagf; - if (GRAPHICS_VER(i915) >= 12) + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) + cagf = rpstat & MTL_CAGF_MASK; + else if (GRAPHICS_VER(i915) >= 12) cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) cagf = (rpstat >> 8) & 0xff; @@ -2116,7 +2118,13 @@ static u32 read_cagf(struct intel_rps *rps) struct intel_uncore *uncore = rps_to_uncore(rps); u32 freq; - if (GRAPHICS_VER(i915) >= 12) { + /* + * For Gen12+ reading freq from HW does not need a forcewake and + * registers will return 0 freq when GT is in RC6 + */ + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { + freq = intel_uncore_read(rps_to_gt(rps)->uncore, MTL_MIRROR_TARGET_WP1); + } else if (GRAPHICS_VER(i915) >= 12) { freq = intel_uncore_read(uncore, GEN12_RPSTAT1); } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { vlv_punit_get(i915); -- 2.38.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 2/4] drm/i915/mtl: Modify CAGF functions for MTL @ 2022-10-19 5:20 ` Ashutosh Dixit 0 siblings, 0 replies; 26+ messages in thread From: Ashutosh Dixit @ 2022-10-19 5:20 UTC (permalink / raw) To: intel-gfx; +Cc: Anshuman Gupta, Badal Nilawar, dri-devel, Rodrigo Vivi From: Badal Nilawar <badal.nilawar@intel.com> Update CAGF functions for MTL to get actual resolved frequency of 3D and SAMedia. v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR) Move MTL branches in cagf functions to top (MattR) Fix commit message (Andi) v3: Added comment about registers not needing forcewake for Gen12+ and returning 0 freq in RC6 Bspec: 66300 Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++++ drivers/gpu/drm/i915/gt/intel_rps.c | 12 ++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index a7a0129d0e3fc..b4b1b54ad738f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -21,6 +21,10 @@ */ #define PERF_REG(offset) _MMIO(offset) +/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */ +#define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60) +#define MTL_CAGF_MASK REG_GENMASK(8, 0) + /* RPM unit config (Gen8+) */ #define RPM_CONFIG0 _MMIO(0xd00) #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index df21258976d86..5a743ae4dd11e 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -2093,7 +2093,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) struct drm_i915_private *i915 = rps_to_i915(rps); u32 cagf; - if (GRAPHICS_VER(i915) >= 12) + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) + cagf = rpstat & MTL_CAGF_MASK; + else if (GRAPHICS_VER(i915) >= 12) cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) cagf = (rpstat >> 8) & 0xff; @@ -2116,7 +2118,13 @@ static u32 read_cagf(struct intel_rps *rps) struct intel_uncore *uncore = rps_to_uncore(rps); u32 freq; - if (GRAPHICS_VER(i915) >= 12) { + /* + * For Gen12+ reading freq from HW does not need a forcewake and + * registers will return 0 freq when GT is in RC6 + */ + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { + freq = intel_uncore_read(rps_to_gt(rps)->uncore, MTL_MIRROR_TARGET_WP1); + } else if (GRAPHICS_VER(i915) >= 12) { freq = intel_uncore_read(uncore, GEN12_RPSTAT1); } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { vlv_punit_get(i915); -- 2.38.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915/mtl: Modify CAGF functions for MTL 2022-10-19 5:20 ` Ashutosh Dixit @ 2022-10-19 14:58 ` Rodrigo Vivi -1 siblings, 0 replies; 26+ messages in thread From: Rodrigo Vivi @ 2022-10-19 14:58 UTC (permalink / raw) To: Ashutosh Dixit; +Cc: intel-gfx, dri-devel On Tue, Oct 18, 2022 at 10:20:41PM -0700, Ashutosh Dixit wrote: > From: Badal Nilawar <badal.nilawar@intel.com> > > Update CAGF functions for MTL to get actual resolved frequency of 3D and > SAMedia. > > v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR) > Move MTL branches in cagf functions to top (MattR) > Fix commit message (Andi) > v3: Added comment about registers not needing forcewake for Gen12+ and > returning 0 freq in RC6 > > Bspec: 66300 > > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++++ > drivers/gpu/drm/i915/gt/intel_rps.c | 12 ++++++++++-- > 2 files changed, 14 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index a7a0129d0e3fc..b4b1b54ad738f 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -21,6 +21,10 @@ > */ > #define PERF_REG(offset) _MMIO(offset) > > +/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */ > +#define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60) > +#define MTL_CAGF_MASK REG_GENMASK(8, 0) > + > /* RPM unit config (Gen8+) */ > #define RPM_CONFIG0 _MMIO(0xd00) > #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > index df21258976d86..5a743ae4dd11e 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > @@ -2093,7 +2093,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) > struct drm_i915_private *i915 = rps_to_i915(rps); > u32 cagf; > > - if (GRAPHICS_VER(i915) >= 12) > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) > + cagf = rpstat & MTL_CAGF_MASK; I believe we should advocate more the use of the REG_FIELD_GET cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat); > + else if (GRAPHICS_VER(i915) >= 12) > cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat); // witht the proper REG_GENAMSK usage on the gen12_cagf_mask... > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > cagf = (rpstat >> 8) & 0xff; #define RPE_MASK REG_GENMASK(15, 8) cagf = REG_FIELD_GET(RPE_MASK, rpstat) > @@ -2116,7 +2118,13 @@ static u32 read_cagf(struct intel_rps *rps) > struct intel_uncore *uncore = rps_to_uncore(rps); ^ > u32 freq; > > - if (GRAPHICS_VER(i915) >= 12) { > + /* > + * For Gen12+ reading freq from HW does not need a forcewake and > + * registers will return 0 freq when GT is in RC6 > + */ > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { > + freq = intel_uncore_read(rps_to_gt(rps)->uncore, MTL_MIRROR_TARGET_WP1); here we should use directly the local uncore already declared above with the same helper... and consistent with the following elses... > + } else if (GRAPHICS_VER(i915) >= 12) { > freq = intel_uncore_read(uncore, GEN12_RPSTAT1); > } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > vlv_punit_get(i915); > -- > 2.38.0 > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 2/4] drm/i915/mtl: Modify CAGF functions for MTL @ 2022-10-19 14:58 ` Rodrigo Vivi 0 siblings, 0 replies; 26+ messages in thread From: Rodrigo Vivi @ 2022-10-19 14:58 UTC (permalink / raw) To: Ashutosh Dixit; +Cc: Anshuman Gupta, intel-gfx, Badal Nilawar, dri-devel On Tue, Oct 18, 2022 at 10:20:41PM -0700, Ashutosh Dixit wrote: > From: Badal Nilawar <badal.nilawar@intel.com> > > Update CAGF functions for MTL to get actual resolved frequency of 3D and > SAMedia. > > v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR) > Move MTL branches in cagf functions to top (MattR) > Fix commit message (Andi) > v3: Added comment about registers not needing forcewake for Gen12+ and > returning 0 freq in RC6 > > Bspec: 66300 > > Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++++ > drivers/gpu/drm/i915/gt/intel_rps.c | 12 ++++++++++-- > 2 files changed, 14 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index a7a0129d0e3fc..b4b1b54ad738f 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -21,6 +21,10 @@ > */ > #define PERF_REG(offset) _MMIO(offset) > > +/* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */ > +#define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60) > +#define MTL_CAGF_MASK REG_GENMASK(8, 0) > + > /* RPM unit config (Gen8+) */ > #define RPM_CONFIG0 _MMIO(0xd00) > #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > index df21258976d86..5a743ae4dd11e 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > @@ -2093,7 +2093,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) > struct drm_i915_private *i915 = rps_to_i915(rps); > u32 cagf; > > - if (GRAPHICS_VER(i915) >= 12) > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) > + cagf = rpstat & MTL_CAGF_MASK; I believe we should advocate more the use of the REG_FIELD_GET cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat); > + else if (GRAPHICS_VER(i915) >= 12) > cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat); // witht the proper REG_GENAMSK usage on the gen12_cagf_mask... > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > cagf = (rpstat >> 8) & 0xff; #define RPE_MASK REG_GENMASK(15, 8) cagf = REG_FIELD_GET(RPE_MASK, rpstat) > @@ -2116,7 +2118,13 @@ static u32 read_cagf(struct intel_rps *rps) > struct intel_uncore *uncore = rps_to_uncore(rps); ^ > u32 freq; > > - if (GRAPHICS_VER(i915) >= 12) { > + /* > + * For Gen12+ reading freq from HW does not need a forcewake and > + * registers will return 0 freq when GT is in RC6 > + */ > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { > + freq = intel_uncore_read(rps_to_gt(rps)->uncore, MTL_MIRROR_TARGET_WP1); here we should use directly the local uncore already declared above with the same helper... and consistent with the following elses... > + } else if (GRAPHICS_VER(i915) >= 12) { > freq = intel_uncore_read(uncore, GEN12_RPSTAT1); > } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > vlv_punit_get(i915); > -- > 2.38.0 > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915/mtl: Modify CAGF functions for MTL 2022-10-19 14:58 ` Rodrigo Vivi @ 2022-10-19 23:43 ` Dixit, Ashutosh -1 siblings, 0 replies; 26+ messages in thread From: Dixit, Ashutosh @ 2022-10-19 23:43 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-gfx, dri-devel On Wed, 19 Oct 2022 07:58:13 -0700, Rodrigo Vivi wrote: > > On Tue, Oct 18, 2022 at 10:20:41PM -0700, Ashutosh Dixit wrote: > > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > > index df21258976d86..5a743ae4dd11e 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > > @@ -2093,7 +2093,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) > > struct drm_i915_private *i915 = rps_to_i915(rps); > > u32 cagf; > > > > - if (GRAPHICS_VER(i915) >= 12) > > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) > > + cagf = rpstat & MTL_CAGF_MASK; > > I believe we should advocate more the use of the REG_FIELD_GET > > cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat); > > > + else if (GRAPHICS_VER(i915) >= 12) > > cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; > > cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat); > // witht the proper REG_GENAMSK usage on the gen12_cagf_mask... > > > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > > cagf = (rpstat >> 8) & 0xff; > > #define RPE_MASK REG_GENMASK(15, 8) > cagf = REG_FIELD_GET(RPE_MASK, rpstat) All these are now converted to REG_FIELD_GET in series version v8. > > @@ -2116,7 +2118,13 @@ static u32 read_cagf(struct intel_rps *rps) > > struct intel_uncore *uncore = rps_to_uncore(rps); > ^ > > > u32 freq; > > > > - if (GRAPHICS_VER(i915) >= 12) { > > + /* > > + * For Gen12+ reading freq from HW does not need a forcewake and > > + * registers will return 0 freq when GT is in RC6 > > + */ > > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { > > + freq = intel_uncore_read(rps_to_gt(rps)->uncore, MTL_MIRROR_TARGET_WP1); > > here we should use directly the local uncore already declared above with > the same helper... and consistent with the following elses... Fixed. > > > + } else if (GRAPHICS_VER(i915) >= 12) { > > freq = intel_uncore_read(uncore, GEN12_RPSTAT1); > > } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > > vlv_punit_get(i915); > > -- > > 2.38.0 > > Thanks. -- Ashutosh ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 2/4] drm/i915/mtl: Modify CAGF functions for MTL @ 2022-10-19 23:43 ` Dixit, Ashutosh 0 siblings, 0 replies; 26+ messages in thread From: Dixit, Ashutosh @ 2022-10-19 23:43 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: Anshuman Gupta, intel-gfx, Badal Nilawar, dri-devel On Wed, 19 Oct 2022 07:58:13 -0700, Rodrigo Vivi wrote: > > On Tue, Oct 18, 2022 at 10:20:41PM -0700, Ashutosh Dixit wrote: > > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > > index df21258976d86..5a743ae4dd11e 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > > @@ -2093,7 +2093,9 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat) > > struct drm_i915_private *i915 = rps_to_i915(rps); > > u32 cagf; > > > > - if (GRAPHICS_VER(i915) >= 12) > > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) > > + cagf = rpstat & MTL_CAGF_MASK; > > I believe we should advocate more the use of the REG_FIELD_GET > > cagf = REG_FIELD_GET(MTL_CAGF_MASK, rpstat); > > > + else if (GRAPHICS_VER(i915) >= 12) > > cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT; > > cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat); > // witht the proper REG_GENAMSK usage on the gen12_cagf_mask... > > > else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > > cagf = (rpstat >> 8) & 0xff; > > #define RPE_MASK REG_GENMASK(15, 8) > cagf = REG_FIELD_GET(RPE_MASK, rpstat) All these are now converted to REG_FIELD_GET in series version v8. > > @@ -2116,7 +2118,13 @@ static u32 read_cagf(struct intel_rps *rps) > > struct intel_uncore *uncore = rps_to_uncore(rps); > ^ > > > u32 freq; > > > > - if (GRAPHICS_VER(i915) >= 12) { > > + /* > > + * For Gen12+ reading freq from HW does not need a forcewake and > > + * registers will return 0 freq when GT is in RC6 > > + */ > > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { > > + freq = intel_uncore_read(rps_to_gt(rps)->uncore, MTL_MIRROR_TARGET_WP1); > > here we should use directly the local uncore already declared above with > the same helper... and consistent with the following elses... Fixed. > > > + } else if (GRAPHICS_VER(i915) >= 12) { > > freq = intel_uncore_read(uncore, GEN12_RPSTAT1); > > } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > > vlv_punit_get(i915); > > -- > > 2.38.0 > > Thanks. -- Ashutosh ^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915/gt: Use RC6 residency types as arguments to residency functions 2022-10-19 5:20 ` Ashutosh Dixit @ 2022-10-19 5:20 ` Ashutosh Dixit -1 siblings, 0 replies; 26+ messages in thread From: Ashutosh Dixit @ 2022-10-19 5:20 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi Previously RC6 residency functions directly accepted RC6 residency register MMIO offsets (there are four RC6 residency registers). This worked but required an assumption on the residency register layout so was not future proof. Therefore change RC6 residency functions to accept RC6 residency types instead of register MMIO offsets. The knowledge of register offsets as well as ID to offset mapping is now maintained solely in intel_rc6 and can be tailored for different platforms and different register layouts as need arises. v2: Address review comments by Jani N - Change residency functions to accept RC6 residency types instead of register ID's - s/intel_rc6_print_rc5_res/intel_rc6_print_residency/ - Remove "const enum" in function arguments - Naming: intel_rc6_* for enum - Use INTEL_RC6_RES_MAX and other minor changes Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Suggested-by: Jani Nikula <jani.nikula@linux.intel.com> Reported-by: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 27 +++------ drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 ++-- drivers/gpu/drm/i915/gt/intel_rc6.c | 55 +++++++++++-------- drivers/gpu/drm/i915/gt/intel_rc6.h | 8 ++- drivers/gpu/drm/i915/gt/intel_rc6_types.h | 15 ++++- drivers/gpu/drm/i915/gt/selftest_rc6.c | 6 +- drivers/gpu/drm/i915/i915_pmu.c | 6 +- 7 files changed, 70 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c index 40d0a3be42acf..235d593cfaeba 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c @@ -83,19 +83,6 @@ static int fw_domains_show(struct seq_file *m, void *data) } DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(fw_domains); -static void print_rc6_res(struct seq_file *m, - const char *title, - const i915_reg_t reg) -{ - struct intel_gt *gt = m->private; - intel_wakeref_t wakeref; - - with_intel_runtime_pm(gt->uncore->rpm, wakeref) - seq_printf(m, "%s %u (%llu us)\n", title, - intel_uncore_read(gt->uncore, reg), - intel_rc6_residency_us(>->rc6, reg)); -} - static int vlv_drpc(struct seq_file *m) { struct intel_gt *gt = m->private; @@ -115,8 +102,8 @@ static int vlv_drpc(struct seq_file *m) seq_printf(m, "Media Power Well: %s\n", (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); - print_rc6_res(m, "Render RC6 residency since boot:", GEN6_GT_GFX_RC6); - print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6); + intel_rc6_print_residency(m, "Render RC6 residency since boot:", INTEL_RC6_RES_RC6); + intel_rc6_print_residency(m, "Media RC6 residency since boot:", INTEL_RC6_RES_VLV_MEDIA); return fw_domains_show(m, NULL); } @@ -192,11 +179,11 @@ static int gen6_drpc(struct seq_file *m) } /* Not exactly sure what this is */ - print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:", - GEN6_GT_GFX_RC6_LOCKED); - print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6); - print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p); - print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp); + intel_rc6_print_residency(m, "RC6 \"Locked to RPn\" residency since boot:", + INTEL_RC6_RES_RC6_LOCKED); + intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6); + intel_rc6_print_residency(m, "RC6+ residency since boot:", INTEL_RC6_RES_RC6p); + intel_rc6_print_residency(m, "RC6++ residency since boot:", INTEL_RC6_RES_RC6pp); if (GRAPHICS_VER(i915) <= 7) { seq_printf(m, "RC6 voltage: %dmV\n", diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c index 9041609523697..19a60000e052c 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c @@ -93,13 +93,13 @@ sysfs_gt_attribute_r_func(struct device *dev, struct device_attribute *attr, sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX) #ifdef CONFIG_PM -static u32 get_residency(struct intel_gt *gt, i915_reg_t reg) +static u32 get_residency(struct intel_gt *gt, enum intel_rc6_res_type id) { intel_wakeref_t wakeref; u64 res = 0; with_intel_runtime_pm(gt->uncore->rpm, wakeref) - res = intel_rc6_residency_us(>->rc6, reg); + res = intel_rc6_residency_us(>->rc6, id); return DIV_ROUND_CLOSEST_ULL(res, 1000); } @@ -123,7 +123,7 @@ static ssize_t rc6_enable_show(struct device *dev, static u32 __rc6_residency_ms_show(struct intel_gt *gt) { - return get_residency(gt, GEN6_GT_GFX_RC6); + return get_residency(gt, INTEL_RC6_RES_RC6); } static ssize_t rc6_residency_ms_show(struct device *dev, @@ -138,7 +138,7 @@ static ssize_t rc6_residency_ms_show(struct device *dev, static u32 __rc6p_residency_ms_show(struct intel_gt *gt) { - return get_residency(gt, GEN6_GT_GFX_RC6p); + return get_residency(gt, INTEL_RC6_RES_RC6p); } static ssize_t rc6p_residency_ms_show(struct device *dev, @@ -153,7 +153,7 @@ static ssize_t rc6p_residency_ms_show(struct device *dev, static u32 __rc6pp_residency_ms_show(struct intel_gt *gt) { - return get_residency(gt, GEN6_GT_GFX_RC6pp); + return get_residency(gt, INTEL_RC6_RES_RC6pp); } static ssize_t rc6pp_residency_ms_show(struct device *dev, @@ -168,7 +168,7 @@ static ssize_t rc6pp_residency_ms_show(struct device *dev, static u32 __media_rc6_residency_ms_show(struct intel_gt *gt) { - return get_residency(gt, VLV_GT_MEDIA_RC6); + return get_residency(gt, INTEL_RC6_RES_VLV_MEDIA); } static ssize_t media_rc6_residency_ms_show(struct device *dev, diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index f8d0523f4c18e..6db4e60d5fba5 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -551,6 +551,14 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6) intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); } +static void rc6_res_reg_init(struct intel_rc6 *rc6) +{ + rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED; + rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6; + rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p; + rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp; +} + void intel_rc6_init(struct intel_rc6 *rc6) { struct drm_i915_private *i915 = rc6_to_i915(rc6); @@ -562,6 +570,8 @@ void intel_rc6_init(struct intel_rc6 *rc6) if (!rc6_supported(rc6)) return; + rc6_res_reg_init(rc6); + if (IS_CHERRYVIEW(i915)) err = chv_rc6_init(rc6); else if (IS_VALLEYVIEW(i915)) @@ -736,31 +746,19 @@ static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg) return lower | (u64)upper << 8; } -u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg) +u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id) { struct drm_i915_private *i915 = rc6_to_i915(rc6); struct intel_uncore *uncore = rc6_to_uncore(rc6); u64 time_hw, prev_hw, overflow_hw; + i915_reg_t reg = rc6->res_reg[id]; unsigned int fw_domains; unsigned long flags; - unsigned int i; u32 mul, div; if (!rc6->supported) return 0; - /* - * Store previous hw counter values for counter wrap-around handling. - * - * There are only four interesting registers and they live next to each - * other so we can use the relative address, compared to the smallest - * one as the index into driver storage. - */ - i = (i915_mmio_reg_offset(reg) - - i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32); - if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency))) - return 0; - fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ); spin_lock_irqsave(&uncore->lock, flags); @@ -789,11 +787,11 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg) /* * Counter wrap handling. * - * But relying on a sufficient frequency of queries otherwise counters - * can still wrap. + * Store previous hw counter values for counter wrap-around handling. But + * relying on a sufficient frequency of queries otherwise counters can still wrap. */ - prev_hw = rc6->prev_hw_residency[i]; - rc6->prev_hw_residency[i] = time_hw; + prev_hw = rc6->prev_hw_residency[id]; + rc6->prev_hw_residency[id] = time_hw; /* RC6 delta from last sample. */ if (time_hw >= prev_hw) @@ -802,8 +800,8 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg) time_hw += overflow_hw - prev_hw; /* Add delta to RC6 extended raw driver copy. */ - time_hw += rc6->cur_residency[i]; - rc6->cur_residency[i] = time_hw; + time_hw += rc6->cur_residency[id]; + rc6->cur_residency[id] = time_hw; intel_uncore_forcewake_put__locked(uncore, fw_domains); spin_unlock_irqrestore(&uncore->lock, flags); @@ -811,9 +809,22 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg) return mul_u64_u32_div(time_hw, mul, div); } -u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg) +u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id) +{ + return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, id), 1000); +} + +void intel_rc6_print_residency(struct seq_file *m, const char *title, + enum intel_rc6_res_type id) { - return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, reg), 1000); + struct intel_gt *gt = m->private; + i915_reg_t reg = gt->rc6.res_reg[id]; + intel_wakeref_t wakeref; + + with_intel_runtime_pm(gt->uncore->rpm, wakeref) + seq_printf(m, "%s %u (%llu us)\n", title, + intel_uncore_read(gt->uncore, reg), + intel_rc6_residency_us(>->rc6, id)); } #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h b/drivers/gpu/drm/i915/gt/intel_rc6.h index b6fea71afc223..3105bc72c096b 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.h +++ b/drivers/gpu/drm/i915/gt/intel_rc6.h @@ -6,7 +6,7 @@ #ifndef INTEL_RC6_H #define INTEL_RC6_H -#include "i915_reg_defs.h" +#include "intel_rc6_types.h" struct intel_engine_cs; struct intel_rc6; @@ -21,7 +21,9 @@ void intel_rc6_sanitize(struct intel_rc6 *rc6); void intel_rc6_enable(struct intel_rc6 *rc6); void intel_rc6_disable(struct intel_rc6 *rc6); -u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, i915_reg_t reg); -u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg); +u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id); +u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id); +void intel_rc6_print_residency(struct seq_file *m, const char *title, + enum intel_rc6_res_type id); #endif /* INTEL_RC6_H */ diff --git a/drivers/gpu/drm/i915/gt/intel_rc6_types.h b/drivers/gpu/drm/i915/gt/intel_rc6_types.h index e747492b2f46e..fa23c4dce00b4 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6_types.h +++ b/drivers/gpu/drm/i915/gt/intel_rc6_types.h @@ -13,9 +13,20 @@ struct drm_i915_gem_object; +/* RC6 residency types */ +enum intel_rc6_res_type { + INTEL_RC6_RES_RC6_LOCKED, + INTEL_RC6_RES_RC6, + INTEL_RC6_RES_RC6p, + INTEL_RC6_RES_RC6pp, + INTEL_RC6_RES_MAX, + INTEL_RC6_RES_VLV_MEDIA = INTEL_RC6_RES_RC6p, +}; + struct intel_rc6 { - u64 prev_hw_residency[4]; - u64 cur_residency[4]; + i915_reg_t res_reg[INTEL_RC6_RES_MAX]; + u64 prev_hw_residency[INTEL_RC6_RES_MAX]; + u64 cur_residency[INTEL_RC6_RES_MAX]; u32 ctl_enable; diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c index 8c70b7e120749..2ceeadecc639c 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c @@ -19,11 +19,11 @@ static u64 rc6_residency(struct intel_rc6 *rc6) /* XXX VLV_GT_MEDIA_RC6? */ - result = intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6); + result = intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6); if (HAS_RC6p(rc6_to_i915(rc6))) - result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6p); + result += intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6p); if (HAS_RC6pp(rc6_to_i915(rc6))) - result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6pp); + result += intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6pp); return result; } diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 67140a87182f8..52531ab28c5f5 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -148,13 +148,13 @@ static u64 __get_rc6(struct intel_gt *gt) struct drm_i915_private *i915 = gt->i915; u64 val; - val = intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6); + val = intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6); if (HAS_RC6p(i915)) - val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6p); + val += intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6p); if (HAS_RC6pp(i915)) - val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6pp); + val += intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6pp); return val; } -- 2.38.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 3/4] drm/i915/gt: Use RC6 residency types as arguments to residency functions @ 2022-10-19 5:20 ` Ashutosh Dixit 0 siblings, 0 replies; 26+ messages in thread From: Ashutosh Dixit @ 2022-10-19 5:20 UTC (permalink / raw) To: intel-gfx; +Cc: Anshuman Gupta, Badal Nilawar, dri-devel, Rodrigo Vivi Previously RC6 residency functions directly accepted RC6 residency register MMIO offsets (there are four RC6 residency registers). This worked but required an assumption on the residency register layout so was not future proof. Therefore change RC6 residency functions to accept RC6 residency types instead of register MMIO offsets. The knowledge of register offsets as well as ID to offset mapping is now maintained solely in intel_rc6 and can be tailored for different platforms and different register layouts as need arises. v2: Address review comments by Jani N - Change residency functions to accept RC6 residency types instead of register ID's - s/intel_rc6_print_rc5_res/intel_rc6_print_residency/ - Remove "const enum" in function arguments - Naming: intel_rc6_* for enum - Use INTEL_RC6_RES_MAX and other minor changes Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Suggested-by: Jani Nikula <jani.nikula@linux.intel.com> Reported-by: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 27 +++------ drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 12 ++-- drivers/gpu/drm/i915/gt/intel_rc6.c | 55 +++++++++++-------- drivers/gpu/drm/i915/gt/intel_rc6.h | 8 ++- drivers/gpu/drm/i915/gt/intel_rc6_types.h | 15 ++++- drivers/gpu/drm/i915/gt/selftest_rc6.c | 6 +- drivers/gpu/drm/i915/i915_pmu.c | 6 +- 7 files changed, 70 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c index 40d0a3be42acf..235d593cfaeba 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c @@ -83,19 +83,6 @@ static int fw_domains_show(struct seq_file *m, void *data) } DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(fw_domains); -static void print_rc6_res(struct seq_file *m, - const char *title, - const i915_reg_t reg) -{ - struct intel_gt *gt = m->private; - intel_wakeref_t wakeref; - - with_intel_runtime_pm(gt->uncore->rpm, wakeref) - seq_printf(m, "%s %u (%llu us)\n", title, - intel_uncore_read(gt->uncore, reg), - intel_rc6_residency_us(>->rc6, reg)); -} - static int vlv_drpc(struct seq_file *m) { struct intel_gt *gt = m->private; @@ -115,8 +102,8 @@ static int vlv_drpc(struct seq_file *m) seq_printf(m, "Media Power Well: %s\n", (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); - print_rc6_res(m, "Render RC6 residency since boot:", GEN6_GT_GFX_RC6); - print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6); + intel_rc6_print_residency(m, "Render RC6 residency since boot:", INTEL_RC6_RES_RC6); + intel_rc6_print_residency(m, "Media RC6 residency since boot:", INTEL_RC6_RES_VLV_MEDIA); return fw_domains_show(m, NULL); } @@ -192,11 +179,11 @@ static int gen6_drpc(struct seq_file *m) } /* Not exactly sure what this is */ - print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:", - GEN6_GT_GFX_RC6_LOCKED); - print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6); - print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p); - print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp); + intel_rc6_print_residency(m, "RC6 \"Locked to RPn\" residency since boot:", + INTEL_RC6_RES_RC6_LOCKED); + intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6); + intel_rc6_print_residency(m, "RC6+ residency since boot:", INTEL_RC6_RES_RC6p); + intel_rc6_print_residency(m, "RC6++ residency since boot:", INTEL_RC6_RES_RC6pp); if (GRAPHICS_VER(i915) <= 7) { seq_printf(m, "RC6 voltage: %dmV\n", diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c index 9041609523697..19a60000e052c 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c @@ -93,13 +93,13 @@ sysfs_gt_attribute_r_func(struct device *dev, struct device_attribute *attr, sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX) #ifdef CONFIG_PM -static u32 get_residency(struct intel_gt *gt, i915_reg_t reg) +static u32 get_residency(struct intel_gt *gt, enum intel_rc6_res_type id) { intel_wakeref_t wakeref; u64 res = 0; with_intel_runtime_pm(gt->uncore->rpm, wakeref) - res = intel_rc6_residency_us(>->rc6, reg); + res = intel_rc6_residency_us(>->rc6, id); return DIV_ROUND_CLOSEST_ULL(res, 1000); } @@ -123,7 +123,7 @@ static ssize_t rc6_enable_show(struct device *dev, static u32 __rc6_residency_ms_show(struct intel_gt *gt) { - return get_residency(gt, GEN6_GT_GFX_RC6); + return get_residency(gt, INTEL_RC6_RES_RC6); } static ssize_t rc6_residency_ms_show(struct device *dev, @@ -138,7 +138,7 @@ static ssize_t rc6_residency_ms_show(struct device *dev, static u32 __rc6p_residency_ms_show(struct intel_gt *gt) { - return get_residency(gt, GEN6_GT_GFX_RC6p); + return get_residency(gt, INTEL_RC6_RES_RC6p); } static ssize_t rc6p_residency_ms_show(struct device *dev, @@ -153,7 +153,7 @@ static ssize_t rc6p_residency_ms_show(struct device *dev, static u32 __rc6pp_residency_ms_show(struct intel_gt *gt) { - return get_residency(gt, GEN6_GT_GFX_RC6pp); + return get_residency(gt, INTEL_RC6_RES_RC6pp); } static ssize_t rc6pp_residency_ms_show(struct device *dev, @@ -168,7 +168,7 @@ static ssize_t rc6pp_residency_ms_show(struct device *dev, static u32 __media_rc6_residency_ms_show(struct intel_gt *gt) { - return get_residency(gt, VLV_GT_MEDIA_RC6); + return get_residency(gt, INTEL_RC6_RES_VLV_MEDIA); } static ssize_t media_rc6_residency_ms_show(struct device *dev, diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index f8d0523f4c18e..6db4e60d5fba5 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -551,6 +551,14 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6) intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); } +static void rc6_res_reg_init(struct intel_rc6 *rc6) +{ + rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED; + rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6; + rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p; + rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp; +} + void intel_rc6_init(struct intel_rc6 *rc6) { struct drm_i915_private *i915 = rc6_to_i915(rc6); @@ -562,6 +570,8 @@ void intel_rc6_init(struct intel_rc6 *rc6) if (!rc6_supported(rc6)) return; + rc6_res_reg_init(rc6); + if (IS_CHERRYVIEW(i915)) err = chv_rc6_init(rc6); else if (IS_VALLEYVIEW(i915)) @@ -736,31 +746,19 @@ static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg) return lower | (u64)upper << 8; } -u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg) +u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id) { struct drm_i915_private *i915 = rc6_to_i915(rc6); struct intel_uncore *uncore = rc6_to_uncore(rc6); u64 time_hw, prev_hw, overflow_hw; + i915_reg_t reg = rc6->res_reg[id]; unsigned int fw_domains; unsigned long flags; - unsigned int i; u32 mul, div; if (!rc6->supported) return 0; - /* - * Store previous hw counter values for counter wrap-around handling. - * - * There are only four interesting registers and they live next to each - * other so we can use the relative address, compared to the smallest - * one as the index into driver storage. - */ - i = (i915_mmio_reg_offset(reg) - - i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32); - if (drm_WARN_ON_ONCE(&i915->drm, i >= ARRAY_SIZE(rc6->cur_residency))) - return 0; - fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ); spin_lock_irqsave(&uncore->lock, flags); @@ -789,11 +787,11 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg) /* * Counter wrap handling. * - * But relying on a sufficient frequency of queries otherwise counters - * can still wrap. + * Store previous hw counter values for counter wrap-around handling. But + * relying on a sufficient frequency of queries otherwise counters can still wrap. */ - prev_hw = rc6->prev_hw_residency[i]; - rc6->prev_hw_residency[i] = time_hw; + prev_hw = rc6->prev_hw_residency[id]; + rc6->prev_hw_residency[id] = time_hw; /* RC6 delta from last sample. */ if (time_hw >= prev_hw) @@ -802,8 +800,8 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg) time_hw += overflow_hw - prev_hw; /* Add delta to RC6 extended raw driver copy. */ - time_hw += rc6->cur_residency[i]; - rc6->cur_residency[i] = time_hw; + time_hw += rc6->cur_residency[id]; + rc6->cur_residency[id] = time_hw; intel_uncore_forcewake_put__locked(uncore, fw_domains); spin_unlock_irqrestore(&uncore->lock, flags); @@ -811,9 +809,22 @@ u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg) return mul_u64_u32_div(time_hw, mul, div); } -u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg) +u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id) +{ + return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, id), 1000); +} + +void intel_rc6_print_residency(struct seq_file *m, const char *title, + enum intel_rc6_res_type id) { - return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, reg), 1000); + struct intel_gt *gt = m->private; + i915_reg_t reg = gt->rc6.res_reg[id]; + intel_wakeref_t wakeref; + + with_intel_runtime_pm(gt->uncore->rpm, wakeref) + seq_printf(m, "%s %u (%llu us)\n", title, + intel_uncore_read(gt->uncore, reg), + intel_rc6_residency_us(>->rc6, id)); } #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h b/drivers/gpu/drm/i915/gt/intel_rc6.h index b6fea71afc223..3105bc72c096b 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.h +++ b/drivers/gpu/drm/i915/gt/intel_rc6.h @@ -6,7 +6,7 @@ #ifndef INTEL_RC6_H #define INTEL_RC6_H -#include "i915_reg_defs.h" +#include "intel_rc6_types.h" struct intel_engine_cs; struct intel_rc6; @@ -21,7 +21,9 @@ void intel_rc6_sanitize(struct intel_rc6 *rc6); void intel_rc6_enable(struct intel_rc6 *rc6); void intel_rc6_disable(struct intel_rc6 *rc6); -u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, i915_reg_t reg); -u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg); +u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id); +u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id); +void intel_rc6_print_residency(struct seq_file *m, const char *title, + enum intel_rc6_res_type id); #endif /* INTEL_RC6_H */ diff --git a/drivers/gpu/drm/i915/gt/intel_rc6_types.h b/drivers/gpu/drm/i915/gt/intel_rc6_types.h index e747492b2f46e..fa23c4dce00b4 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6_types.h +++ b/drivers/gpu/drm/i915/gt/intel_rc6_types.h @@ -13,9 +13,20 @@ struct drm_i915_gem_object; +/* RC6 residency types */ +enum intel_rc6_res_type { + INTEL_RC6_RES_RC6_LOCKED, + INTEL_RC6_RES_RC6, + INTEL_RC6_RES_RC6p, + INTEL_RC6_RES_RC6pp, + INTEL_RC6_RES_MAX, + INTEL_RC6_RES_VLV_MEDIA = INTEL_RC6_RES_RC6p, +}; + struct intel_rc6 { - u64 prev_hw_residency[4]; - u64 cur_residency[4]; + i915_reg_t res_reg[INTEL_RC6_RES_MAX]; + u64 prev_hw_residency[INTEL_RC6_RES_MAX]; + u64 cur_residency[INTEL_RC6_RES_MAX]; u32 ctl_enable; diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c index 8c70b7e120749..2ceeadecc639c 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c @@ -19,11 +19,11 @@ static u64 rc6_residency(struct intel_rc6 *rc6) /* XXX VLV_GT_MEDIA_RC6? */ - result = intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6); + result = intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6); if (HAS_RC6p(rc6_to_i915(rc6))) - result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6p); + result += intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6p); if (HAS_RC6pp(rc6_to_i915(rc6))) - result += intel_rc6_residency_ns(rc6, GEN6_GT_GFX_RC6pp); + result += intel_rc6_residency_ns(rc6, INTEL_RC6_RES_RC6pp); return result; } diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 67140a87182f8..52531ab28c5f5 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -148,13 +148,13 @@ static u64 __get_rc6(struct intel_gt *gt) struct drm_i915_private *i915 = gt->i915; u64 val; - val = intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6); + val = intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6); if (HAS_RC6p(i915)) - val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6p); + val += intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6p); if (HAS_RC6pp(i915)) - val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6pp); + val += intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6pp); return val; } -- 2.38.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/gt: Use RC6 residency types as arguments to residency functions 2022-10-19 5:20 ` Ashutosh Dixit @ 2022-10-19 7:51 ` Jani Nikula -1 siblings, 0 replies; 26+ messages in thread From: Jani Nikula @ 2022-10-19 7:51 UTC (permalink / raw) To: Ashutosh Dixit, intel-gfx; +Cc: dri-devel, Rodrigo Vivi On Tue, 18 Oct 2022, Ashutosh Dixit <ashutosh.dixit@intel.com> wrote: > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h b/drivers/gpu/drm/i915/gt/intel_rc6.h > index b6fea71afc223..3105bc72c096b 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rc6.h > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.h > @@ -6,7 +6,7 @@ > #ifndef INTEL_RC6_H > #define INTEL_RC6_H > > -#include "i915_reg_defs.h" > +#include "intel_rc6_types.h" > > struct intel_engine_cs; > struct intel_rc6; > @@ -21,7 +21,9 @@ void intel_rc6_sanitize(struct intel_rc6 *rc6); > void intel_rc6_enable(struct intel_rc6 *rc6); > void intel_rc6_disable(struct intel_rc6 *rc6); > > -u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, i915_reg_t reg); > -u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg); > +u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id); > +u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id); > +void intel_rc6_print_residency(struct seq_file *m, const char *title, > + enum intel_rc6_res_type id); > > #endif /* INTEL_RC6_H */ Please apply this on top to avoid includes from includes. diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h b/drivers/gpu/drm/i915/gt/intel_rc6.h index 3105bc72c096..456fa668a276 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.h +++ b/drivers/gpu/drm/i915/gt/intel_rc6.h @@ -6,10 +6,11 @@ #ifndef INTEL_RC6_H #define INTEL_RC6_H -#include "intel_rc6_types.h" +#include <linux/types.h> -struct intel_engine_cs; +enum intel_rc6_res_type; struct intel_rc6; +struct seq_file; void intel_rc6_init(struct intel_rc6 *rc6); void intel_rc6_fini(struct intel_rc6 *rc6); -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 3/4] drm/i915/gt: Use RC6 residency types as arguments to residency functions @ 2022-10-19 7:51 ` Jani Nikula 0 siblings, 0 replies; 26+ messages in thread From: Jani Nikula @ 2022-10-19 7:51 UTC (permalink / raw) To: Ashutosh Dixit, intel-gfx Cc: Anshuman Gupta, Badal Nilawar, dri-devel, Rodrigo Vivi On Tue, 18 Oct 2022, Ashutosh Dixit <ashutosh.dixit@intel.com> wrote: > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h b/drivers/gpu/drm/i915/gt/intel_rc6.h > index b6fea71afc223..3105bc72c096b 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rc6.h > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.h > @@ -6,7 +6,7 @@ > #ifndef INTEL_RC6_H > #define INTEL_RC6_H > > -#include "i915_reg_defs.h" > +#include "intel_rc6_types.h" > > struct intel_engine_cs; > struct intel_rc6; > @@ -21,7 +21,9 @@ void intel_rc6_sanitize(struct intel_rc6 *rc6); > void intel_rc6_enable(struct intel_rc6 *rc6); > void intel_rc6_disable(struct intel_rc6 *rc6); > > -u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, i915_reg_t reg); > -u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg); > +u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id); > +u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id); > +void intel_rc6_print_residency(struct seq_file *m, const char *title, > + enum intel_rc6_res_type id); > > #endif /* INTEL_RC6_H */ Please apply this on top to avoid includes from includes. diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h b/drivers/gpu/drm/i915/gt/intel_rc6.h index 3105bc72c096..456fa668a276 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.h +++ b/drivers/gpu/drm/i915/gt/intel_rc6.h @@ -6,10 +6,11 @@ #ifndef INTEL_RC6_H #define INTEL_RC6_H -#include "intel_rc6_types.h" +#include <linux/types.h> -struct intel_engine_cs; +enum intel_rc6_res_type; struct intel_rc6; +struct seq_file; void intel_rc6_init(struct intel_rc6 *rc6); void intel_rc6_fini(struct intel_rc6 *rc6); -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/gt: Use RC6 residency types as arguments to residency functions 2022-10-19 7:51 ` Jani Nikula @ 2022-10-19 23:40 ` Dixit, Ashutosh -1 siblings, 0 replies; 26+ messages in thread From: Dixit, Ashutosh @ 2022-10-19 23:40 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, dri-devel, Rodrigo Vivi On Wed, 19 Oct 2022 00:51:45 -0700, Jani Nikula wrote: > > On Tue, 18 Oct 2022, Ashutosh Dixit <ashutosh.dixit@intel.com> wrote: > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h b/drivers/gpu/drm/i915/gt/intel_rc6.h > > index b6fea71afc223..3105bc72c096b 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_rc6.h > > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.h > > @@ -6,7 +6,7 @@ > > #ifndef INTEL_RC6_H > > #define INTEL_RC6_H > > > > -#include "i915_reg_defs.h" > > +#include "intel_rc6_types.h" > > > > struct intel_engine_cs; > > struct intel_rc6; > > @@ -21,7 +21,9 @@ void intel_rc6_sanitize(struct intel_rc6 *rc6); > > void intel_rc6_enable(struct intel_rc6 *rc6); > > void intel_rc6_disable(struct intel_rc6 *rc6); > > > > -u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, i915_reg_t reg); > > -u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg); > > +u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id); > > +u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id); > > +void intel_rc6_print_residency(struct seq_file *m, const char *title, > > + enum intel_rc6_res_type id); > > > > #endif /* INTEL_RC6_H */ > > Please apply this on top to avoid includes from includes. > > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h b/drivers/gpu/drm/i915/gt/intel_rc6.h > index 3105bc72c096..456fa668a276 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rc6.h > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.h > @@ -6,10 +6,11 @@ > #ifndef INTEL_RC6_H > #define INTEL_RC6_H > > -#include "intel_rc6_types.h" > +#include <linux/types.h> > > -struct intel_engine_cs; > +enum intel_rc6_res_type; > struct intel_rc6; > +struct seq_file; > > void intel_rc6_init(struct intel_rc6 *rc6); > void intel_rc6_fini(struct intel_rc6 *rc6); Thanks, done in series version v8. Ashutosh ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 3/4] drm/i915/gt: Use RC6 residency types as arguments to residency functions @ 2022-10-19 23:40 ` Dixit, Ashutosh 0 siblings, 0 replies; 26+ messages in thread From: Dixit, Ashutosh @ 2022-10-19 23:40 UTC (permalink / raw) To: Jani Nikula Cc: Anshuman Gupta, intel-gfx, Badal Nilawar, dri-devel, Rodrigo Vivi On Wed, 19 Oct 2022 00:51:45 -0700, Jani Nikula wrote: > > On Tue, 18 Oct 2022, Ashutosh Dixit <ashutosh.dixit@intel.com> wrote: > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h b/drivers/gpu/drm/i915/gt/intel_rc6.h > > index b6fea71afc223..3105bc72c096b 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_rc6.h > > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.h > > @@ -6,7 +6,7 @@ > > #ifndef INTEL_RC6_H > > #define INTEL_RC6_H > > > > -#include "i915_reg_defs.h" > > +#include "intel_rc6_types.h" > > > > struct intel_engine_cs; > > struct intel_rc6; > > @@ -21,7 +21,9 @@ void intel_rc6_sanitize(struct intel_rc6 *rc6); > > void intel_rc6_enable(struct intel_rc6 *rc6); > > void intel_rc6_disable(struct intel_rc6 *rc6); > > > > -u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, i915_reg_t reg); > > -u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg); > > +u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id); > > +u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id); > > +void intel_rc6_print_residency(struct seq_file *m, const char *title, > > + enum intel_rc6_res_type id); > > > > #endif /* INTEL_RC6_H */ > > Please apply this on top to avoid includes from includes. > > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h b/drivers/gpu/drm/i915/gt/intel_rc6.h > index 3105bc72c096..456fa668a276 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rc6.h > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.h > @@ -6,10 +6,11 @@ > #ifndef INTEL_RC6_H > #define INTEL_RC6_H > > -#include "intel_rc6_types.h" > +#include <linux/types.h> > > -struct intel_engine_cs; > +enum intel_rc6_res_type; > struct intel_rc6; > +struct seq_file; > > void intel_rc6_init(struct intel_rc6 *rc6); > void intel_rc6_fini(struct intel_rc6 *rc6); Thanks, done in series version v8. Ashutosh ^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915/mtl: C6 residency and C state type for MTL SAMedia 2022-10-19 5:20 ` Ashutosh Dixit @ 2022-10-19 5:20 ` Ashutosh Dixit -1 siblings, 0 replies; 26+ messages in thread From: Ashutosh Dixit @ 2022-10-19 5:20 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel, Rodrigo Vivi From: Badal Nilawar <badal.nilawar@intel.com> Add support for C6 residency and C state type for MTL SAMedia. Also add mtl_drpc. v2: Fixed review comments (Ashutosh) v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R) Remove MTL_CC_SHIFT (Ashutosh) Adapt to RC6 residency register code refactor (Jani N) v4: Move MTL branch to top in drpc_show Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 60 ++++++++++++++++++- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 ++ drivers/gpu/drm/i915/gt/intel_rc6.c | 17 ++++-- 3 files changed, 77 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c index 235d593cfaeba..c88d8ec62b692 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c @@ -256,6 +256,62 @@ static int ilk_drpc(struct seq_file *m) return 0; } +static int mtl_drpc(struct seq_file *m) +{ + struct intel_gt *gt = m->private; + struct intel_uncore *uncore = gt->uncore; + u32 gt_core_status, rcctl1, global_forcewake; + u32 mtl_powergate_enable = 0, mtl_powergate_status = 0; + + gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1); + + global_forcewake = intel_uncore_read(uncore, FORCEWAKE_GT_GEN9); + + rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); + mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE); + mtl_powergate_status = intel_uncore_read(uncore, + GEN9_PWRGT_DOMAIN_STATUS); + + seq_printf(m, "RC6 Enabled: %s\n", + str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); + if (gt->type == GT_MEDIA) { + seq_printf(m, "Media Well Gating Enabled: %s\n", + str_yes_no(mtl_powergate_enable & GEN9_MEDIA_PG_ENABLE)); + } else { + seq_printf(m, "Render Well Gating Enabled: %s\n", + str_yes_no(mtl_powergate_enable & GEN9_RENDER_PG_ENABLE)); + } + + seq_puts(m, "Current RC state: "); + switch (REG_FIELD_GET(MTL_CC_MASK, gt_core_status)) { + case MTL_CC0: + seq_puts(m, "on\n"); + break; + case MTL_CC6: + seq_puts(m, "RC6\n"); + break; + default: + seq_puts(m, "Unknown\n"); + break; + } + + if (gt->type == GT_MEDIA) + seq_printf(m, "Media Power Well: %s\n", + (mtl_powergate_status & + GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); + else + seq_printf(m, "Render Power Well: %s\n", + (mtl_powergate_status & + GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); + + /* Works for both render and media gt's */ + intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6); + + seq_printf(m, "Global Forcewake Requests: 0x%x\n", global_forcewake); + + return fw_domains_show(m, NULL); +} + static int drpc_show(struct seq_file *m, void *unused) { struct intel_gt *gt = m->private; @@ -264,7 +320,9 @@ static int drpc_show(struct seq_file *m, void *unused) int err = -ENODEV; with_intel_runtime_pm(gt->uncore->rpm, wakeref) { - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) + err = mtl_drpc(m); + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) err = vlv_drpc(m); else if (GRAPHICS_VER(i915) >= 6) err = gen6_drpc(m); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index b4b1b54ad738f..9f168867eb8ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -24,6 +24,9 @@ /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */ #define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60) #define MTL_CAGF_MASK REG_GENMASK(8, 0) +#define MTL_CC0 0x0 +#define MTL_CC6 0x3 +#define MTL_CC_MASK REG_GENMASK(12, 9) /* RPM unit config (Gen8+) */ #define RPM_CONFIG0 _MMIO(0xd00) @@ -1516,6 +1519,8 @@ #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8) #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc) +#define MTL_MEDIA_MC6 _MMIO(0x138048) + #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c) #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 6db4e60d5fba5..2ee4051e4d961 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -553,10 +553,19 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6) static void rc6_res_reg_init(struct intel_rc6 *rc6) { - rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED; - rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6; - rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p; - rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp; + memset(rc6->res_reg, INVALID_MMIO_REG.reg, sizeof(rc6->res_reg)); + + switch (rc6_to_gt(rc6)->type) { + case GT_MEDIA: + rc6->res_reg[INTEL_RC6_RES_RC6] = MTL_MEDIA_MC6; + break; + default: + rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED; + rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6; + rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p; + rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp; + break; + } } void intel_rc6_init(struct intel_rc6 *rc6) -- 2.38.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 4/4] drm/i915/mtl: C6 residency and C state type for MTL SAMedia @ 2022-10-19 5:20 ` Ashutosh Dixit 0 siblings, 0 replies; 26+ messages in thread From: Ashutosh Dixit @ 2022-10-19 5:20 UTC (permalink / raw) To: intel-gfx; +Cc: Anshuman Gupta, Badal Nilawar, dri-devel, Rodrigo Vivi From: Badal Nilawar <badal.nilawar@intel.com> Add support for C6 residency and C state type for MTL SAMedia. Also add mtl_drpc. v2: Fixed review comments (Ashutosh) v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R) Remove MTL_CC_SHIFT (Ashutosh) Adapt to RC6 residency register code refactor (Jani N) v4: Move MTL branch to top in drpc_show Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 60 ++++++++++++++++++- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 ++ drivers/gpu/drm/i915/gt/intel_rc6.c | 17 ++++-- 3 files changed, 77 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c index 235d593cfaeba..c88d8ec62b692 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c @@ -256,6 +256,62 @@ static int ilk_drpc(struct seq_file *m) return 0; } +static int mtl_drpc(struct seq_file *m) +{ + struct intel_gt *gt = m->private; + struct intel_uncore *uncore = gt->uncore; + u32 gt_core_status, rcctl1, global_forcewake; + u32 mtl_powergate_enable = 0, mtl_powergate_status = 0; + + gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1); + + global_forcewake = intel_uncore_read(uncore, FORCEWAKE_GT_GEN9); + + rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); + mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE); + mtl_powergate_status = intel_uncore_read(uncore, + GEN9_PWRGT_DOMAIN_STATUS); + + seq_printf(m, "RC6 Enabled: %s\n", + str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); + if (gt->type == GT_MEDIA) { + seq_printf(m, "Media Well Gating Enabled: %s\n", + str_yes_no(mtl_powergate_enable & GEN9_MEDIA_PG_ENABLE)); + } else { + seq_printf(m, "Render Well Gating Enabled: %s\n", + str_yes_no(mtl_powergate_enable & GEN9_RENDER_PG_ENABLE)); + } + + seq_puts(m, "Current RC state: "); + switch (REG_FIELD_GET(MTL_CC_MASK, gt_core_status)) { + case MTL_CC0: + seq_puts(m, "on\n"); + break; + case MTL_CC6: + seq_puts(m, "RC6\n"); + break; + default: + seq_puts(m, "Unknown\n"); + break; + } + + if (gt->type == GT_MEDIA) + seq_printf(m, "Media Power Well: %s\n", + (mtl_powergate_status & + GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); + else + seq_printf(m, "Render Power Well: %s\n", + (mtl_powergate_status & + GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); + + /* Works for both render and media gt's */ + intel_rc6_print_residency(m, "RC6 residency since boot:", INTEL_RC6_RES_RC6); + + seq_printf(m, "Global Forcewake Requests: 0x%x\n", global_forcewake); + + return fw_domains_show(m, NULL); +} + static int drpc_show(struct seq_file *m, void *unused) { struct intel_gt *gt = m->private; @@ -264,7 +320,9 @@ static int drpc_show(struct seq_file *m, void *unused) int err = -ENODEV; with_intel_runtime_pm(gt->uncore->rpm, wakeref) { - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) + err = mtl_drpc(m); + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) err = vlv_drpc(m); else if (GRAPHICS_VER(i915) >= 6) err = gen6_drpc(m); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index b4b1b54ad738f..9f168867eb8ae 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -24,6 +24,9 @@ /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */ #define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60) #define MTL_CAGF_MASK REG_GENMASK(8, 0) +#define MTL_CC0 0x0 +#define MTL_CC6 0x3 +#define MTL_CC_MASK REG_GENMASK(12, 9) /* RPM unit config (Gen8+) */ #define RPM_CONFIG0 _MMIO(0xd00) @@ -1516,6 +1519,8 @@ #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8) #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc) +#define MTL_MEDIA_MC6 _MMIO(0x138048) + #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c) #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 6db4e60d5fba5..2ee4051e4d961 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -553,10 +553,19 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6) static void rc6_res_reg_init(struct intel_rc6 *rc6) { - rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED; - rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6; - rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p; - rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp; + memset(rc6->res_reg, INVALID_MMIO_REG.reg, sizeof(rc6->res_reg)); + + switch (rc6_to_gt(rc6)->type) { + case GT_MEDIA: + rc6->res_reg[INTEL_RC6_RES_RC6] = MTL_MEDIA_MC6; + break; + default: + rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED; + rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6; + rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p; + rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp; + break; + } } void intel_rc6_init(struct intel_rc6 *rc6) -- 2.38.0 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: CAGF and RC6 changes for MTL (rev6) 2022-10-19 5:20 ` Ashutosh Dixit ` (4 preceding siblings ...) (?) @ 2022-10-19 5:52 ` Patchwork -1 siblings, 0 replies; 26+ messages in thread From: Patchwork @ 2022-10-19 5:52 UTC (permalink / raw) To: Badal Nilawar; +Cc: intel-gfx == Series Details == Series: i915: CAGF and RC6 changes for MTL (rev6) URL : https://patchwork.freedesktop.org/series/108156/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. ^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for i915: CAGF and RC6 changes for MTL (rev6) 2022-10-19 5:20 ` Ashutosh Dixit ` (5 preceding siblings ...) (?) @ 2022-10-19 6:08 ` Patchwork -1 siblings, 0 replies; 26+ messages in thread From: Patchwork @ 2022-10-19 6:08 UTC (permalink / raw) To: Badal Nilawar; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 6110 bytes --] == Series Details == Series: i915: CAGF and RC6 changes for MTL (rev6) URL : https://patchwork.freedesktop.org/series/108156/ State : success == Summary == CI Bug Log - changes from CI_DRM_12258 -> Patchwork_108156v6 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/index.html Participating hosts (39 -> 39) ------------------------------ Additional (1): fi-hsw-4770 Missing (1): fi-adl-ddr5 Known issues ------------ Here are the changes found in Patchwork_108156v6 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_gttfill@basic: - fi-pnv-d510: [PASS][1] -> [FAIL][2] ([i915#7229]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/fi-pnv-d510/igt@gem_exec_gttfill@basic.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-pnv-d510/igt@gem_exec_gttfill@basic.html * igt@gem_lmem_swapping@basic: - fi-apl-guc: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-apl-guc/igt@gem_lmem_swapping@basic.html * igt@gem_tiled_blits@basic: - fi-pnv-d510: [PASS][4] -> [SKIP][5] ([fdo#109271]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/fi-pnv-d510/igt@gem_tiled_blits@basic.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-pnv-d510/igt@gem_tiled_blits@basic.html * igt@i915_pm_backlight@basic-brightness: - fi-hsw-4770: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#3012]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-hsw-4770/igt@i915_pm_backlight@basic-brightness.html * igt@i915_pm_rpm@module-reload: - fi-hsw-4770: NOTRUN -> [INCOMPLETE][7] ([i915#7221]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-hsw-4770/igt@i915_pm_rpm@module-reload.html * igt@i915_selftest@live@sanitycheck: - fi-apl-guc: NOTRUN -> [INCOMPLETE][8] ([i915#7222]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-apl-guc/igt@i915_selftest@live@sanitycheck.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - fi-hsw-4770: NOTRUN -> [SKIP][9] ([fdo#109271]) +9 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-hsw-4770/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html * igt@kms_chamelium@dp-crc-fast: - fi-hsw-4770: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +7 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-hsw-4770/igt@kms_chamelium@dp-crc-fast.html * igt@kms_psr@sprite_plane_onoff: - fi-hsw-4770: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#1072]) +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html * igt@runner@aborted: - fi-hsw-4770: NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#4312] / [i915#5594]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-hsw-4770/igt@runner@aborted.html - fi-apl-guc: NOTRUN -> [FAIL][13] ([fdo#109271] / [i915#4312]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-apl-guc/igt@runner@aborted.html #### Possible fixes #### * igt@core_hotunplug@unbind-rebind: - fi-apl-guc: [INCOMPLETE][14] ([i915#7073]) -> [PASS][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/fi-apl-guc/igt@core_hotunplug@unbind-rebind.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-apl-guc/igt@core_hotunplug@unbind-rebind.html #### Warnings #### * igt@i915_suspend@basic-s3-without-i915: - fi-bdw-gvtdvm: [FAIL][16] ([fdo#103375]) -> [INCOMPLETE][17] ([i915#146]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/fi-bdw-gvtdvm/igt@i915_suspend@basic-s3-without-i915.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/fi-bdw-gvtdvm/igt@i915_suspend@basic-s3-without-i915.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537 [i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594 [i915#7073]: https://gitlab.freedesktop.org/drm/intel/issues/7073 [i915#7221]: https://gitlab.freedesktop.org/drm/intel/issues/7221 [i915#7222]: https://gitlab.freedesktop.org/drm/intel/issues/7222 [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229 Build changes ------------- * Linux: CI_DRM_12258 -> Patchwork_108156v6 CI-20190529: 20190529 CI_DRM_12258: 46aaaf749a4300985a8415b327a96a2bffb63018 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7019: fdbafce2b74e84739bb1d81223ae6f01fb442980 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_108156v6: 46aaaf749a4300985a8415b327a96a2bffb63018 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 2a1c7fe37394 drm/i915/mtl: C6 residency and C state type for MTL SAMedia 40c279ce31e5 drm/i915/gt: Use RC6 residency types as arguments to residency functions b556bf45a29e drm/i915/mtl: Modify CAGF functions for MTL 6f049dbc25af drm/i915: Use GEN12_RPSTAT register for GT freq == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/index.html [-- Attachment #2: Type: text/html, Size: 7502 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for i915: CAGF and RC6 changes for MTL (rev7) 2022-10-19 5:20 ` Ashutosh Dixit ` (6 preceding siblings ...) (?) @ 2022-10-19 12:11 ` Patchwork -1 siblings, 0 replies; 26+ messages in thread From: Patchwork @ 2022-10-19 12:11 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: i915: CAGF and RC6 changes for MTL (rev7) URL : https://patchwork.freedesktop.org/series/108156/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/108156/revisions/7/mbox/ not applied Applying: drm/i915: Use GEN12_RPSTAT register for GT freq Applying: drm/i915/mtl: Modify CAGF functions for MTL Applying: drm/i915/gt: Use RC6 residency types as arguments to residency functions Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/gt/intel_rc6.h Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/gt/intel_rc6.h CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_rc6.h error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0003 drm/i915/gt: Use RC6 residency types as arguments to residency functions When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". ^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: CAGF and RC6 changes for MTL (rev6) 2022-10-19 5:20 ` Ashutosh Dixit ` (7 preceding siblings ...) (?) @ 2022-10-19 13:43 ` Patchwork -1 siblings, 0 replies; 26+ messages in thread From: Patchwork @ 2022-10-19 13:43 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 30697 bytes --] == Series Details == Series: i915: CAGF and RC6 changes for MTL (rev6) URL : https://patchwork.freedesktop.org/series/108156/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12258_full -> Patchwork_108156v6_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_108156v6_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_108156v6_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_108156v6_full: ### IGT changes ### #### Possible regressions #### * igt@kms_plane_lowres@tiling-none@pipe-c-hdmi-a-2: - shard-glk: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-glk9/igt@kms_plane_lowres@tiling-none@pipe-c-hdmi-a-2.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-glk6/igt@kms_plane_lowres@tiling-none@pipe-c-hdmi-a-2.html * igt@perf_pmu@interrupts: - shard-skl: [PASS][3] -> [FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-skl1/igt@perf_pmu@interrupts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl4/igt@perf_pmu@interrupts.html #### Warnings #### * igt@gem_workarounds@suspend-resume-context: - shard-apl: [INCOMPLETE][5] ([i915#7231]) -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-apl1/igt@gem_workarounds@suspend-resume-context.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-apl2/igt@gem_workarounds@suspend-resume-context.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@gem_ctx_isolation@preservation-s3@rcs0: - {shard-dg1}: NOTRUN -> [INCOMPLETE][7] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-dg1-13/igt@gem_ctx_isolation@preservation-s3@rcs0.html * igt@i915_suspend@basic-s2idle-without-i915: - {shard-rkl}: [PASS][8] -> [INCOMPLETE][9] +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-rkl-1/igt@i915_suspend@basic-s2idle-without-i915.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-rkl-5/igt@i915_suspend@basic-s2idle-without-i915.html Known issues ------------ Here are the changes found in Patchwork_108156v6_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@feature_discovery@display-4x: - shard-iclb: NOTRUN -> [SKIP][10] ([i915#1839]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@feature_discovery@display-4x.html * igt@gem_create@create-massive: - shard-skl: NOTRUN -> [DMESG-WARN][11] ([i915#4991]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl4/igt@gem_create@create-massive.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][12] ([i915#2846]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl7/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-none@vecs0: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-glk5/igt@gem_exec_fair@basic-none@vecs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-glk8/igt@gem_exec_fair@basic-none@vecs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-iclb7/igt@gem_exec_fair@basic-pace@vcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][17] ([i915#2842]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html * igt@gem_exec_params@no-bsd: - shard-iclb: NOTRUN -> [SKIP][18] ([fdo#109283]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@gem_exec_params@no-bsd.html * igt@gem_lmem_swapping@verify-ccs: - shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl6/igt@gem_lmem_swapping@verify-ccs.html * igt@gem_render_copy@yf-tiled-to-vebox-x-tiled: - shard-iclb: NOTRUN -> [SKIP][20] ([i915#768]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@gem_render_copy@yf-tiled-to-vebox-x-tiled.html * igt@gem_softpin@evict-single-offset: - shard-iclb: [PASS][21] -> [FAIL][22] ([i915#4171]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-iclb3/igt@gem_softpin@evict-single-offset.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb7/igt@gem_softpin@evict-single-offset.html * igt@gem_userptr_blits@dmabuf-unsync: - shard-iclb: NOTRUN -> [SKIP][23] ([i915#3297]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@gem_userptr_blits@dmabuf-unsync.html * igt@gem_userptr_blits@probe: - shard-iclb: NOTRUN -> [FAIL][24] ([i915#7224]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@gem_userptr_blits@probe.html * igt@gen7_exec_parse@bitmasks: - shard-iclb: NOTRUN -> [SKIP][25] ([fdo#109289]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@gen7_exec_parse@bitmasks.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-iclb: NOTRUN -> [SKIP][26] ([i915#658]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@i915_selftest@mock@requests: - shard-iclb: [PASS][27] -> [INCOMPLETE][28] ([i915#7267]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-iclb8/igt@i915_selftest@mock@requests.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb8/igt@i915_selftest@mock@requests.html * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc: - shard-skl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3886]) +6 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl6/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc: - shard-iclb: NOTRUN -> [SKIP][30] ([fdo#109278]) +5 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@kms_ccs@pipe-a-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc.html * igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs: - shard-iclb: NOTRUN -> [SKIP][31] ([fdo#109278] / [i915#3886]) +2 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html * igt@kms_chamelium@dp-hpd: - shard-iclb: NOTRUN -> [SKIP][32] ([fdo#109284] / [fdo#111827]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@kms_chamelium@dp-hpd.html * igt@kms_chamelium@dp-hpd-enable-disable-mode: - shard-skl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +6 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl6/igt@kms_chamelium@dp-hpd-enable-disable-mode.html * igt@kms_cursor_legacy@short-busy-flip-before-cursor: - shard-iclb: NOTRUN -> [SKIP][34] ([i915#4103]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@kms_cursor_legacy@short-busy-flip-before-cursor.html * igt@kms_flip@2x-wf_vblank-ts-check: - shard-iclb: NOTRUN -> [SKIP][35] ([fdo#109274]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@kms_flip@2x-wf_vblank-ts-check.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-skl: NOTRUN -> [FAIL][36] ([i915#79]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][37] ([i915#2672]) +5 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][38] ([i915#3555]) +2 similar issues [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling@pipe-a-default-mode.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt: - shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109280]) +2 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt.html * igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-c-edp-1: - shard-skl: NOTRUN -> [FAIL][40] ([i915#4573]) +2 similar issues [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl6/igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-c-edp-1.html * igt@kms_plane_lowres@tiling-none@pipe-a-edp-1: - shard-iclb: NOTRUN -> [SKIP][41] ([i915#3536]) +2 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@kms_plane_lowres@tiling-none@pipe-a-edp-1.html * igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1: - shard-iclb: [PASS][42] -> [SKIP][43] ([i915#5235]) +2 similar issues [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-iclb7/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html * igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b-edp-1: - shard-skl: NOTRUN -> [SKIP][44] ([fdo#109271]) +134 similar issues [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl6/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b-edp-1.html * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-a-edp-1: - shard-skl: [PASS][45] -> [DMESG-WARN][46] ([i915#1982]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-skl9/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-a-edp-1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl10/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-a-edp-1.html * igt@kms_psr2_sf@overlay-plane-update-continuous-sf: - shard-iclb: NOTRUN -> [SKIP][47] ([fdo#111068] / [i915#658]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb: - shard-skl: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#658]) +3 similar issues [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html * igt@kms_psr@cursor_render: - shard-glk: NOTRUN -> [SKIP][49] ([fdo#109271]) +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-glk5/igt@kms_psr@cursor_render.html * igt@kms_psr@psr2_cursor_blt: - shard-iclb: [PASS][50] -> [SKIP][51] ([fdo#109441]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@kms_psr@psr2_cursor_blt.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109441]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_psr@suspend: - shard-skl: NOTRUN -> [INCOMPLETE][53] ([i915#4939]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl1/igt@kms_psr@suspend.html * igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-c: - shard-snb: NOTRUN -> [SKIP][54] ([fdo#109271]) +1 similar issue [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-snb7/igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-c.html * igt@kms_writeback@writeback-pixel-formats: - shard-iclb: NOTRUN -> [SKIP][55] ([i915#2437]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@kms_writeback@writeback-pixel-formats.html * igt@perf@polling-parameterized: - shard-iclb: [PASS][56] -> [FAIL][57] ([i915#5639]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-iclb3/igt@perf@polling-parameterized.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb7/igt@perf@polling-parameterized.html * igt@perf_pmu@rc6-suspend: - shard-skl: NOTRUN -> [INCOMPLETE][58] ([i915#7252]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl4/igt@perf_pmu@rc6-suspend.html * igt@sysfs_clients@split-50: - shard-iclb: NOTRUN -> [SKIP][59] ([i915#2994]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@sysfs_clients@split-50.html #### Possible fixes #### * igt@gem_ctx_persistence@engines-hang@bcs0: - {shard-rkl}: [SKIP][60] ([i915#6252]) -> [PASS][61] [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-rkl-5/igt@gem_ctx_persistence@engines-hang@bcs0.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-rkl-4/igt@gem_ctx_persistence@engines-hang@bcs0.html * igt@gem_eio@hibernate: - shard-snb: [INCOMPLETE][62] -> [PASS][63] [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-snb7/igt@gem_eio@hibernate.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-snb7/igt@gem_eio@hibernate.html * igt@gem_eio@in-flight-suspend: - {shard-rkl}: [FAIL][64] ([fdo#103375]) -> [PASS][65] [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-rkl-4/igt@gem_eio@in-flight-suspend.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-rkl-6/igt@gem_eio@in-flight-suspend.html * igt@gem_exec_balancer@fairslice: - {shard-rkl}: [SKIP][66] ([i915#6259]) -> [PASS][67] [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-rkl-5/igt@gem_exec_balancer@fairslice.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-rkl-2/igt@gem_exec_balancer@fairslice.html * igt@gem_exec_balancer@parallel-bb-first: - shard-iclb: [SKIP][68] ([i915#4525]) -> [PASS][69] [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-iclb7/igt@gem_exec_balancer@parallel-bb-first.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb1/igt@gem_exec_balancer@parallel-bb-first.html * igt@gem_exec_reloc@basic-gtt: - {shard-rkl}: [SKIP][70] ([i915#3281]) -> [PASS][71] +1 similar issue [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-rkl-4/igt@gem_exec_reloc@basic-gtt.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-rkl-5/igt@gem_exec_reloc@basic-gtt.html * igt@gem_exec_whisper@basic-queues-priority-all: - shard-iclb: [INCOMPLETE][72] ([i915#6755]) -> [PASS][73] [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-iclb3/igt@gem_exec_whisper@basic-queues-priority-all.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@gem_exec_whisper@basic-queues-priority-all.html * igt@gem_pwrite@basic-self: - {shard-rkl}: [SKIP][74] ([i915#3282]) -> [PASS][75] +2 similar issues [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-rkl-4/igt@gem_pwrite@basic-self.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-rkl-5/igt@gem_pwrite@basic-self.html * igt@i915_pm_dc@dc9-dpms: - shard-iclb: [SKIP][76] ([i915#4281]) -> [PASS][77] [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb7/igt@i915_pm_dc@dc9-dpms.html * igt@i915_pm_rpm@drm-resources-equal: - {shard-rkl}: [SKIP][78] ([fdo#109308]) -> [PASS][79] [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-rkl-4/igt@i915_pm_rpm@drm-resources-equal.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-rkl-6/igt@i915_pm_rpm@drm-resources-equal.html * igt@i915_selftest@mock@requests: - shard-glk: [INCOMPLETE][80] -> [PASS][81] [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-glk1/igt@i915_selftest@mock@requests.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-glk5/igt@i915_selftest@mock@requests.html * igt@i915_suspend@fence-restore-tiled2untiled: - {shard-rkl}: [INCOMPLETE][82] -> [PASS][83] [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-rkl-5/igt@i915_suspend@fence-restore-tiled2untiled.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-rkl-4/igt@i915_suspend@fence-restore-tiled2untiled.html * igt@kms_big_fb@x-tiled-32bpp-rotate-0: - {shard-rkl}: [SKIP][84] ([i915#1845] / [i915#4098]) -> [PASS][85] +16 similar issues [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-rkl-4/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html * igt@kms_flip@flip-vs-expired-vblank@b-edp1: - shard-skl: [FAIL][86] ([i915#79]) -> [PASS][87] [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html * igt@kms_flip@flip-vs-fences@a-edp1: - shard-skl: [DMESG-WARN][88] ([i915#1982]) -> [PASS][89] [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-skl6/igt@kms_flip@flip-vs-fences@a-edp1.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl9/igt@kms_flip@flip-vs-fences@a-edp1.html * igt@kms_frontbuffer_tracking@fbc-tiling-linear: - {shard-rkl}: [SKIP][90] ([i915#1849] / [i915#4098]) -> [PASS][91] +13 similar issues [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1: - shard-iclb: [SKIP][92] ([i915#5235]) -> [PASS][93] +2 similar issues [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html * igt@kms_psr@cursor_mmap_gtt: - {shard-rkl}: [SKIP][94] ([i915#1072]) -> [PASS][95] +2 similar issues [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-rkl-4/igt@kms_psr@cursor_mmap_gtt.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-rkl-6/igt@kms_psr@cursor_mmap_gtt.html * igt@kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [SKIP][96] ([fdo#109441]) -> [PASS][97] [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-iclb7/igt@kms_psr@psr2_sprite_mmap_gtt.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html * igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-b: - {shard-rkl}: [SKIP][98] ([i915#4098]) -> [PASS][99] [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-rkl-4/igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-b.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-rkl-6/igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-b.html * igt@perf_pmu@busy-double-start@vcs1: - {shard-dg1}: [FAIL][100] ([i915#4349]) -> [PASS][101] [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-dg1-12/igt@perf_pmu@busy-double-start@vcs1.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-dg1-19/igt@perf_pmu@busy-double-start@vcs1.html #### Warnings #### * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb: - shard-iclb: [SKIP][102] ([i915#658]) -> [SKIP][103] ([i915#2920]) +1 similar issue [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html * igt@runner@aborted: - shard-skl: ([FAIL][104], [FAIL][105], [FAIL][106]) ([i915#4312]) -> ([FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111]) ([i915#3002] / [i915#4312] / [i915#6949]) [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-skl4/igt@runner@aborted.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-skl4/igt@runner@aborted.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12258/shard-skl9/igt@runner@aborted.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl9/igt@runner@aborted.html [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl4/igt@runner@aborted.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl10/igt@runner@aborted.html [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl9/igt@runner@aborted.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/shard-skl6/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2532]: https://gitlab.freedesktop.org/drm/intel/issues/2532 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349 [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939 [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248 [i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251 [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252 [i915#6259]: https://gitlab.freedesktop.org/drm/intel/issues/6259 [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#6755]: https://gitlab.freedesktop.org/drm/intel/issues/6755 [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946 [i915#6949]: https://gitlab.freedesktop.org/drm/intel/issues/6949 [i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037 [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118 [i915#7142]: https://gitlab.freedesktop.org/drm/intel/issues/7142 [i915#7224]: https://gitlab.freedesktop.org/drm/intel/issues/7224 [i915#7231]: https://gitlab.freedesktop.org/drm/intel/issues/7231 [i915#7252]: https://gitlab.freedesktop.org/drm/intel/issues/7252 [i915#7267]: https://gitlab.freedesktop.org/drm/intel/issues/7267 [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 Build changes ------------- * Linux: CI_DRM_12258 -> Patchwork_108156v6 CI-20190529: 20190529 CI_DRM_12258: 46aaaf749a4300985a8415b327a96a2bffb63018 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7019: fdbafce2b74e84739bb1d81223ae6f01fb442980 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_108156v6: 46aaaf749a4300985a8415b327a96a2bffb63018 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v6/index.html [-- Attachment #2: Type: text/html, Size: 32318 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2022-10-19 23:43 UTC | newest] Thread overview: 26+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-10-19 5:20 [Intel-gfx] [PATCH 0/4] i915: CAGF and RC6 changes for MTL Ashutosh Dixit 2022-10-19 5:20 ` Ashutosh Dixit 2022-10-19 5:20 ` [Intel-gfx] [PATCH 1/4] drm/i915: Use GEN12_RPSTAT register for GT freq Ashutosh Dixit 2022-10-19 5:20 ` Ashutosh Dixit 2022-10-19 15:06 ` [Intel-gfx] " Rodrigo Vivi 2022-10-19 15:06 ` Rodrigo Vivi 2022-10-19 23:42 ` [Intel-gfx] " Dixit, Ashutosh 2022-10-19 23:42 ` Dixit, Ashutosh 2022-10-19 5:20 ` [Intel-gfx] [PATCH 2/4] drm/i915/mtl: Modify CAGF functions for MTL Ashutosh Dixit 2022-10-19 5:20 ` Ashutosh Dixit 2022-10-19 14:58 ` [Intel-gfx] " Rodrigo Vivi 2022-10-19 14:58 ` Rodrigo Vivi 2022-10-19 23:43 ` [Intel-gfx] " Dixit, Ashutosh 2022-10-19 23:43 ` Dixit, Ashutosh 2022-10-19 5:20 ` [Intel-gfx] [PATCH 3/4] drm/i915/gt: Use RC6 residency types as arguments to residency functions Ashutosh Dixit 2022-10-19 5:20 ` Ashutosh Dixit 2022-10-19 7:51 ` [Intel-gfx] " Jani Nikula 2022-10-19 7:51 ` Jani Nikula 2022-10-19 23:40 ` [Intel-gfx] " Dixit, Ashutosh 2022-10-19 23:40 ` Dixit, Ashutosh 2022-10-19 5:20 ` [Intel-gfx] [PATCH 4/4] drm/i915/mtl: C6 residency and C state type for MTL SAMedia Ashutosh Dixit 2022-10-19 5:20 ` Ashutosh Dixit 2022-10-19 5:52 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: CAGF and RC6 changes for MTL (rev6) Patchwork 2022-10-19 6:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-10-19 12:11 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for i915: CAGF and RC6 changes for MTL (rev7) Patchwork 2022-10-19 13:43 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: CAGF and RC6 changes for MTL (rev6) Patchwork
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