All of lore.kernel.org
 help / color / mirror / Atom feed
From: Conor Dooley <conor@kernel.org>
To: daire.mcnamara@microchip.com
Cc: conor.dooley@microchip.com, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, paul.walmsley@sifive.com,
	palmer@dabbelt.com, aou@eecs.berkeley.edu, lpieralisi@kernel.org,
	kw@linux.com, bhelgaas@google.com,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-pci@vger.kernel.org
Subject: Re: [PATCH v1 1/9] PCI: microchip: Align register, offset, and mask names with hw docs
Date: Wed, 23 Nov 2022 21:09:06 +0000	[thread overview]
Message-ID: <Y36L8nnZw46mm8x/@spud> (raw)
In-Reply-To: <20221116135504.258687-2-daire.mcnamara@microchip.com>

On Wed, Nov 16, 2022 at 01:54:56PM +0000, daire.mcnamara@microchip.com wrote:
> From: Daire McNamara <daire.mcnamara@microchip.com>
> 
> Minor re-organisation so that macros representing registers ascend in
> numerical order and use the same names as their hardware documentation.
> Removed registers not used by the driver.
> 
> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  drivers/pci/controller/pcie-microchip-host.c | 122 +++++++++----------
>  1 file changed, 60 insertions(+), 62 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c
> index 0ebf7015e9af..80e7554722ca 100644
> --- a/drivers/pci/controller/pcie-microchip-host.c
> +++ b/drivers/pci/controller/pcie-microchip-host.c

> @@ -137,7 +78,8 @@
>  #define ISTATUS_LOCAL				0x184
>  #define IMASK_HOST				0x188
>  #define ISTATUS_HOST				0x18c
> -#define MSI_ADDR				0x190
> +#define IMSI_ADDR				0x190
> +#define  MSI_ADDR				0x190

Trivial, trivial comment - I think it would look more intentional as:
#define  MSI_ADDR				IMSI_ADDR

Otherwise this seems grand to me, modulo the SoB issue.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.


WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: daire.mcnamara@microchip.com
Cc: conor.dooley@microchip.com, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, paul.walmsley@sifive.com,
	palmer@dabbelt.com, aou@eecs.berkeley.edu, lpieralisi@kernel.org,
	kw@linux.com, bhelgaas@google.com,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-pci@vger.kernel.org
Subject: Re: [PATCH v1 1/9] PCI: microchip: Align register, offset, and mask names with hw docs
Date: Wed, 23 Nov 2022 21:09:06 +0000	[thread overview]
Message-ID: <Y36L8nnZw46mm8x/@spud> (raw)
In-Reply-To: <20221116135504.258687-2-daire.mcnamara@microchip.com>

On Wed, Nov 16, 2022 at 01:54:56PM +0000, daire.mcnamara@microchip.com wrote:
> From: Daire McNamara <daire.mcnamara@microchip.com>
> 
> Minor re-organisation so that macros representing registers ascend in
> numerical order and use the same names as their hardware documentation.
> Removed registers not used by the driver.
> 
> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  drivers/pci/controller/pcie-microchip-host.c | 122 +++++++++----------
>  1 file changed, 60 insertions(+), 62 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c
> index 0ebf7015e9af..80e7554722ca 100644
> --- a/drivers/pci/controller/pcie-microchip-host.c
> +++ b/drivers/pci/controller/pcie-microchip-host.c

> @@ -137,7 +78,8 @@
>  #define ISTATUS_LOCAL				0x184
>  #define IMASK_HOST				0x188
>  #define ISTATUS_HOST				0x18c
> -#define MSI_ADDR				0x190
> +#define IMSI_ADDR				0x190
> +#define  MSI_ADDR				0x190

Trivial, trivial comment - I think it would look more intentional as:
#define  MSI_ADDR				IMSI_ADDR

Otherwise this seems grand to me, modulo the SoB issue.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2022-11-23 21:09 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-16 13:54 [PATCH v1 0/9] PCI: microchip: Partition address translations daire.mcnamara
2022-11-16 13:54 ` daire.mcnamara
2022-11-16 13:54 ` [PATCH v1 1/9] PCI: microchip: Align register, offset, and mask names with hw docs daire.mcnamara
2022-11-16 13:54   ` daire.mcnamara
2022-11-23 21:09   ` Conor Dooley [this message]
2022-11-23 21:09     ` Conor Dooley
2022-11-16 13:54 ` [PATCH v1 2/9] PCI: microchip: Correct the DED and SEC interrupt bit offsets daire.mcnamara
2022-11-16 13:54   ` daire.mcnamara
2022-11-16 15:19   ` Conor Dooley
2022-11-16 15:19     ` Conor Dooley
2022-11-23 21:28   ` Conor Dooley
2022-11-23 21:28     ` Conor Dooley
2022-11-16 13:54 ` [PATCH v1 3/9] PCI: microchip: Enable event handlers to access bridge and ctrl ptrs daire.mcnamara
2022-11-16 13:54   ` daire.mcnamara
2022-11-23 21:34   ` Conor Dooley
2022-11-23 21:34     ` Conor Dooley
2022-11-16 13:54 ` [PATCH v1 4/9] PCI: microchip: Clean up initialisation of interrupts daire.mcnamara
2022-11-16 13:54   ` daire.mcnamara
2022-11-16 15:17   ` kernel test robot
2022-11-16 15:17     ` kernel test robot
2022-11-17 18:28   ` kernel test robot
2022-11-17 18:28     ` kernel test robot
2022-11-23 21:58   ` Conor Dooley
2022-11-23 21:58     ` Conor Dooley
2022-11-16 13:55 ` [PATCH v1 5/9] PCI: microchip: Gather MSI information from hardware config registers daire.mcnamara
2022-11-16 13:55   ` daire.mcnamara
2022-11-16 16:41   ` Bjorn Helgaas
2022-11-16 16:41     ` Bjorn Helgaas
2022-11-23 22:09   ` Conor Dooley
2022-11-23 22:09     ` Conor Dooley
2022-11-16 13:55 ` [PATCH v1 6/9] PCI: microchip: Re-partition code between probe() and init() daire.mcnamara
2022-11-16 13:55   ` daire.mcnamara
2022-11-23 22:39   ` Conor Dooley
2022-11-23 22:39     ` Conor Dooley
2022-11-16 13:55 ` [PATCH v1 7/9] PCI: microchip: Partition outbound address translation daire.mcnamara
2022-11-16 13:55   ` daire.mcnamara
2022-11-23 22:44   ` Conor Dooley
2022-11-23 22:44     ` Conor Dooley
2022-11-16 13:55 ` [PATCH v1 8/9] PCI: microchip: Partition inbound " daire.mcnamara
2022-11-16 13:55   ` daire.mcnamara
2022-11-16 16:49   ` Bjorn Helgaas
2022-11-16 16:49     ` Bjorn Helgaas
2022-11-16 17:01     ` Conor Dooley
2022-11-16 17:01       ` Conor Dooley
2022-11-16 20:10   ` kernel test robot
2022-11-16 20:10     ` kernel test robot
2022-11-17  6:06   ` kernel test robot
2022-11-17  6:06     ` kernel test robot
2022-11-23 23:05   ` Conor Dooley
2022-11-23 23:05     ` Conor Dooley
2022-11-16 13:55 ` [PATCH v1 9/9] riscv: dts: microchip: add parent ranges and dma-ranges for IKRD v2022.09 daire.mcnamara
2022-11-16 13:55   ` daire.mcnamara
2022-11-23 22:14   ` Conor Dooley
2022-11-23 22:14     ` Conor Dooley
2022-11-23 23:15 ` [PATCH v1 0/9] PCI: microchip: Partition address translations Conor Dooley
2022-11-23 23:15   ` Conor Dooley

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=Y36L8nnZw46mm8x/@spud \
    --to=conor@kernel.org \
    --cc=aou@eecs.berkeley.edu \
    --cc=bhelgaas@google.com \
    --cc=conor.dooley@microchip.com \
    --cc=daire.mcnamara@microchip.com \
    --cc=devicetree@vger.kernel.org \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=kw@linux.com \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=lpieralisi@kernel.org \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=robh+dt@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.