Re: [PATCH v1 0/9] PCI: microchip: Partition address translations

[Conor Dooley <conor@kernel.org>]

Hey Daire,

On Wed, Nov 16, 2022 at 01:54:55PM +0000, daire.mcnamara@microchip.com wrote:
> From: Daire McNamara <daire.mcnamara@microchip.com>
> 
> Microchip PolarFire SoC is a 64-bit device and has DDR starting at
> 0x80000000 and 0x1000000000. Its PCIe rootport is connected to the CPU
> Coreplex via an FPGA fabric. The AXI connections between the Coreplex and
> the fabric are 64-bit and the AXI connections between the fabric and the
> rootport are 32-bit.  For the CPU CorePlex to act as an AXI-Master to the
> PCIe devices and for the PCIe devices to act as bus masters to DDR at these
> base addresses, the fabric can be customised to add/remove offsets for bits
> 38-32 in each direction. These offsets, if present, vary with each
> customer's design.
> 
> To support this variety, the rootport driver must know how much address
> translation (both inbound and outbound) is performed by a particular
> customer design and how much address translation must be provided by the
> rootport.
> 
> This patchset contains a parent/child dma-ranges scheme suggested by Rob
> Herring. It creates an FPGA PCIe parent bus which wraps the PCIe rootport
> and implements a parsing scheme where the root port identifies what address
> translations are performed by the FPGA fabric parent bus, and what
> address translations must be done by the rootport itself.

I've tried this scheme with a bunch of different PCI configurations, and
it holds water, so I am happy with it :) Hopefully Rob is a lot happier
with this version of it too!

It's been long enough that I think you should be good to submit a
cleaned up version, provided Rob's happy on the DT side I think.

Thanks,
Conor.

> See https://lore.kernel.org/linux-pci/20220902142202.2437658-1-daire.mcnamara@microchip.com/
> for the relevant previous patch submission discussion.
> 
> It also re-partitions the probe() and init() functions as suggested by
> Bjorn Helgaas to make them more maintainable as the init() function had
> become too large.
> 
> It also contains some minor fixes and clean-ups that are pre-requisites:
> - to align register, offset, and mask names with the hardware documentation
>   and to have the register definitions appear in the same order as in the
>   hardware documentation;
> - to harvest the MSI information from the hardware configuration register
>   as these depend on the FPGA fabric design and can vary with different
>   customer designs;
> - to clean up interrupt initialisation to make it more maintainable;
> - to fix SEC and DED interrupt handling.
> 
> I expect Conor will take the dts patch via the soc tree once the PCIe parts
> of the series are accepted.
> 
> Conor Dooley (1):
>   riscv: dts: microchip: add parent ranges and dma-ranges for IKRD
>     v2022.09
> 
> Daire McNamara (8):
>   PCI: microchip: Align register, offset, and mask names with hw docs
>   PCI: microchip: Correct the DED and SEC interrupt bit offsets
>   PCI: microchip: Enable event handlers to access bridge and ctrl ptrs
>   PCI: microchip: Clean up initialisation of interrupts
>   PCI: microchip: Gather MSI information from hardware config registers
>   PCI: microchip: Re-partition code between probe() and init()
>   PCI: microchip: Partition outbound address translation
>   PCI: microchip: Partition inbound address translation
> 
>  .../dts/microchip/mpfs-icicle-kit-fabric.dtsi |  62 +-
>  drivers/pci/controller/pcie-microchip-host.c  | 676 +++++++++++++-----
>  2 files changed, 522 insertions(+), 216 deletions(-)
> 
> 
> base-commit: 3c1f24109dfc4fb1a3730ed237e50183c6bb26b3
> -- 
> 2.25.1
> 
> 
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