From: Andrew Lunn <andrew@lunn.ch>
To: Zhou Yanjie <zhouyanjie@wanyeetech.com>
Cc: davem@davemloft.net, kuba@kernel.org, robh+dt@kernel.org,
peppe.cavallaro@st.com, alexandre.torgue@foss.st.com,
joabreu@synopsys.com, mcoquelin.stm32@gmail.com,
linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org, dongsheng.qiu@ingenic.com,
aric.pzqi@ingenic.com, rick.tyliu@ingenic.com,
sihui.liu@ingenic.com, jun.jiang@ingenic.com,
sernia.zhou@foxmail.com, paul@crapouillou.net
Subject: Re: [PATCH v2 2/2] net: stmmac: Add Ingenic SoCs MAC support.
Date: Thu, 10 Jun 2021 16:57:29 +0200 [thread overview]
Message-ID: <YMIoWS57Ra19E1qT@lunn.ch> (raw)
In-Reply-To: <12f35415-532e-5514-bc97-683fb9655091@wanyeetech.com>
> Here is Ingenic's reply, the time length corresponding to a unit is 19.5ps
> (19500fs).
Sometimes, there is a negative offset in the delays. So a delay value
of 0 written to the register actually means -200ps or something.
Andrew
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Lunn <andrew@lunn.ch>
To: Zhou Yanjie <zhouyanjie@wanyeetech.com>
Cc: davem@davemloft.net, kuba@kernel.org, robh+dt@kernel.org,
peppe.cavallaro@st.com, alexandre.torgue@foss.st.com,
joabreu@synopsys.com, mcoquelin.stm32@gmail.com,
linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org, dongsheng.qiu@ingenic.com,
aric.pzqi@ingenic.com, rick.tyliu@ingenic.com,
sihui.liu@ingenic.com, jun.jiang@ingenic.com,
sernia.zhou@foxmail.com, paul@crapouillou.net
Subject: Re: [PATCH v2 2/2] net: stmmac: Add Ingenic SoCs MAC support.
Date: Thu, 10 Jun 2021 16:57:29 +0200 [thread overview]
Message-ID: <YMIoWS57Ra19E1qT@lunn.ch> (raw)
In-Reply-To: <12f35415-532e-5514-bc97-683fb9655091@wanyeetech.com>
> Here is Ingenic's reply, the time length corresponding to a unit is 19.5ps
> (19500fs).
Sometimes, there is a negative offset in the delays. So a delay value
of 0 written to the register actually means -200ps or something.
Andrew
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-06-10 14:57 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-09 17:35 [PATCH v2 0/2] Add Ingenic SoCs MAC support 周琰杰 (Zhou Yanjie)
2021-06-09 17:35 ` 周琰杰 (Zhou Yanjie)
2021-06-09 17:35 ` [PATCH v2 1/2] dt-bindings: dwmac: Add bindings for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
2021-06-09 17:35 ` 周琰杰 (Zhou Yanjie)
2021-06-09 17:35 ` [PATCH v2 2/2] net: stmmac: Add Ingenic SoCs MAC support 周琰杰 (Zhou Yanjie)
2021-06-09 17:35 ` 周琰杰 (Zhou Yanjie)
2021-06-10 3:19 ` Andrew Lunn
2021-06-10 3:19 ` Andrew Lunn
2021-06-10 8:00 ` Zhou Yanjie
2021-06-10 8:00 ` Zhou Yanjie
2021-06-10 12:15 ` Andrew Lunn
2021-06-10 12:15 ` Andrew Lunn
[not found] ` <346f64d9-6949-b506-258f-4cfa7eb22784@wanyeetech.com>
2021-06-10 14:42 ` Andrew Lunn
2021-06-10 14:42 ` Andrew Lunn
2021-06-13 8:26 ` 周琰杰
2021-06-13 8:26 ` 周琰杰
[not found] ` <12f35415-532e-5514-bc97-683fb9655091@wanyeetech.com>
2021-06-10 14:57 ` Andrew Lunn [this message]
2021-06-10 14:57 ` Andrew Lunn
2021-06-13 8:34 ` 周琰杰
2021-06-13 8:34 ` 周琰杰
2021-06-13 16:31 ` Andrew Lunn
2021-06-13 16:31 ` Andrew Lunn
2021-06-14 15:57 ` 周琰杰
2021-06-14 15:57 ` 周琰杰
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