From: Andi Shyti <andi.shyti@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>,
intel-gfx@lists.freedesktop.org,
Lucas De Marchi <lucas.demarchi@intel.com>,
dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3 07/10] drm/i915/xehp: Determine which tile raised an interrupt
Date: Tue, 2 Nov 2021 00:33:04 +0100 [thread overview]
Message-ID: <YYB5MJRdoCXmExpn@intel.intel> (raw)
In-Reply-To: <20211029032817.3747750-8-matthew.d.roper@intel.com>
Hi Matt and Paulo,
> @@ -2771,40 +2771,45 @@ static inline void dg1_master_intr_enable(void __iomem * const regs)
> static irqreturn_t dg1_irq_handler(int irq, void *arg)
> {
> struct drm_i915_private * const i915 = arg;
> + void __iomem * const t0_regs = i915->gt.uncore->regs;
> struct intel_gt *gt = &i915->gt;
> - void __iomem * const regs = gt->uncore->regs;
> u32 master_tile_ctl, master_ctl;
> - u32 gu_misc_iir;
> + u32 gu_misc_iir = 0;
just a nitpick, this doesn't need to be initialize and you could
also insert it inside the for_each_gt()
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Thanks,
Andi
> + unsigned int i;
>
> if (!intel_irqs_enabled(i915))
> return IRQ_NONE;
>
> - master_tile_ctl = dg1_master_intr_disable(regs);
> + master_tile_ctl = dg1_master_intr_disable(t0_regs);
> if (!master_tile_ctl) {
> - dg1_master_intr_enable(regs);
> + dg1_master_intr_enable(t0_regs);
> return IRQ_NONE;
> }
>
> - /* FIXME: we only support tile 0 for now. */
> - if (master_tile_ctl & DG1_MSTR_TILE(0)) {
> + for_each_gt(i915, i, gt) {
> + void __iomem *const regs = gt->uncore->regs;
> +
> + if ((master_tile_ctl & DG1_MSTR_TILE(i)) == 0)
> + continue;
> +
> master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
> raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl);
> - } else {
> - DRM_ERROR("Tile not supported: 0x%08x\n", master_tile_ctl);
> - dg1_master_intr_enable(regs);
> - return IRQ_NONE;
> - }
>
> - gen11_gt_irq_handler(gt, master_ctl);
> + gen11_gt_irq_handler(gt, master_ctl);
>
> - if (master_ctl & GEN11_DISPLAY_IRQ)
> - gen11_display_irq_handler(i915);
> -
> - gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
> + /*
> + * In practice we'll only get display and gu_misc interrupts
> + * for the GSE on tile0, but it's still simplest to process
> + * them inside the loop.
> + */
> + if (master_ctl & GEN11_DISPLAY_IRQ)
> + gen11_display_irq_handler(i915);
>
> - dg1_master_intr_enable(regs);
> + gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
> + gen11_gu_misc_irq_handler(gt, gu_misc_iir);
> + }
>
> - gen11_gu_misc_irq_handler(gt, gu_misc_iir);
> + dg1_master_intr_enable(t0_regs);
>
> pmu_irq_stats(i915, IRQ_HANDLED);
>
> --
> 2.33.0
WARNING: multiple messages have this Message-ID (diff)
From: Andi Shyti <andi.shyti@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>,
Tvrtko Ursulin <tvrtko.ursulin@intel.com>,
intel-gfx@lists.freedesktop.org,
Lucas De Marchi <lucas.demarchi@intel.com>,
dri-devel@lists.freedesktop.org,
Stuart Summers <stuart.summers@intel.com>
Subject: Re: [PATCH v3 07/10] drm/i915/xehp: Determine which tile raised an interrupt
Date: Tue, 2 Nov 2021 00:33:04 +0100 [thread overview]
Message-ID: <YYB5MJRdoCXmExpn@intel.intel> (raw)
In-Reply-To: <20211029032817.3747750-8-matthew.d.roper@intel.com>
Hi Matt and Paulo,
> @@ -2771,40 +2771,45 @@ static inline void dg1_master_intr_enable(void __iomem * const regs)
> static irqreturn_t dg1_irq_handler(int irq, void *arg)
> {
> struct drm_i915_private * const i915 = arg;
> + void __iomem * const t0_regs = i915->gt.uncore->regs;
> struct intel_gt *gt = &i915->gt;
> - void __iomem * const regs = gt->uncore->regs;
> u32 master_tile_ctl, master_ctl;
> - u32 gu_misc_iir;
> + u32 gu_misc_iir = 0;
just a nitpick, this doesn't need to be initialize and you could
also insert it inside the for_each_gt()
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Thanks,
Andi
> + unsigned int i;
>
> if (!intel_irqs_enabled(i915))
> return IRQ_NONE;
>
> - master_tile_ctl = dg1_master_intr_disable(regs);
> + master_tile_ctl = dg1_master_intr_disable(t0_regs);
> if (!master_tile_ctl) {
> - dg1_master_intr_enable(regs);
> + dg1_master_intr_enable(t0_regs);
> return IRQ_NONE;
> }
>
> - /* FIXME: we only support tile 0 for now. */
> - if (master_tile_ctl & DG1_MSTR_TILE(0)) {
> + for_each_gt(i915, i, gt) {
> + void __iomem *const regs = gt->uncore->regs;
> +
> + if ((master_tile_ctl & DG1_MSTR_TILE(i)) == 0)
> + continue;
> +
> master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
> raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl);
> - } else {
> - DRM_ERROR("Tile not supported: 0x%08x\n", master_tile_ctl);
> - dg1_master_intr_enable(regs);
> - return IRQ_NONE;
> - }
>
> - gen11_gt_irq_handler(gt, master_ctl);
> + gen11_gt_irq_handler(gt, master_ctl);
>
> - if (master_ctl & GEN11_DISPLAY_IRQ)
> - gen11_display_irq_handler(i915);
> -
> - gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
> + /*
> + * In practice we'll only get display and gu_misc interrupts
> + * for the GSE on tile0, but it's still simplest to process
> + * them inside the loop.
> + */
> + if (master_ctl & GEN11_DISPLAY_IRQ)
> + gen11_display_irq_handler(i915);
>
> - dg1_master_intr_enable(regs);
> + gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
> + gen11_gu_misc_irq_handler(gt, gu_misc_iir);
> + }
>
> - gen11_gu_misc_irq_handler(gt, gu_misc_iir);
> + dg1_master_intr_enable(t0_regs);
>
> pmu_irq_stats(i915, IRQ_HANDLED);
>
> --
> 2.33.0
next prev parent reply other threads:[~2021-11-01 23:33 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-29 3:28 [Intel-gfx] [PATCH v3 00/10] i915: Initial multi-tile support Matt Roper
2021-10-29 3:28 ` Matt Roper
2021-10-29 3:28 ` [Intel-gfx] [PATCH v3 01/10] drm/i915: rework some irq functions to take intel_gt as argument Matt Roper
2021-10-29 3:28 ` Matt Roper
2021-10-29 3:28 ` [Intel-gfx] [PATCH v3 02/10] drm/i915: split general MMIO setup from per-GT uncore init Matt Roper
2021-10-29 3:28 ` Matt Roper
2021-11-11 5:12 ` [Intel-gfx] " Matt Roper
2021-11-11 5:12 ` Matt Roper
2021-10-29 3:28 ` [Intel-gfx] [PATCH v3 03/10] drm/i915: Restructure probe to handle multi-tile platforms Matt Roper
2021-10-29 3:28 ` Matt Roper
2021-11-01 22:58 ` [Intel-gfx] " Andi Shyti
2021-11-01 22:58 ` Andi Shyti
2021-11-01 23:21 ` [Intel-gfx] " Andi Shyti
2021-11-01 23:21 ` Andi Shyti
2021-10-29 3:28 ` [Intel-gfx] [PATCH v3 04/10] drm/i915: Store backpointer to GT in uncore Matt Roper
2021-10-29 3:28 ` Matt Roper
2021-10-29 3:28 ` [Intel-gfx] [PATCH v3 05/10] drm/i915: Prepare for multiple gts Matt Roper
2021-10-29 3:28 ` Matt Roper
2021-11-01 23:11 ` [Intel-gfx] " Andi Shyti
2021-11-01 23:11 ` Andi Shyti
2021-11-02 9:36 ` [Intel-gfx] " Tvrtko Ursulin
2021-11-02 11:26 ` Andi Shyti
2021-11-02 11:26 ` Andi Shyti
2021-11-02 13:58 ` Tvrtko Ursulin
2021-11-02 21:08 ` Andi Shyti
2021-11-02 21:08 ` Andi Shyti
2021-10-29 3:28 ` [Intel-gfx] [PATCH v3 06/10] drm/i915: Initial support for per-tile uncore Matt Roper
2021-10-29 3:28 ` Matt Roper
2021-10-29 3:28 ` [Intel-gfx] [PATCH v3 07/10] drm/i915/xehp: Determine which tile raised an interrupt Matt Roper
2021-10-29 3:28 ` Matt Roper
2021-11-01 23:33 ` Andi Shyti [this message]
2021-11-01 23:33 ` Andi Shyti
2021-10-29 3:28 ` [Intel-gfx] [PATCH v3 08/10] drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware Matt Roper
2021-10-29 3:28 ` Matt Roper
2021-10-29 3:28 ` [Intel-gfx] [PATCH v3 09/10] drm/i915/guc: Update CT debug macro for multi-tile Matt Roper
2021-10-29 3:28 ` Matt Roper
2021-11-01 23:35 ` [Intel-gfx] " Andi Shyti
2021-11-01 23:35 ` Andi Shyti
2021-10-29 3:28 ` [Intel-gfx] [PATCH v3 10/10] drm/i915/xehpsdv: Initialize multi-tiles Matt Roper
2021-10-29 3:28 ` Matt Roper
2021-10-29 3:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Initial multi-tile support (rev3) Patchwork
2021-10-29 4:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-29 10:16 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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