From: Rob Herring <robh@kernel.org>
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Tudor Ambarus <Tudor.Ambarus@microchip.com>,
Pratyush Yadav <p.yadav@ti.com>, Michael Walle <michael@walle.cc>,
linux-mtd@lists.infradead.org, Mark Brown <broonie@kernel.org>,
linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Michal Simek <monstr@monstr.eu>
Subject: Re: [PATCH v2 4/5] spi: dt-bindings: Describe stacked/parallel memories modes
Date: Wed, 1 Dec 2021 18:04:10 -0600 [thread overview]
Message-ID: <YagNemH3SYHQJBTs@robh.at.kernel.org> (raw)
In-Reply-To: <20211126163450.394861-5-miquel.raynal@bootlin.com>
On Fri, Nov 26, 2021 at 05:34:49PM +0100, Miquel Raynal wrote:
> Describe two new memories modes:
> - A stacked mode when the bus is common but the address space extended
> with an additinals wires.
> - A parallel mode with parallel busses accessing parallel flashes where
> the data is spread.
I don't quite understand why this is in spi-controller.yaml.
Also, please see this series[1].
Rob
[1] https://lore.kernel.org/all/20211109181911.2251-1-p.yadav@ti.com/
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WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Tudor Ambarus <Tudor.Ambarus@microchip.com>,
Pratyush Yadav <p.yadav@ti.com>, Michael Walle <michael@walle.cc>,
linux-mtd@lists.infradead.org, Mark Brown <broonie@kernel.org>,
linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Michal Simek <monstr@monstr.eu>
Subject: Re: [PATCH v2 4/5] spi: dt-bindings: Describe stacked/parallel memories modes
Date: Wed, 1 Dec 2021 18:04:10 -0600 [thread overview]
Message-ID: <YagNemH3SYHQJBTs@robh.at.kernel.org> (raw)
In-Reply-To: <20211126163450.394861-5-miquel.raynal@bootlin.com>
On Fri, Nov 26, 2021 at 05:34:49PM +0100, Miquel Raynal wrote:
> Describe two new memories modes:
> - A stacked mode when the bus is common but the address space extended
> with an additinals wires.
> - A parallel mode with parallel busses accessing parallel flashes where
> the data is spread.
I don't quite understand why this is in spi-controller.yaml.
Also, please see this series[1].
Rob
[1] https://lore.kernel.org/all/20211109181911.2251-1-p.yadav@ti.com/
next prev parent reply other threads:[~2021-12-02 0:05 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-26 16:34 [PATCH v2 0/5] Stacked/parallel memories bindings Miquel Raynal
2021-11-26 16:34 ` Miquel Raynal
2021-11-26 16:34 ` [PATCH v2 1/5] spi: dt-bindings: Allow describing flashes with two CS Miquel Raynal
2021-11-26 16:34 ` Miquel Raynal
2021-11-26 16:34 ` [PATCH v2 2/5] dt-bindings: mtd: spi-nor: Allow external properties Miquel Raynal
2021-11-26 16:34 ` Miquel Raynal
2021-12-02 0:05 ` Rob Herring
2021-12-02 0:05 ` Rob Herring
2021-12-02 7:25 ` Miquel Raynal
2021-12-02 7:25 ` Miquel Raynal
2021-12-02 15:51 ` Rob Herring
2021-12-02 15:51 ` Rob Herring
2021-11-26 16:34 ` [PATCH v2 3/5] dt-bindings: mtd: spi-nor: Allow two CS per device Miquel Raynal
2021-11-26 16:34 ` Miquel Raynal
2021-12-02 0:06 ` Rob Herring
2021-12-02 0:06 ` Rob Herring
2021-11-26 16:34 ` [PATCH v2 4/5] spi: dt-bindings: Describe stacked/parallel memories modes Miquel Raynal
2021-11-26 16:34 ` Miquel Raynal
2021-12-02 0:04 ` Rob Herring [this message]
2021-12-02 0:04 ` Rob Herring
2021-11-26 16:34 ` [PATCH v2 5/5] spi: dt-bindings: Add an example with two stacked flashes Miquel Raynal
2021-11-26 16:34 ` Miquel Raynal
2021-11-27 23:13 ` Rob Herring
2021-11-27 23:13 ` Rob Herring
2021-11-28 16:55 ` Rob Herring
2021-11-28 16:55 ` Rob Herring
2021-11-29 9:23 ` Miquel Raynal
2021-11-29 9:23 ` Miquel Raynal
2021-12-01 23:57 ` Rob Herring
2021-12-01 23:57 ` Rob Herring
2021-12-02 7:26 ` Miquel Raynal
2021-12-02 7:26 ` Miquel Raynal
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