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From: Andrew Lunn <andrew@lunn.ch>
To: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: linus.walleij@linaro.org, robh+dt@kernel.org,
	catalin.marinas@arm.com, will@kernel.org,
	gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com,
	kostap@marvell.com, robert.marko@sartura.hr,
	linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 3/4] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board
Date: Thu, 7 Apr 2022 01:23:41 +0200	[thread overview]
Message-ID: <Yk4g/ShFxNsCM8JR@lunn.ch> (raw)
In-Reply-To: <20220406032158.1449049-4-chris.packham@alliedtelesis.co.nz>

On Wed, Apr 06, 2022 at 03:21:57PM +1200, Chris Packham wrote:
> The 98DX2530 SoC is the Control and Management CPU integrated into
> the Marvell 98DX25xx and 98DX35xx series of switch chip (internally
> referred to as AlleyCat5 and AlleyCat5X).
> 
> These files have been taken from the Marvell SDK and lightly cleaned
> up with the License and copyright retained.
> 
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>

> +&eth0 {
> +	status = "okay";
> +	phy = <&phy0>;

This is O.K, but most DT files now use phy-handle, not phy.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

WARNING: multiple messages have this Message-ID (diff)
From: Andrew Lunn <andrew@lunn.ch>
To: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: linus.walleij@linaro.org, robh+dt@kernel.org,
	catalin.marinas@arm.com, will@kernel.org,
	gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com,
	kostap@marvell.com, robert.marko@sartura.hr,
	linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 3/4] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board
Date: Thu, 7 Apr 2022 01:23:41 +0200	[thread overview]
Message-ID: <Yk4g/ShFxNsCM8JR@lunn.ch> (raw)
In-Reply-To: <20220406032158.1449049-4-chris.packham@alliedtelesis.co.nz>

On Wed, Apr 06, 2022 at 03:21:57PM +1200, Chris Packham wrote:
> The 98DX2530 SoC is the Control and Management CPU integrated into
> the Marvell 98DX25xx and 98DX35xx series of switch chip (internally
> referred to as AlleyCat5 and AlleyCat5X).
> 
> These files have been taken from the Marvell SDK and lightly cleaned
> up with the License and copyright retained.
> 
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>

> +&eth0 {
> +	status = "okay";
> +	phy = <&phy0>;

This is O.K, but most DT files now use phy-handle, not phy.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-04-06 23:23 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-06  3:21 [PATCH v3 0/4] arm64: mvebu: Support for Marvell 98DX2530 (and variants) Chris Packham
2022-04-06  3:21 ` Chris Packham
2022-04-06  3:21 ` [PATCH v3 1/4] dt-bindings: pinctrl: mvebu: Document bindings for AC5 Chris Packham
2022-04-06  3:21   ` Chris Packham
2022-04-06 23:20   ` Andrew Lunn
2022-04-06 23:20     ` Andrew Lunn
2022-04-13 18:29   ` Rob Herring
2022-04-13 18:29     ` Rob Herring
2022-04-06  3:21 ` [PATCH v3 2/4] pinctrl: mvebu: pinctrl driver for 98DX2530 SoC Chris Packham
2022-04-06  3:21   ` Chris Packham
2022-04-06 12:36   ` Andrew Lunn
2022-04-06 12:36     ` Andrew Lunn
2022-04-06 21:51     ` Chris Packham
2022-04-06 21:51       ` Chris Packham
2022-04-06 23:17       ` Andrew Lunn
2022-04-06 23:17         ` Andrew Lunn
2022-04-06  3:21 ` [PATCH v3 3/4] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board Chris Packham
2022-04-06  3:21   ` Chris Packham
2022-04-06 23:23   ` Andrew Lunn [this message]
2022-04-06 23:23     ` Andrew Lunn
2022-04-06 23:29     ` Chris Packham
2022-04-06 23:29       ` Chris Packham
2022-04-06  3:21 ` [PATCH v3 4/4] arm64: marvell: enable the 98DX2530 pinctrl driver Chris Packham
2022-04-06  3:21   ` Chris Packham

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