From: Oliver Upton <oupton@google.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
kvm@vger.kernel.org, Andre Przywara <andre.przywara@arm.com>,
kernel-team@android.com, kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 3/4] KVM: arm64: vgic-v3: Implement MMIO-based LPI invalidation
Date: Thu, 7 Apr 2022 23:13:24 +0000 [thread overview]
Message-ID: <Yk9wFMICRqF6ROti@google.com> (raw)
In-Reply-To: <20220405182327.205520-4-maz@kernel.org>
On Tue, Apr 05, 2022 at 07:23:26PM +0100, Marc Zyngier wrote:
> Since GICv4.1, it has become legal for an implementation to advertise
> GICR_{INVLPIR,INVALLR,SYNCR} while having an ITS, allowing for a more
> efficient invalidation scheme (no guest command queue contention when
> multiple CPUs are generating invalidations).
>
> Provide the invalidation registers as a primitive to their ITS
> counterpart. Note that we don't advertise them to the guest yet
> (the architecture allows an implementation to do this).
>
I'll admit that this part tripped me up a bit, odd stuff.
> Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Oliver Upton <oupton@google.com>
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kvmarm@lists.cs.columbia.edu
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WARNING: multiple messages have this Message-ID (diff)
From: Oliver Upton <oupton@google.com>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
kvmarm@lists.cs.columbia.edu, James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Andre Przywara <andre.przywara@arm.com>,
Eric Auger <eric.auger@redhat.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
kernel-team@android.com
Subject: Re: [PATCH v2 3/4] KVM: arm64: vgic-v3: Implement MMIO-based LPI invalidation
Date: Thu, 7 Apr 2022 23:13:24 +0000 [thread overview]
Message-ID: <Yk9wFMICRqF6ROti@google.com> (raw)
In-Reply-To: <20220405182327.205520-4-maz@kernel.org>
On Tue, Apr 05, 2022 at 07:23:26PM +0100, Marc Zyngier wrote:
> Since GICv4.1, it has become legal for an implementation to advertise
> GICR_{INVLPIR,INVALLR,SYNCR} while having an ITS, allowing for a more
> efficient invalidation scheme (no guest command queue contention when
> multiple CPUs are generating invalidations).
>
> Provide the invalidation registers as a primitive to their ITS
> counterpart. Note that we don't advertise them to the guest yet
> (the architecture allows an implementation to do this).
>
I'll admit that this part tripped me up a bit, odd stuff.
> Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Oliver Upton <oupton@google.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Oliver Upton <oupton@google.com>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
kvmarm@lists.cs.columbia.edu, James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Andre Przywara <andre.przywara@arm.com>,
Eric Auger <eric.auger@redhat.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
kernel-team@android.com
Subject: Re: [PATCH v2 3/4] KVM: arm64: vgic-v3: Implement MMIO-based LPI invalidation
Date: Thu, 7 Apr 2022 23:13:24 +0000 [thread overview]
Message-ID: <Yk9wFMICRqF6ROti@google.com> (raw)
In-Reply-To: <20220405182327.205520-4-maz@kernel.org>
On Tue, Apr 05, 2022 at 07:23:26PM +0100, Marc Zyngier wrote:
> Since GICv4.1, it has become legal for an implementation to advertise
> GICR_{INVLPIR,INVALLR,SYNCR} while having an ITS, allowing for a more
> efficient invalidation scheme (no guest command queue contention when
> multiple CPUs are generating invalidations).
>
> Provide the invalidation registers as a primitive to their ITS
> counterpart. Note that we don't advertise them to the guest yet
> (the architecture allows an implementation to do this).
>
I'll admit that this part tripped me up a bit, odd stuff.
> Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Oliver Upton <oupton@google.com>
next prev parent reply other threads:[~2022-04-07 23:13 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-05 18:23 [PATCH v2 0/4] KVM: arm64: vgic-v3: MMIO-based LPI invalidation and co Marc Zyngier
2022-04-05 18:23 ` Marc Zyngier
2022-04-05 18:23 ` Marc Zyngier
2022-04-05 18:23 ` [PATCH v2 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES} Marc Zyngier
2022-04-05 18:23 ` [PATCH v2 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR,CES} Marc Zyngier
2022-04-05 18:23 ` [PATCH v2 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES} Marc Zyngier
2022-04-07 20:13 ` [PATCH v2 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR,CES} Oliver Upton
2022-04-07 20:13 ` Oliver Upton
2022-04-07 20:13 ` Oliver Upton
2022-05-04 15:15 ` [irqchip: irq/irqchip-next] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES} irqchip-bot for Marc Zyngier
2022-04-05 18:23 ` [PATCH v2 2/4] KVM: arm64: vgic-v3: Expose GICR_CTLR.RWP when disabling LPIs Marc Zyngier
2022-04-05 18:23 ` Marc Zyngier
2022-04-05 18:23 ` Marc Zyngier
2022-04-05 18:23 ` [PATCH v2 3/4] KVM: arm64: vgic-v3: Implement MMIO-based LPI invalidation Marc Zyngier
2022-04-05 18:23 ` Marc Zyngier
2022-04-05 18:23 ` Marc Zyngier
2022-04-07 23:13 ` Oliver Upton [this message]
2022-04-07 23:13 ` Oliver Upton
2022-04-07 23:13 ` Oliver Upton
2022-04-05 18:23 ` [PATCH v2 4/4] KVM: arm64: vgic-v3: Advertise GICR_CTLR.{IR, CES} as a new GICD_IIDR revision Marc Zyngier
2022-04-05 18:23 ` [PATCH v2 4/4] KVM: arm64: vgic-v3: Advertise GICR_CTLR.{IR,CES} " Marc Zyngier
2022-04-05 18:23 ` [PATCH v2 4/4] KVM: arm64: vgic-v3: Advertise GICR_CTLR.{IR, CES} " Marc Zyngier
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