From: Oliver Upton <oupton@google.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
kvm@vger.kernel.org, Andre Przywara <andre.przywara@arm.com>,
kernel-team@android.com, kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR,CES}
Date: Thu, 7 Apr 2022 20:13:22 +0000 [thread overview]
Message-ID: <Yk9F4jkfmYKdvUHz@google.com> (raw)
In-Reply-To: <20220405182327.205520-2-maz@kernel.org>
On Tue, Apr 05, 2022 at 07:23:24PM +0100, Marc Zyngier wrote:
> As we're about to expose GICR_CTLR.{IR,CES} to guests, populate
> the include file with the architectural values.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Oliver Upton <oupton@google.com>
> ---
> include/linux/irqchip/arm-gic-v3.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
> index 12d91f0dedf9..728691365464 100644
> --- a/include/linux/irqchip/arm-gic-v3.h
> +++ b/include/linux/irqchip/arm-gic-v3.h
> @@ -127,6 +127,8 @@
> #define GICR_PIDR2 GICD_PIDR2
>
> #define GICR_CTLR_ENABLE_LPIS (1UL << 0)
> +#define GICR_CTLR_CES (1UL << 1)
> +#define GICR_CTLR_IR (1UL << 2)
> #define GICR_CTLR_RWP (1UL << 3)
>
> #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
> --
> 2.34.1
>
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Oliver Upton <oupton@google.com>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
kvmarm@lists.cs.columbia.edu, James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Andre Przywara <andre.przywara@arm.com>,
Eric Auger <eric.auger@redhat.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
kernel-team@android.com
Subject: Re: [PATCH v2 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR,CES}
Date: Thu, 7 Apr 2022 20:13:22 +0000 [thread overview]
Message-ID: <Yk9F4jkfmYKdvUHz@google.com> (raw)
In-Reply-To: <20220405182327.205520-2-maz@kernel.org>
On Tue, Apr 05, 2022 at 07:23:24PM +0100, Marc Zyngier wrote:
> As we're about to expose GICR_CTLR.{IR,CES} to guests, populate
> the include file with the architectural values.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Oliver Upton <oupton@google.com>
> ---
> include/linux/irqchip/arm-gic-v3.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
> index 12d91f0dedf9..728691365464 100644
> --- a/include/linux/irqchip/arm-gic-v3.h
> +++ b/include/linux/irqchip/arm-gic-v3.h
> @@ -127,6 +127,8 @@
> #define GICR_PIDR2 GICD_PIDR2
>
> #define GICR_CTLR_ENABLE_LPIS (1UL << 0)
> +#define GICR_CTLR_CES (1UL << 1)
> +#define GICR_CTLR_IR (1UL << 2)
> #define GICR_CTLR_RWP (1UL << 3)
>
> #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
> --
> 2.34.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Oliver Upton <oupton@google.com>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,
kvmarm@lists.cs.columbia.edu, James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Andre Przywara <andre.przywara@arm.com>,
Eric Auger <eric.auger@redhat.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
kernel-team@android.com
Subject: Re: [PATCH v2 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR,CES}
Date: Thu, 7 Apr 2022 20:13:22 +0000 [thread overview]
Message-ID: <Yk9F4jkfmYKdvUHz@google.com> (raw)
In-Reply-To: <20220405182327.205520-2-maz@kernel.org>
On Tue, Apr 05, 2022 at 07:23:24PM +0100, Marc Zyngier wrote:
> As we're about to expose GICR_CTLR.{IR,CES} to guests, populate
> the include file with the architectural values.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Oliver Upton <oupton@google.com>
> ---
> include/linux/irqchip/arm-gic-v3.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
> index 12d91f0dedf9..728691365464 100644
> --- a/include/linux/irqchip/arm-gic-v3.h
> +++ b/include/linux/irqchip/arm-gic-v3.h
> @@ -127,6 +127,8 @@
> #define GICR_PIDR2 GICD_PIDR2
>
> #define GICR_CTLR_ENABLE_LPIS (1UL << 0)
> +#define GICR_CTLR_CES (1UL << 1)
> +#define GICR_CTLR_IR (1UL << 2)
> #define GICR_CTLR_RWP (1UL << 3)
>
> #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
> --
> 2.34.1
>
next prev parent reply other threads:[~2022-04-07 20:13 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-05 18:23 [PATCH v2 0/4] KVM: arm64: vgic-v3: MMIO-based LPI invalidation and co Marc Zyngier
2022-04-05 18:23 ` Marc Zyngier
2022-04-05 18:23 ` Marc Zyngier
2022-04-05 18:23 ` [PATCH v2 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES} Marc Zyngier
2022-04-05 18:23 ` [PATCH v2 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR,CES} Marc Zyngier
2022-04-05 18:23 ` [PATCH v2 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES} Marc Zyngier
2022-04-07 20:13 ` Oliver Upton [this message]
2022-04-07 20:13 ` [PATCH v2 1/4] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR,CES} Oliver Upton
2022-04-07 20:13 ` Oliver Upton
2022-05-04 15:15 ` [irqchip: irq/irqchip-next] irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES} irqchip-bot for Marc Zyngier
2022-04-05 18:23 ` [PATCH v2 2/4] KVM: arm64: vgic-v3: Expose GICR_CTLR.RWP when disabling LPIs Marc Zyngier
2022-04-05 18:23 ` Marc Zyngier
2022-04-05 18:23 ` Marc Zyngier
2022-04-05 18:23 ` [PATCH v2 3/4] KVM: arm64: vgic-v3: Implement MMIO-based LPI invalidation Marc Zyngier
2022-04-05 18:23 ` Marc Zyngier
2022-04-05 18:23 ` Marc Zyngier
2022-04-07 23:13 ` Oliver Upton
2022-04-07 23:13 ` Oliver Upton
2022-04-07 23:13 ` Oliver Upton
2022-04-05 18:23 ` [PATCH v2 4/4] KVM: arm64: vgic-v3: Advertise GICR_CTLR.{IR, CES} as a new GICD_IIDR revision Marc Zyngier
2022-04-05 18:23 ` [PATCH v2 4/4] KVM: arm64: vgic-v3: Advertise GICR_CTLR.{IR,CES} " Marc Zyngier
2022-04-05 18:23 ` [PATCH v2 4/4] KVM: arm64: vgic-v3: Advertise GICR_CTLR.{IR, CES} " Marc Zyngier
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