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From: Andrew Lunn <andrew@lunn.ch>
To: "Pali Rohár" <pali@kernel.org>
Cc: Gregory Clement <gregory.clement@bootlin.com>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] irqchip/armada-370-xp: Do not allow mapping IRQ 0 and 1
Date: Fri, 29 Apr 2022 14:30:53 +0200	[thread overview]
Message-ID: <YmvafYwhtIoaOMmk@lunn.ch> (raw)
In-Reply-To: <20220425113706.29310-2-pali@kernel.org>

On Mon, Apr 25, 2022 at 01:37:06PM +0200, Pali Rohár wrote:
> IRQs 0 and 1 cannot be mapped, they are handled internally by this driver
> and this driver does not call generic_handle_domain_irq() for these IRQs.
> So do not allow mapping these IRQs and correctly propagate error from the
> .irq_map callback.

So you are referring to this?

                /* Check if the interrupt is not masked on current CPU.
                 * Test IRQ (0-1) and FIQ (8-9) mask bits.
                 */
                if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
                        continue;

                if (irqn == 1) {
                        armada_370_xp_handle_msi_irq(NULL, true);
                        continue;
                }


Should the two FIQ interrupts also return -EINVAL?

       Andrew

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WARNING: multiple messages have this Message-ID (diff)
From: Andrew Lunn <andrew@lunn.ch>
To: "Pali Rohár" <pali@kernel.org>
Cc: Gregory Clement <gregory.clement@bootlin.com>,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] irqchip/armada-370-xp: Do not allow mapping IRQ 0 and 1
Date: Fri, 29 Apr 2022 14:30:53 +0200	[thread overview]
Message-ID: <YmvafYwhtIoaOMmk@lunn.ch> (raw)
In-Reply-To: <20220425113706.29310-2-pali@kernel.org>

On Mon, Apr 25, 2022 at 01:37:06PM +0200, Pali Rohár wrote:
> IRQs 0 and 1 cannot be mapped, they are handled internally by this driver
> and this driver does not call generic_handle_domain_irq() for these IRQs.
> So do not allow mapping these IRQs and correctly propagate error from the
> .irq_map callback.

So you are referring to this?

                /* Check if the interrupt is not masked on current CPU.
                 * Test IRQ (0-1) and FIQ (8-9) mask bits.
                 */
                if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
                        continue;

                if (irqn == 1) {
                        armada_370_xp_handle_msi_irq(NULL, true);
                        continue;
                }


Should the two FIQ interrupts also return -EINVAL?

       Andrew

  reply	other threads:[~2022-04-29 12:32 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-25 11:37 [PATCH 1/2] irqchip/armada-370-xp: Do not touch Performance Counter Overflow on A375, A38x, A39x Pali Rohár
2022-04-25 11:37 ` Pali Rohár
2022-04-25 11:37 ` [PATCH 2/2] irqchip/armada-370-xp: Do not allow mapping IRQ 0 and 1 Pali Rohár
2022-04-25 11:37   ` Pali Rohár
2022-04-29 12:30   ` Andrew Lunn [this message]
2022-04-29 12:30     ` Andrew Lunn
2022-05-01 12:02     ` Pali Rohár
2022-05-01 12:02       ` Pali Rohár
2022-05-06 11:22   ` Marc Zyngier
2022-05-06 11:22     ` Marc Zyngier
2022-05-06 11:25   ` [irqchip: irq/irqchip-next] " irqchip-bot for Pali Rohár
2022-04-29 12:23 ` [PATCH 1/2] irqchip/armada-370-xp: Do not touch Performance Counter Overflow on A375, A38x, A39x Andrew Lunn
2022-04-29 12:23   ` Andrew Lunn
2022-04-29 13:05   ` Pali Rohár
2022-04-29 13:05     ` Pali Rohár
2022-04-29 22:23     ` Andrew Lunn
2022-04-29 22:23       ` Andrew Lunn
2022-04-29 22:31       ` Pali Rohár
2022-04-29 22:31         ` Pali Rohár
2022-04-29 22:39         ` Andrew Lunn
2022-04-29 22:39           ` Andrew Lunn
2022-05-06 11:25 ` [irqchip: irq/irqchip-next] " irqchip-bot for Pali Rohár

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