From: Andi Shyti <andi.shyti@linux.intel.com>
To: "Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com>
Cc: Intel GFX <intel-gfx@lists.freedesktop.org>,
Lucas De Marchi <lucas.demarchi@intel.com>,
DRI Devel <dri-devel@lists.freedesktop.org>,
Chris Wilson <chris@chris-wilson.co.uk>,
Matthew Auld <matthew.auld@intel.com>
Subject: Re: [Intel-gfx] [PATCH v7 3/7] drm/i915: Prepare for multiple GTs
Date: Fri, 20 May 2022 00:03:44 +0200 [thread overview]
Message-ID: <Yoa+wBHpVjCBZjH0@intel.intel> (raw)
In-Reply-To: <c29bd965-eaff-5767-34a4-1eee27a7fe3f@intel.com>
Hi Daniele,
> > > @@ -909,6 +903,8 @@ int i915_driver_probe(struct pci_dev *pdev,
> > > const struct pci_device_id *ent)
> > > i915_ggtt_driver_late_release(i915);
> > > out_cleanup_mmio:
> > > i915_driver_mmio_release(i915);
> > > +out_tiles_cleanup:
> > > + intel_gt_release_all(i915);
> >
> > We don't seem to call intel_gt_release_all() from driver_release(), so
> > we might be leaking something there. I wanted to send a patch to add the
> > call at the same place in the flow as in this error path, but then I
> > noticed that i915_driver_late_release(), which we call a few lines
> > below, calls intel_gt_driver_late_release_all(), which seems to expect
> > that the GTs are still allocated, so we probably need to flip the order
> > those are called in, or move the cleanup code from late_release() to
> > late_release_all() (or vice versa).
> > Andi, can you have a look at this?
well spotted! I will check it.
> Ping! :)
Sorry for taking so long for replying. I'm on it, now.
Thank you,
Andi
WARNING: multiple messages have this Message-ID (diff)
From: Andi Shyti <andi.shyti@linux.intel.com>
To: "Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>,
Andi Shyti <andi@etezian.org>,
Tvrtko Ursulin <tvrtko.ursulin@intel.com>,
Intel GFX <intel-gfx@lists.freedesktop.org>,
Lucas De Marchi <lucas.demarchi@intel.com>,
DRI Devel <dri-devel@lists.freedesktop.org>,
Chris Wilson <chris@chris-wilson.co.uk>,
Matthew Auld <matthew.auld@intel.com>,
Andi Shyti <andi.shyti@linux.intel.com>,
Michal Wajdeczko <michal.wajdeczko@intel.com>
Subject: Re: [PATCH v7 3/7] drm/i915: Prepare for multiple GTs
Date: Fri, 20 May 2022 00:03:44 +0200 [thread overview]
Message-ID: <Yoa+wBHpVjCBZjH0@intel.intel> (raw)
In-Reply-To: <c29bd965-eaff-5767-34a4-1eee27a7fe3f@intel.com>
Hi Daniele,
> > > @@ -909,6 +903,8 @@ int i915_driver_probe(struct pci_dev *pdev,
> > > const struct pci_device_id *ent)
> > > i915_ggtt_driver_late_release(i915);
> > > out_cleanup_mmio:
> > > i915_driver_mmio_release(i915);
> > > +out_tiles_cleanup:
> > > + intel_gt_release_all(i915);
> >
> > We don't seem to call intel_gt_release_all() from driver_release(), so
> > we might be leaking something there. I wanted to send a patch to add the
> > call at the same place in the flow as in this error path, but then I
> > noticed that i915_driver_late_release(), which we call a few lines
> > below, calls intel_gt_driver_late_release_all(), which seems to expect
> > that the GTs are still allocated, so we probably need to flip the order
> > those are called in, or move the cleanup code from late_release() to
> > late_release_all() (or vice versa).
> > Andi, can you have a look at this?
well spotted! I will check it.
> Ping! :)
Sorry for taking so long for replying. I'm on it, now.
Thank you,
Andi
next prev parent reply other threads:[~2022-05-19 22:03 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-18 23:39 [Intel-gfx] [PATCH v7 0/7] Introduce multitile support Andi Shyti
2022-03-18 23:39 ` Andi Shyti
2022-03-18 23:39 ` [Intel-gfx] [PATCH v7 1/7] drm/i915: Rename INTEL_REGION_LMEM with INTEL_REGION_LMEM_0 Andi Shyti
2022-03-18 23:39 ` Andi Shyti
2022-03-18 23:39 ` [Intel-gfx] [PATCH v7 2/7] drm/i915/gt: add gt_is_root() helper Andi Shyti
2022-03-18 23:39 ` Andi Shyti
2022-03-18 23:39 ` [Intel-gfx] [PATCH v7 3/7] drm/i915: Prepare for multiple GTs Andi Shyti
2022-03-18 23:39 ` Andi Shyti
2022-03-19 12:08 ` [Intel-gfx] " Michal Wajdeczko
2022-03-19 12:08 ` Michal Wajdeczko
2022-03-20 15:51 ` [Intel-gfx] " Andi Shyti
2022-03-20 15:51 ` Andi Shyti
2022-05-11 19:11 ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-05-11 19:11 ` Ceraolo Spurio, Daniele
2022-05-19 14:53 ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-05-19 14:53 ` Ceraolo Spurio, Daniele
2022-05-19 22:03 ` Andi Shyti [this message]
2022-05-19 22:03 ` Andi Shyti
2022-03-18 23:39 ` [Intel-gfx] [PATCH v7 4/7] drm/i915/gt: create per-tile sysfs interface Andi Shyti
2022-03-18 23:39 ` Andi Shyti
2022-03-18 23:39 ` [Intel-gfx] [PATCH v7 5/7] drm/i915/gt: Create per-tile RC6 " Andi Shyti
2022-03-18 23:39 ` Andi Shyti
2022-03-18 23:39 ` [Intel-gfx] [PATCH v7 6/7] drm/i915/gt: Create per-tile RPS sysfs interfaces Andi Shyti
2022-03-18 23:39 ` Andi Shyti
2022-05-05 13:14 ` [Intel-gfx] " Tvrtko Ursulin
2022-05-05 13:27 ` Andi Shyti
2022-05-05 13:27 ` Andi Shyti
2022-05-06 11:53 ` Jani Nikula
2022-05-06 15:21 ` Andi Shyti
2022-05-06 15:21 ` Andi Shyti
2022-03-18 23:39 ` [Intel-gfx] [PATCH v7 7/7] drm/i915/gt: Add sysfs throttle frequency interfaces Andi Shyti
2022-03-18 23:39 ` Andi Shyti
2022-03-18 23:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce multitile support Patchwork
2022-03-18 23:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-03-19 0:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-19 2:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-03-21 10:05 ` Matthew Auld
2022-03-21 16:44 ` Vudum, Lakshminarayana
2022-03-21 16:28 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2022-03-21 16:43 ` Patchwork
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