* [PATCH v6 1/2] ns16550: use poll mode if INTERRUPT_LINE is 0xff @ 2022-05-20 8:53 Marek Marczykowski-Górecki 2022-05-20 8:53 ` [PATCH v6 2/2] ns16550: Add more device IDs for Intel LPSS UART Marek Marczykowski-Górecki 2022-05-20 9:47 ` [PATCH v6 1/2] ns16550: use poll mode if INTERRUPT_LINE is 0xff Jan Beulich 0 siblings, 2 replies; 6+ messages in thread From: Marek Marczykowski-Górecki @ 2022-05-20 8:53 UTC (permalink / raw) To: xen-devel Cc: Marek Marczykowski-Górecki, Roger Pau Monné, Andrew Cooper, George Dunlap, Jan Beulich, Julien Grall, Stefano Stabellini, Wei Liu Intel LPSS has INTERRUPT_LINE set to 0xff by default, that is declared by the PCI Local Bus Specification Revision 3.0 (from 2004) as "unknown"/"no connection". Fallback to poll mode in this case. The 0xff handling is x86-specific, the surrounding code is guarded with CONFIG_X86 anyway. Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com> Reviewed-by: Roger Pau Monné <roger.pau@citrix.com> --- Changes in v6: - wrap the check in additional CONFIG_X86, with appropriate comment Changes in v5: - drop IRQ 0 from the log message Changes in v4: - adjust log message, change it from WARNING to INFO - re-add x86 reference in the commit message Changes in v3: - change back to checking 0xff explicitly - adjust commit message, include spec reference - change warning to match the above Changes in v2: - add log message - extend commit message - code style fix --- xen/drivers/char/ns16550.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index fb75cee4a13a..b37f67dc7430 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -1238,6 +1238,17 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) pci_conf_read8(PCI_SBDF(0, b, d, f), PCI_INTERRUPT_LINE) : 0; +#ifdef CONFIG_X86 + /* PCI Local Bus Specification Revision 3.0 defines 0xff value + * as special only for X86 */ + if ( uart->irq == 0xff ) + uart->irq = 0; +#endif + if ( !uart->irq ) + printk(XENLOG_INFO + "ns16550: %pp no legacy IRQ, using poll mode\n", + &PCI_SBDF(0, b, d, f)); + return 0; } } -- 2.35.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v6 2/2] ns16550: Add more device IDs for Intel LPSS UART 2022-05-20 8:53 [PATCH v6 1/2] ns16550: use poll mode if INTERRUPT_LINE is 0xff Marek Marczykowski-Górecki @ 2022-05-20 8:53 ` Marek Marczykowski-Górecki 2022-05-20 9:42 ` Jan Beulich 2022-05-20 9:47 ` [PATCH v6 1/2] ns16550: use poll mode if INTERRUPT_LINE is 0xff Jan Beulich 1 sibling, 1 reply; 6+ messages in thread From: Marek Marczykowski-Górecki @ 2022-05-20 8:53 UTC (permalink / raw) To: xen-devel Cc: Marek Marczykowski-Górecki, Andrew Cooper, George Dunlap, Jan Beulich, Julien Grall, Stefano Stabellini, Wei Liu This is purely based on the spec: - Intel 500 Series PCH: 635218-006 - Intel 600 Series PCH: 691222-001, 648364-003 This is tested only on TGL-LP added initially, but according to the spec, they should behave the same. Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com> Acked-by: Andrew Cooper <andrew.cooper3@citrix.com> --- Changes in v2: - new patch, adding more IDs to the patch that went in already --- xen/drivers/char/ns16550.c | 80 +++++++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index b37f67dc7430..b7da5646fc28 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -1077,12 +1077,90 @@ static const struct ns16550_config __initconst uart_config[] = .dev_id = 0x0358, .param = param_exar_xr17v358 }, - /* Intel Corp. TGL-LP LPSS PCI */ + /* Intel Corp. TGL-LP LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0xa0a8, + .param = param_intel_lpss + }, + /* Intel Corp. TGL-LP LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0xa0a9, + .param = param_intel_lpss + }, + /* Intel Corp. TGL-LP LPSS PCI UART #2 */ { .vendor_id = PCI_VENDOR_ID_INTEL, .dev_id = 0xa0c7, .param = param_intel_lpss }, + /* Intel Corp. TGL-H LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x43a8, + .param = param_intel_lpss + }, + /* Intel Corp. TGL-H LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x43a9, + .param = param_intel_lpss + }, + /* Intel Corp. TGL-H LPSS PCI UART #2 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x43a7, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-P LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x51a8, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-P LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x51a9, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-P LPSS PCI UART #2 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x51c7, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-P LPSS PCI UART #3 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x51da, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-S LPSS PCI UART #0 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7aa8, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-S LPSS PCI UART #1 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7aa9, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-S LPSS PCI UART #2 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7afe, + .param = param_intel_lpss + }, + /* Intel Corp. ADL-S LPSS PCI UART #3 */ + { + .vendor_id = PCI_VENDOR_ID_INTEL, + .dev_id = 0x7adc, + .param = param_intel_lpss + }, }; static int __init -- 2.35.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v6 2/2] ns16550: Add more device IDs for Intel LPSS UART 2022-05-20 8:53 ` [PATCH v6 2/2] ns16550: Add more device IDs for Intel LPSS UART Marek Marczykowski-Górecki @ 2022-05-20 9:42 ` Jan Beulich 2022-05-20 10:32 ` Marek Marczykowski-Górecki 0 siblings, 1 reply; 6+ messages in thread From: Jan Beulich @ 2022-05-20 9:42 UTC (permalink / raw) To: Marek Marczykowski-Górecki Cc: Andrew Cooper, George Dunlap, Julien Grall, Stefano Stabellini, Wei Liu, xen-devel On 20.05.2022 10:53, Marek Marczykowski-Górecki wrote: > This is purely based on the spec: > - Intel 500 Series PCH: 635218-006 > - Intel 600 Series PCH: 691222-001, 648364-003 > > This is tested only on TGL-LP added initially, but according to the > spec, they should behave the same. > > Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com> > Acked-by: Andrew Cooper <andrew.cooper3@citrix.com> Oops? Commit 1f0b1f5cce9d. Jan ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v6 2/2] ns16550: Add more device IDs for Intel LPSS UART 2022-05-20 9:42 ` Jan Beulich @ 2022-05-20 10:32 ` Marek Marczykowski-Górecki 0 siblings, 0 replies; 6+ messages in thread From: Marek Marczykowski-Górecki @ 2022-05-20 10:32 UTC (permalink / raw) To: Jan Beulich Cc: Andrew Cooper, George Dunlap, Julien Grall, Stefano Stabellini, Wei Liu, xen-devel [-- Attachment #1: Type: text/plain, Size: 725 bytes --] On Fri, May 20, 2022 at 11:42:37AM +0200, Jan Beulich wrote: > On 20.05.2022 10:53, Marek Marczykowski-Górecki wrote: > > This is purely based on the spec: > > - Intel 500 Series PCH: 635218-006 > > - Intel 600 Series PCH: 691222-001, 648364-003 > > > > This is tested only on TGL-LP added initially, but according to the > > spec, they should behave the same. > > > > Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com> > > Acked-by: Andrew Cooper <andrew.cooper3@citrix.com> > > Oops? Commit 1f0b1f5cce9d. Right, I haven't fetch new master. No changes here for several iterations, so everything is fine. -- Best Regards, Marek Marczykowski-Górecki Invisible Things Lab [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v6 1/2] ns16550: use poll mode if INTERRUPT_LINE is 0xff 2022-05-20 8:53 [PATCH v6 1/2] ns16550: use poll mode if INTERRUPT_LINE is 0xff Marek Marczykowski-Górecki 2022-05-20 8:53 ` [PATCH v6 2/2] ns16550: Add more device IDs for Intel LPSS UART Marek Marczykowski-Górecki @ 2022-05-20 9:47 ` Jan Beulich 2022-05-20 10:33 ` Marek Marczykowski-Górecki 1 sibling, 1 reply; 6+ messages in thread From: Jan Beulich @ 2022-05-20 9:47 UTC (permalink / raw) To: Marek Marczykowski-Górecki Cc: Roger Pau Monné, Andrew Cooper, George Dunlap, Julien Grall, Stefano Stabellini, Wei Liu, xen-devel On 20.05.2022 10:53, Marek Marczykowski-Górecki wrote: > Intel LPSS has INTERRUPT_LINE set to 0xff by default, that is declared > by the PCI Local Bus Specification Revision 3.0 (from 2004) as > "unknown"/"no connection". Fallback to poll mode in this case. > The 0xff handling is x86-specific, the surrounding code is guarded with > CONFIG_X86 anyway. > > Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com> > Reviewed-by: Roger Pau Monné <roger.pau@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> > Changes in v6: > - wrap the check in additional CONFIG_X86, with appropriate comment Thanks, albeit ... > --- a/xen/drivers/char/ns16550.c > +++ b/xen/drivers/char/ns16550.c > @@ -1238,6 +1238,17 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) > pci_conf_read8(PCI_SBDF(0, b, d, f), > PCI_INTERRUPT_LINE) : 0; > > +#ifdef CONFIG_X86 > + /* PCI Local Bus Specification Revision 3.0 defines 0xff value > + * as special only for X86 */ ... I'll have to remember to correct the style of the comment while committing ... > + if ( uart->irq == 0xff ) > + uart->irq = 0; > +#endif > + if ( !uart->irq ) > + printk(XENLOG_INFO > + "ns16550: %pp no legacy IRQ, using poll mode\n", ... and perhaps insert another colon after %pp here. Jan > + &PCI_SBDF(0, b, d, f)); > + > return 0; > } > } ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v6 1/2] ns16550: use poll mode if INTERRUPT_LINE is 0xff 2022-05-20 9:47 ` [PATCH v6 1/2] ns16550: use poll mode if INTERRUPT_LINE is 0xff Jan Beulich @ 2022-05-20 10:33 ` Marek Marczykowski-Górecki 0 siblings, 0 replies; 6+ messages in thread From: Marek Marczykowski-Górecki @ 2022-05-20 10:33 UTC (permalink / raw) To: Jan Beulich Cc: Roger Pau Monné, Andrew Cooper, George Dunlap, Julien Grall, Stefano Stabellini, Wei Liu, xen-devel [-- Attachment #1: Type: text/plain, Size: 1936 bytes --] On Fri, May 20, 2022 at 11:47:02AM +0200, Jan Beulich wrote: > On 20.05.2022 10:53, Marek Marczykowski-Górecki wrote: > > Intel LPSS has INTERRUPT_LINE set to 0xff by default, that is declared > > by the PCI Local Bus Specification Revision 3.0 (from 2004) as > > "unknown"/"no connection". Fallback to poll mode in this case. > > The 0xff handling is x86-specific, the surrounding code is guarded with > > CONFIG_X86 anyway. > > > > Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com> > > Reviewed-by: Roger Pau Monné <roger.pau@citrix.com> > > Reviewed-by: Jan Beulich <jbeulich@suse.com> Thanks. > > Changes in v6: > > - wrap the check in additional CONFIG_X86, with appropriate comment > > Thanks, albeit ... > > > --- a/xen/drivers/char/ns16550.c > > +++ b/xen/drivers/char/ns16550.c > > @@ -1238,6 +1238,17 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) > > pci_conf_read8(PCI_SBDF(0, b, d, f), > > PCI_INTERRUPT_LINE) : 0; > > > > +#ifdef CONFIG_X86 > > + /* PCI Local Bus Specification Revision 3.0 defines 0xff value > > + * as special only for X86 */ > > ... I'll have to remember to correct the style of the comment while > committing ... > > > + if ( uart->irq == 0xff ) > > + uart->irq = 0; > > +#endif > > + if ( !uart->irq ) > > + printk(XENLOG_INFO > > + "ns16550: %pp no legacy IRQ, using poll mode\n", > > ... and perhaps insert another colon after %pp here. Both fine with me, thanks! > Jan > > > + &PCI_SBDF(0, b, d, f)); > > + > > return 0; > > } > > } > -- Best Regards, Marek Marczykowski-Górecki Invisible Things Lab [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-05-20 10:34 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-05-20 8:53 [PATCH v6 1/2] ns16550: use poll mode if INTERRUPT_LINE is 0xff Marek Marczykowski-Górecki 2022-05-20 8:53 ` [PATCH v6 2/2] ns16550: Add more device IDs for Intel LPSS UART Marek Marczykowski-Górecki 2022-05-20 9:42 ` Jan Beulich 2022-05-20 10:32 ` Marek Marczykowski-Górecki 2022-05-20 9:47 ` [PATCH v6 1/2] ns16550: use poll mode if INTERRUPT_LINE is 0xff Jan Beulich 2022-05-20 10:33 ` Marek Marczykowski-Górecki
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