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From: Andrew Lunn <andrew@lunn.ch>
To: "Russell King (Oracle)" <linux@armlinux.org.uk>
Cc: "Heiner Kallweit" <hkallweit1@gmail.com>,
	"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
	"Alvin Šipraga" <alsi@bang-olufsen.dk>,
	"Claudiu Manoil" <claudiu.manoil@nxp.com>,
	"David S. Miller" <davem@davemloft.net>,
	"DENG Qingfang" <dqfext@gmail.com>,
	"Eric Dumazet" <edumazet@google.com>,
	"Florian Fainelli" <f.fainelli@gmail.com>,
	"George McCollister" <george.mccollister@gmail.com>,
	"Hauke Mehrtens" <hauke@hauke-m.de>,
	"Jakub Kicinski" <kuba@kernel.org>,
	"Kurt Kanzenbach" <kurt@linutronix.de>,
	"Landen Chao" <Landen.Chao@mediatek.com>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org,
	"Marek Behún" <kabel@kernel.org>,
	"Matthias Brugger" <matthias.bgg@gmail.com>,
	netdev@vger.kernel.org, "Paolo Abeni" <pabeni@redhat.com>,
	"Sean Wang" <sean.wang@mediatek.com>,
	UNGLinuxDriver@microchip.com,
	"Vivien Didelot" <vivien.didelot@gmail.com>,
	"Vladimir Oltean" <olteanv@gmail.com>,
	"Woojung Huh" <woojung.huh@microchip.com>
Subject: Re: [PATCH RFC net-next 0/4] net: dsa: always use phylink
Date: Wed, 29 Jun 2022 09:18:10 +0200	[thread overview]
Message-ID: <Yrv8snvIChmoNPwh@lunn.ch> (raw)
In-Reply-To: <YrtvoRhUK+4BneYC@shell.armlinux.org.uk>

> I should point out that if a DSA port can be programmed in software to
> support both SGMII and 1000baseX, this will end up selecting SGMII
> irrespective of what the hardware was wire-strapped to and how it was
> initially configured. Do we believe that would be acceptable?

I'm pretty sure the devel b board has 1000BaseX DSA links between its
two switches. Since both should end up SGMII that should be O.K.

Where we potentially have issues is 1000BaseX to the CPU. This is not
an issue for the Vybrid based boards, since they are fast Ethernet
only, but there are some boards with an IMX6 with 1G ethernet. I guess
they currently use 1000BaseX, and the CPU side of the link probably
has a fixed-link with phy-mode = 1000BaseX. So we might have an issue
there.

	Andrew


WARNING: multiple messages have this Message-ID (diff)
From: Andrew Lunn <andrew@lunn.ch>
To: "Russell King (Oracle)" <linux@armlinux.org.uk>
Cc: "Heiner Kallweit" <hkallweit1@gmail.com>,
	"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
	"Alvin Šipraga" <alsi@bang-olufsen.dk>,
	"Claudiu Manoil" <claudiu.manoil@nxp.com>,
	"David S. Miller" <davem@davemloft.net>,
	"DENG Qingfang" <dqfext@gmail.com>,
	"Eric Dumazet" <edumazet@google.com>,
	"Florian Fainelli" <f.fainelli@gmail.com>,
	"George McCollister" <george.mccollister@gmail.com>,
	"Hauke Mehrtens" <hauke@hauke-m.de>,
	"Jakub Kicinski" <kuba@kernel.org>,
	"Kurt Kanzenbach" <kurt@linutronix.de>,
	"Landen Chao" <Landen.Chao@mediatek.com>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org,
	"Marek Behún" <kabel@kernel.org>,
	"Matthias Brugger" <matthias.bgg@gmail.com>,
	netdev@vger.kernel.org, "Paolo Abeni" <pabeni@redhat.com>,
	"Sean Wang" <sean.wang@mediatek.com>,
	UNGLinuxDriver@microchip.com,
	"Vivien Didelot" <vivien.didelot@gmail.com>,
	"Vladimir Oltean" <olteanv@gmail.com>,
	"Woojung Huh" <woojung.huh@microchip.com>
Subject: Re: [PATCH RFC net-next 0/4] net: dsa: always use phylink
Date: Wed, 29 Jun 2022 09:18:10 +0200	[thread overview]
Message-ID: <Yrv8snvIChmoNPwh@lunn.ch> (raw)
In-Reply-To: <YrtvoRhUK+4BneYC@shell.armlinux.org.uk>

> I should point out that if a DSA port can be programmed in software to
> support both SGMII and 1000baseX, this will end up selecting SGMII
> irrespective of what the hardware was wire-strapped to and how it was
> initially configured. Do we believe that would be acceptable?

I'm pretty sure the devel b board has 1000BaseX DSA links between its
two switches. Since both should end up SGMII that should be O.K.

Where we potentially have issues is 1000BaseX to the CPU. This is not
an issue for the Vybrid based boards, since they are fast Ethernet
only, but there are some boards with an IMX6 with 1G ethernet. I guess
they currently use 1000BaseX, and the CPU side of the link probably
has a fixed-link with phy-mode = 1000BaseX. So we might have an issue
there.

	Andrew

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-06-29  7:19 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-24 11:41 [PATCH RFC net-next 0/4] net: dsa: always use phylink Russell King (Oracle)
2022-06-24 11:41 ` Russell King (Oracle)
2022-06-24 11:41 ` [PATCH RFC net-next 1/4] net: dsa: add support for retrieving the interface mode Russell King (Oracle)
2022-06-24 11:41   ` Russell King (Oracle)
2022-06-24 11:41 ` [PATCH RFC net-next 2/4] net: dsa: mv88e6xxx: report the default interface mode for the port Russell King (Oracle)
2022-06-24 11:41   ` Russell King (Oracle)
2022-06-24 11:42 ` [PATCH RFC net-next 3/4] net: phylink: add phylink_set_max_fixed_link() Russell King (Oracle)
2022-06-24 11:42   ` Russell King (Oracle)
2022-06-25  2:58   ` kernel test robot
2022-06-24 11:42 ` [PATCH RFC net-next 4/4] net: dsa: always use phylink for CPU and DSA ports Russell King (Oracle)
2022-06-24 11:42   ` Russell King (Oracle)
2022-06-28 21:16 ` [PATCH RFC net-next 0/4] net: dsa: always use phylink Russell King (Oracle)
2022-06-28 21:16   ` Russell King (Oracle)
2022-06-29  7:18   ` Andrew Lunn [this message]
2022-06-29  7:18     ` Andrew Lunn
2022-06-29  9:27     ` Marek Behún
2022-06-29  9:27       ` Marek Behún
2022-06-29  9:34       ` Russell King (Oracle)
2022-06-29  9:34         ` Russell King (Oracle)
2022-06-29  9:42         ` Marek Behún
2022-06-29  9:42           ` Marek Behún
2022-06-29  9:43     ` Russell King (Oracle)
2022-06-29  9:43       ` Russell King (Oracle)
2022-06-29 10:10       ` Marek Behún
2022-06-29 10:10         ` Marek Behún
2022-06-29 12:41         ` Russell King (Oracle)
2022-06-29 12:41           ` Russell King (Oracle)

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