From: Fan Ni <nifan.cxl@gmail.com>
To: Shradha Todi <shradha.t@samsung.com>
Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-perf-users@vger.kernel.org,
manivannan.sadhasivam@linaro.org, lpieralisi@kernel.org,
kw@linux.com, robh@kernel.org, bhelgaas@google.com,
jingoohan1@gmail.com, Jonathan.Cameron@huawei.com,
nifan.cxl@gmail.com, a.manzanares@samsung.com,
pankaj.dubey@samsung.com, cassel@kernel.org, 18255117159@163.com,
xueshuai@linux.alibaba.com, renyu.zj@linux.alibaba.com,
will@kernel.org, mark.rutland@arm.com
Subject: Re: [PATCH v7 1/5] perf/dwc_pcie: Move common DWC struct definitions to 'pcie-dwc.h'
Date: Mon, 3 Mar 2025 09:19:38 -0800 [thread overview]
Message-ID: <Z8XkqnQir1CfilvM@debian> (raw)
In-Reply-To: <20250221131548.59616-2-shradha.t@samsung.com>
On Fri, Feb 21, 2025 at 06:45:44PM +0530, Shradha Todi wrote:
> From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>
> Since these are common to all Desginware PCIe IPs, move them to a new
> header 'pcie-dwc.h', so that other drivers like debugfs, perf and sysfs
> could make use of them.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Signed-off-by: Shradha Todi <shradha.t@samsung.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
> ---
> MAINTAINERS | 1 +
> drivers/perf/dwc_pcie_pmu.c | 25 +++----------------------
> include/linux/pcie-dwc.h | 34 ++++++++++++++++++++++++++++++++++
> 3 files changed, 38 insertions(+), 22 deletions(-)
> create mode 100644 include/linux/pcie-dwc.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 3864d473f52f..6474a2d83de4 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -18167,6 +18167,7 @@ S: Maintained
> F: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
> F: Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
> F: drivers/pci/controller/dwc/*designware*
> +F: include/linux/pcie-dwc.h
>
> PCI DRIVER FOR TI DRA7XX/J721E
> M: Vignesh Raghavendra <vigneshr@ti.com>
> diff --git a/drivers/perf/dwc_pcie_pmu.c b/drivers/perf/dwc_pcie_pmu.c
> index cccecae9823f..da30f2c2d674 100644
> --- a/drivers/perf/dwc_pcie_pmu.c
> +++ b/drivers/perf/dwc_pcie_pmu.c
> @@ -13,6 +13,7 @@
> #include <linux/errno.h>
> #include <linux/kernel.h>
> #include <linux/list.h>
> +#include <linux/pcie-dwc.h>
> #include <linux/perf_event.h>
> #include <linux/pci.h>
> #include <linux/platform_device.h>
> @@ -99,26 +100,6 @@ struct dwc_pcie_dev_info {
> struct list_head dev_node;
> };
>
> -struct dwc_pcie_pmu_vsec_id {
> - u16 vendor_id;
> - u16 vsec_id;
> - u8 vsec_rev;
> -};
> -
> -/*
> - * VSEC IDs are allocated by the vendor, so a given ID may mean different
> - * things to different vendors. See PCIe r6.0, sec 7.9.5.2.
> - */
> -static const struct dwc_pcie_pmu_vsec_id dwc_pcie_pmu_vsec_ids[] = {
> - { .vendor_id = PCI_VENDOR_ID_ALIBABA,
> - .vsec_id = 0x02, .vsec_rev = 0x4 },
> - { .vendor_id = PCI_VENDOR_ID_AMPERE,
> - .vsec_id = 0x02, .vsec_rev = 0x4 },
> - { .vendor_id = PCI_VENDOR_ID_QCOM,
> - .vsec_id = 0x02, .vsec_rev = 0x4 },
> - {} /* terminator */
> -};
> -
> static ssize_t cpumask_show(struct device *dev,
> struct device_attribute *attr,
> char *buf)
> @@ -529,14 +510,14 @@ static void dwc_pcie_unregister_pmu(void *data)
>
> static u16 dwc_pcie_des_cap(struct pci_dev *pdev)
> {
> - const struct dwc_pcie_pmu_vsec_id *vid;
> + const struct dwc_pcie_vsec_id *vid;
> u16 vsec;
> u32 val;
>
> if (!pci_is_pcie(pdev) || !(pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT))
> return 0;
>
> - for (vid = dwc_pcie_pmu_vsec_ids; vid->vendor_id; vid++) {
> + for (vid = dwc_pcie_rasdes_vsec_ids; vid->vendor_id; vid++) {
> vsec = pci_find_vsec_capability(pdev, vid->vendor_id,
> vid->vsec_id);
> if (vsec) {
> diff --git a/include/linux/pcie-dwc.h b/include/linux/pcie-dwc.h
> new file mode 100644
> index 000000000000..40f3545731c8
> --- /dev/null
> +++ b/include/linux/pcie-dwc.h
> @@ -0,0 +1,34 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2021-2023 Alibaba Inc.
> + *
> + * Copyright 2025 Linaro Ltd.
> + * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> + */
> +
> +#ifndef LINUX_PCIE_DWC_H
> +#define LINUX_PCIE_DWC_H
> +
> +#include <linux/pci_ids.h>
> +
> +struct dwc_pcie_vsec_id {
> + u16 vendor_id;
> + u16 vsec_id;
> + u8 vsec_rev;
> +};
> +
> +/*
> + * VSEC IDs are allocated by the vendor, so a given ID may mean different
> + * things to different vendors. See PCIe r6.0, sec 7.9.5.2.
> + */
> +static const struct dwc_pcie_vsec_id dwc_pcie_rasdes_vsec_ids[] = {
> + { .vendor_id = PCI_VENDOR_ID_ALIBABA,
> + .vsec_id = 0x02, .vsec_rev = 0x4 },
> + { .vendor_id = PCI_VENDOR_ID_AMPERE,
> + .vsec_id = 0x02, .vsec_rev = 0x4 },
> + { .vendor_id = PCI_VENDOR_ID_QCOM,
> + .vsec_id = 0x02, .vsec_rev = 0x4 },
> + {} /* terminator */
> +};
> +
> +#endif /* LINUX_PCIE_DWC_H */
> --
> 2.17.1
>
next prev parent reply other threads:[~2025-03-03 17:21 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20250221132011epcas5p4dea1e9ae5c09afaabcd1822f3a7d15c5@epcas5p4.samsung.com>
2025-02-21 13:15 ` [PATCH v7 0/5] Add support for debugfs based RAS DES feature in PCIe DW Shradha Todi
2025-02-21 13:15 ` [PATCH v7 1/5] perf/dwc_pcie: Move common DWC struct definitions to 'pcie-dwc.h' Shradha Todi
2025-02-25 14:47 ` Krzysztof Wilczyński
2025-02-26 1:55 ` Shuai Xue
2025-02-26 6:48 ` Krzysztof Wilczyński
2025-03-03 17:19 ` Fan Ni [this message]
2025-02-21 13:15 ` [PATCH v7 2/5] PCI: dwc: Add helper to find the Vendor Specific Extended Capability (VSEC) Shradha Todi
2025-03-03 17:22 ` Fan Ni
2025-02-21 13:15 ` [PATCH v7 3/5] Add debugfs based silicon debug support in DWC Shradha Todi
2025-02-23 8:51 ` Manivannan Sadhasivam
2025-03-03 17:48 ` Fan Ni
2025-03-03 19:46 ` Krzysztof Wilczyński
2025-03-03 20:50 ` Fan Ni
2025-03-04 6:44 ` Krzysztof Wilczyński
2025-03-04 14:54 ` Geert Uytterhoeven
2025-03-04 14:57 ` Geert Uytterhoeven
2025-03-04 15:46 ` Krzysztof Wilczyński
2025-03-04 16:52 ` Shradha Todi
2025-03-05 7:44 ` 'Krzysztof Wilczyński'
2025-03-05 9:04 ` Shradha Todi
2025-03-04 17:11 ` Manivannan Sadhasivam
2025-03-04 17:58 ` Krzysztof Wilczyński
2025-03-05 17:38 ` Bjorn Helgaas
2025-03-05 18:28 ` Manivannan Sadhasivam
2025-03-05 19:09 ` Krzysztof Wilczyński
2025-03-05 21:57 ` Krzysztof Wilczyński
2025-03-06 8:22 ` Geert Uytterhoeven
2025-03-06 9:02 ` Krzysztof Wilczyński
2025-03-07 9:37 ` Shradha Todi
2025-03-04 15:18 ` Manivannan Sadhasivam
2025-02-21 13:15 ` [PATCH v7 4/5] Add debugfs based error injection " Shradha Todi
2025-02-23 8:53 ` Manivannan Sadhasivam
2025-03-03 9:52 ` Krzysztof Wilczyński
2025-03-04 6:50 ` Krzysztof Wilczyński
2025-03-04 15:29 ` Manivannan Sadhasivam
2025-03-04 15:35 ` Krzysztof Wilczyński
2025-03-04 17:00 ` Shradha Todi
2025-03-05 7:26 ` 'Krzysztof Wilczyński'
2025-03-03 17:53 ` Fan Ni
2025-02-21 13:15 ` [PATCH v7 5/5] Add debugfs based statistical counter " Shradha Todi
2025-02-23 8:54 ` Manivannan Sadhasivam
2025-03-03 18:02 ` Fan Ni
2025-03-03 19:42 ` Krzysztof Wilczyński
2025-03-03 21:03 ` Fan Ni
2025-03-04 15:32 ` Manivannan Sadhasivam
2025-03-04 17:10 ` Shradha Todi
2025-03-05 4:26 ` Fan Ni
2025-03-07 9:47 ` Shradha Todi
2025-02-24 17:08 ` [PATCH v7 0/5] Add support for debugfs based RAS DES feature in PCIe DW Niklas Cassel
2025-02-25 8:28 ` Manivannan Sadhasivam
2025-02-25 14:33 ` Krzysztof Wilczyński
2025-02-25 14:35 ` Niklas Cassel
2025-02-25 17:15 ` Manivannan Sadhasivam
2025-02-25 14:30 ` Krzysztof Wilczyński
2025-03-03 19:51 ` Krzysztof Wilczyński
2025-02-28 11:43 ` Hrishikesh Deleep
2025-03-03 20:00 ` Krzysztof Wilczyński
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