From: John Watts <contact@jookia.org>
To: linux-sunxi@lists.linux.dev
Cc: Wolfgang Grandegger <wg@grandegger.com>,
Marc Kleine-Budde <mkl@pengutronix.de>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-can@vger.kernel.org, netdev@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 2/4] riscv: dts: allwinner: d1: Add CAN controller nodes
Date: Sun, 23 Jul 2023 19:18:33 +1000 [thread overview]
Message-ID: <ZLzwaQlS-l_KKpUX@titan> (raw)
In-Reply-To: <20230721221552.1973203-4-contact@jookia.org>
On Sat, Jul 22, 2023 at 08:15:51AM +1000, John Watts wrote:
> ...
> + /omit-if-no-ref/
> + can0_pins: can0-pins {
> + pins = "PB2", "PB3";
> + function = "can0";
> + };
> ...
> + can0: can@2504000 {
> + compatible = "allwinner,sun20i-d1-can";
> + reg = <0x02504000 0x400>;
> + interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CAN0>;
> + resets = <&ccu RST_BUS_CAN0>;
> + status = "disabled";
> + };
Just a quick late night question to people with more knowledge than me:
These chips only have one pinctrl configuration for can0 and can1. Should the
can nodes have this pre-set instead of the board dts doing this?
I see this happening in sun4i-a10.dtsi for instance, but it also seems like it
could become a problem when it comes to re-using the dtsi for newer chip variants.
John.
WARNING: multiple messages have this Message-ID (diff)
From: John Watts <contact@jookia.org>
To: linux-sunxi@lists.linux.dev
Cc: Wolfgang Grandegger <wg@grandegger.com>,
Marc Kleine-Budde <mkl@pengutronix.de>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-can@vger.kernel.org, netdev@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 2/4] riscv: dts: allwinner: d1: Add CAN controller nodes
Date: Sun, 23 Jul 2023 19:18:33 +1000 [thread overview]
Message-ID: <ZLzwaQlS-l_KKpUX@titan> (raw)
In-Reply-To: <20230721221552.1973203-4-contact@jookia.org>
On Sat, Jul 22, 2023 at 08:15:51AM +1000, John Watts wrote:
> ...
> + /omit-if-no-ref/
> + can0_pins: can0-pins {
> + pins = "PB2", "PB3";
> + function = "can0";
> + };
> ...
> + can0: can@2504000 {
> + compatible = "allwinner,sun20i-d1-can";
> + reg = <0x02504000 0x400>;
> + interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CAN0>;
> + resets = <&ccu RST_BUS_CAN0>;
> + status = "disabled";
> + };
Just a quick late night question to people with more knowledge than me:
These chips only have one pinctrl configuration for can0 and can1. Should the
can nodes have this pre-set instead of the board dts doing this?
I see this happening in sun4i-a10.dtsi for instance, but it also seems like it
could become a problem when it comes to re-using the dtsi for newer chip variants.
John.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: John Watts <contact@jookia.org>
To: linux-sunxi@lists.linux.dev
Cc: Wolfgang Grandegger <wg@grandegger.com>,
Marc Kleine-Budde <mkl@pengutronix.de>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-can@vger.kernel.org, netdev@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 2/4] riscv: dts: allwinner: d1: Add CAN controller nodes
Date: Sun, 23 Jul 2023 19:18:33 +1000 [thread overview]
Message-ID: <ZLzwaQlS-l_KKpUX@titan> (raw)
In-Reply-To: <20230721221552.1973203-4-contact@jookia.org>
On Sat, Jul 22, 2023 at 08:15:51AM +1000, John Watts wrote:
> ...
> + /omit-if-no-ref/
> + can0_pins: can0-pins {
> + pins = "PB2", "PB3";
> + function = "can0";
> + };
> ...
> + can0: can@2504000 {
> + compatible = "allwinner,sun20i-d1-can";
> + reg = <0x02504000 0x400>;
> + interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CAN0>;
> + resets = <&ccu RST_BUS_CAN0>;
> + status = "disabled";
> + };
Just a quick late night question to people with more knowledge than me:
These chips only have one pinctrl configuration for can0 and can1. Should the
can nodes have this pre-set instead of the board dts doing this?
I see this happening in sun4i-a10.dtsi for instance, but it also seems like it
could become a problem when it comes to re-using the dtsi for newer chip variants.
John.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-07-23 9:19 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-21 22:15 [PATCH v2 0/4] Add support for Allwinner D1 CAN controllers John Watts
2023-07-21 22:15 ` John Watts
2023-07-21 22:15 ` John Watts
2023-07-21 22:15 ` [PATCH v2 1/4] dt-bindings: net: can: Add support for Allwinner D1 CAN controller John Watts
2023-07-21 22:15 ` John Watts
2023-07-21 22:15 ` John Watts
2023-07-22 9:29 ` Krzysztof Kozlowski
2023-07-22 9:29 ` Krzysztof Kozlowski
2023-07-22 9:29 ` Krzysztof Kozlowski
2023-07-21 22:15 ` [PATCH v2 2/4] riscv: dts: allwinner: d1: Add CAN controller nodes John Watts
2023-07-21 22:15 ` John Watts
2023-07-21 22:15 ` John Watts
2023-07-23 9:18 ` John Watts [this message]
2023-07-23 9:18 ` John Watts
2023-07-23 9:18 ` John Watts
2023-07-30 22:03 ` Jernej Škrabec
2023-07-30 22:03 ` Jernej Škrabec
2023-07-30 22:03 ` Jernej Škrabec
2023-07-31 2:38 ` John Watts
2023-07-31 2:38 ` John Watts
2023-07-31 2:38 ` John Watts
2023-08-05 16:40 ` Maksim Kiselev
2023-08-05 16:40 ` Maksim Kiselev
2023-08-05 16:40 ` Maksim Kiselev
2023-08-05 16:51 ` John Watts
2023-08-05 16:51 ` John Watts
2023-08-05 16:51 ` John Watts
2023-08-05 17:49 ` Jernej Škrabec
2023-08-05 17:49 ` Jernej Škrabec
2023-08-05 17:49 ` Jernej Škrabec
2023-08-06 6:33 ` John Watts
2023-08-06 6:33 ` John Watts
2023-08-06 6:33 ` John Watts
2023-08-06 11:42 ` Jernej Škrabec
2023-08-06 11:42 ` Jernej Škrabec
2023-08-06 11:42 ` Jernej Škrabec
2023-08-07 7:16 ` Marc Kleine-Budde
2023-08-07 7:16 ` Marc Kleine-Budde
2023-08-07 7:16 ` Marc Kleine-Budde
2023-08-07 7:30 ` Marc Kleine-Budde
2023-08-07 7:30 ` Marc Kleine-Budde
2023-08-07 7:30 ` Marc Kleine-Budde
2023-07-21 22:15 ` [PATCH v2 3/4] can: sun4i_can: Add acceptance register quirk John Watts
2023-07-21 22:15 ` John Watts
2023-07-21 22:15 ` John Watts
2023-07-21 22:15 ` [PATCH v2 4/4] can: sun4i_can: Add support for the Allwinner D1 John Watts
2023-07-21 22:15 ` John Watts
2023-07-21 22:15 ` John Watts
2023-08-22 12:30 ` Geert Uytterhoeven
2023-08-22 12:30 ` Geert Uytterhoeven
2023-08-22 12:30 ` Geert Uytterhoeven
2023-08-23 3:16 ` John Watts
2023-08-23 3:16 ` John Watts
2023-08-23 3:16 ` John Watts
2023-07-24 8:27 ` [PATCH v2 0/4] Add support for Allwinner D1 CAN controllers Marc Kleine-Budde
2023-07-24 8:27 ` Marc Kleine-Budde
2023-09-01 16:25 ` patchwork-bot+linux-riscv
2023-09-01 16:25 ` patchwork-bot+linux-riscv
2023-09-01 16:25 ` patchwork-bot+linux-riscv
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