From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [Intel-xe] [PATCH 1/3] drm/xe: Add a couple of pcode helpers
Date: Fri, 1 Sep 2023 16:34:46 -0400 [thread overview]
Message-ID: <ZPJK5iahuG41pvcF@intel.com> (raw)
In-Reply-To: <20230901121545.361436-2-sujaritha.sundaresan@intel.com>
On Fri, Sep 01, 2023 at 05:45:43PM +0530, Sujaritha Sundaresan wrote:
> Some pcode commands take additional sub-commands and parameters. Add a
> couple of helpers to help formatting these commands to improve code
> readability.
>
> Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> ---
> drivers/gpu/drm/xe/xe_pcode.c | 28 ++++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_pcode.h | 3 +++
> 2 files changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
> index 7f1bf2297f51..e45169f47500 100644
> --- a/drivers/gpu/drm/xe/xe_pcode.c
> +++ b/drivers/gpu/drm/xe/xe_pcode.c
> @@ -104,6 +104,34 @@ int xe_pcode_read(struct xe_gt *gt, u32 mbox, u32 *val, u32 *val1)
> return err;
> }
>
a doc would be required...
> +int xe_pcode_read_p(struct xe_gt *gt, u32 mbcmd, u32 p1, u32 p2, u32 *val)
a better name would be nice....
> +{
> + u32 mbox;
> + int err;
> +
> + mbox = REG_FIELD_PREP(PCODE_MB_COMMAND, mbcmd)
> + | REG_FIELD_PREP(PCODE_MB_PARAM1, p1)
> + | REG_FIELD_PREP(PCODE_MB_PARAM2, p2);
> +
> + err = xe_pcode_read(gt, mbox, val, NULL);
but why not simply modifying the existent one to accept 2 params?
int xe_pcode_read(struct xe_gt *gt, u32 mbox_param1, u32 mbox_param2,
u32 *val, u32 *val1)
and the equivalent write...
oh, and while doing that, could you please add the missing documentation
to these 2 functions?
Thanks,
Rodrigo.
> +
> + return err;
> +}
> +
> +int xe_pcode_write_p(struct xe_gt *gt, u32 mbcmd, u32 p1, u32 p2, u32 val)
> +{
> + u32 mbox;
> + int err;
> +
> + mbox = REG_FIELD_PREP(PCODE_MB_COMMAND, mbcmd)
> + | REG_FIELD_PREP(PCODE_MB_PARAM1, p1)
> + | REG_FIELD_PREP(PCODE_MB_PARAM2, p2);
> +
> + err = xe_pcode_write(gt, mbox, val);
> +
> + return err;
> +}
> +
> static int xe_pcode_try_request(struct xe_gt *gt, u32 mbox,
> u32 request, u32 reply_mask, u32 reply,
> u32 *status, bool atomic, int timeout_us)
> diff --git a/drivers/gpu/drm/xe/xe_pcode.h b/drivers/gpu/drm/xe/xe_pcode.h
> index 3b4aa8c1a3ba..8d4103afd7e0 100644
> --- a/drivers/gpu/drm/xe/xe_pcode.h
> +++ b/drivers/gpu/drm/xe/xe_pcode.h
> @@ -19,6 +19,9 @@ int xe_pcode_write_timeout(struct xe_gt *gt, u32 mbox, u32 val,
> #define xe_pcode_write(gt, mbox, val) \
> xe_pcode_write_timeout(gt, mbox, val, 1)
>
> +int xe_pcode_read_p(struct xe_gt *gt, u32 mbcmd, u32 p1, u32 p2, u32 *val);
> +int xe_pcode_write_p(struct xe_gt *gt, u32 mbcmd, u32 p1, u32 p2, u32 val);
> +
> int xe_pcode_request(struct xe_gt *gt, u32 mbox, u32 request,
> u32 reply_mask, u32 reply, int timeout_ms);
>
> --
> 2.25.1
>
next prev parent reply other threads:[~2023-09-01 20:34 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-01 12:15 [Intel-xe] [PATCH 0/3] Add some performance and frequency sysfs nodes Sujaritha Sundaresan
2023-09-01 12:08 ` [Intel-xe] ✗ CI.Patch_applied: failure for " Patchwork
2023-09-01 12:15 ` [Intel-xe] [PATCH 1/3] drm/xe: Add a couple of pcode helpers Sujaritha Sundaresan
2023-09-01 20:34 ` Rodrigo Vivi [this message]
2023-09-03 13:30 ` Sundaresan, Sujaritha
2023-09-12 5:08 ` Sundaresan, Sujaritha
2023-09-12 14:33 ` Rodrigo Vivi
2023-09-13 4:03 ` Sundaresan, Sujaritha
2023-09-25 8:13 ` Sundaresan, Sujaritha
2023-09-26 17:39 ` Rodrigo Vivi
2023-09-01 12:15 ` [Intel-xe] [PATCH 2/3] drm/xe: Add base performance sysfs attributes Sujaritha Sundaresan
2023-09-01 20:35 ` Rodrigo Vivi
2023-09-03 13:36 ` Sundaresan, Sujaritha
2023-09-12 8:48 ` Sundaresan, Sujaritha
2023-09-12 14:34 ` Rodrigo Vivi
2023-09-13 4:01 ` Sundaresan, Sujaritha
2023-09-01 12:15 ` [Intel-xe] [PATCH 3/3, v2] drm/xe: Sysfs entries to query vram fused min, max frequency Sujaritha Sundaresan
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