From: Peter Xu <peterx@redhat.com>
To: Ethan Chen <ethan84@andestech.com>
Cc: qemu-devel@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
"David Hildenbrand" <david@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: Re: [PATCH 2/6] system/physmem: IOMMU: Invoke the translate_size function if it is implemented
Date: Wed, 25 Oct 2023 11:14:42 -0400 [thread overview]
Message-ID: <ZTkw4itrYANXm4qR@x1n> (raw)
In-Reply-To: <20231025051430.493079-3-ethan84@andestech.com>
On Wed, Oct 25, 2023 at 01:14:26PM +0800, Ethan Chen wrote:
> Signed-off-by: Ethan Chen <ethan84@andestech.com>
> ---
> system/physmem.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/system/physmem.c b/system/physmem.c
> index fc2b0fee01..53b6ab735c 100644
> --- a/system/physmem.c
> +++ b/system/physmem.c
> @@ -432,8 +432,13 @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm
> iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);
> }
>
> - iotlb = imrc->translate(iommu_mr, addr, is_write ?
> - IOMMU_WO : IOMMU_RO, iommu_idx);
> + if (imrc->translate_size) {
> + iotlb = imrc->translate_size(iommu_mr, addr, *plen_out, is_write ?
> + IOMMU_WO : IOMMU_RO, iommu_idx);
> + } else {
> + iotlb = imrc->translate(iommu_mr, addr, is_write ?
> + IOMMU_WO : IOMMU_RO, iommu_idx);
> + }
Currently the translation size is encoded in iotlb.addr_mask. Can riscv do
the same?
For example, lookup addr in match_entry_md() ranges, report size back into
iotlb.addr_mask, rather than enforcing *plen_out range always resides in
one translation only.
IMHO it's actually legal if *plen_out covers more than one IOMMU
translations. QEMU memory core should have taken care of that by
separately translate the ranges and apply RW on top. With current proposal
of translate_size() I think it'll fail instead, which is not wanted.
Thanks,
--
Peter Xu
next prev parent reply other threads:[~2023-10-25 15:16 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-25 5:14 [PATCH 0/6] Support RISC-V IOPMP Ethan Chen via
2023-10-25 5:14 ` Ethan Chen
2023-10-25 5:14 ` [PATCH 1/6] exec/memory: Introduce the translate_size function within the IOMMU class Ethan Chen via
2023-10-25 5:14 ` Ethan Chen
2023-10-25 14:56 ` David Hildenbrand
2023-10-26 7:14 ` Ethan Chen via
2023-10-26 7:14 ` Ethan Chen
2023-10-26 7:26 ` David Hildenbrand
2023-10-25 5:14 ` [PATCH 2/6] system/physmem: IOMMU: Invoke the translate_size function if it is implemented Ethan Chen via
2023-10-25 5:14 ` Ethan Chen
2023-10-25 15:14 ` Peter Xu [this message]
2023-10-26 6:48 ` Ethan Chen via
2023-10-26 6:48 ` Ethan Chen
2023-10-26 14:20 ` Peter Xu
2023-10-27 3:28 ` Ethan Chen via
2023-10-27 3:28 ` Ethan Chen
2023-10-27 16:02 ` Peter Xu
2023-10-27 16:13 ` Peter Xu
2023-10-30 6:00 ` Ethan Chen via
2023-10-30 6:00 ` Ethan Chen
2023-10-30 15:02 ` Peter Xu
2023-10-31 8:52 ` Ethan Chen via
2023-10-31 8:52 ` Ethan Chen
2023-10-25 5:14 ` [PATCH 3/6] exec/memattrs: Add iopmp source id to MemTxAttrs Ethan Chen via
2023-10-25 5:14 ` Ethan Chen
2023-10-25 5:14 ` [PATCH 4/6] Add RISC-V IOPMP support Ethan Chen via
2023-10-25 5:14 ` Ethan Chen
2023-10-25 5:14 ` [PATCH 5/6] hw/dma: Add Andes ATCDMAC300 support Ethan Chen via
2023-10-25 5:14 ` Ethan Chen
2023-10-25 5:14 ` [PATCH 6/6] hw/riscv/virt: Add IOPMP support Ethan Chen via
2023-10-25 5:14 ` Ethan Chen
2023-10-25 5:14 ` Ethan Chen via
2023-10-26 12:02 ` [PATCH 0/6] Support RISC-V IOPMP Ethan Chen via
2023-10-26 12:02 ` Ethan Chen
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