From: Charlie Jenkins <charlie@rivosinc.com>
To: Eric Biggers <ebiggers@kernel.org>
Cc: "Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Jisheng Zhang" <jszhang@kernel.org>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] riscv: Disable misaligned access probe when CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
Date: Fri, 2 Feb 2024 15:13:31 -0800 [thread overview]
Message-ID: <Zb13G6ESgxCa4vhG@ghost> (raw)
In-Reply-To: <20240202230101.GB2055@sol.localdomain>
On Fri, Feb 02, 2024 at 03:01:01PM -0800, Eric Biggers wrote:
> On Thu, Feb 01, 2024 at 03:30:46PM -0800, Charlie Jenkins wrote:
> > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> > index eb3ac304fc42..3a29d8e30e05 100644
> > --- a/arch/riscv/include/asm/cpufeature.h
> > +++ b/arch/riscv/include/asm/cpufeature.h
> > @@ -51,6 +51,7 @@ static inline bool check_unaligned_access_emulated(int cpu)
> > static inline void unaligned_emulation_finish(void) {}
> > #endif
> >
> > +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
>
> #ifdef..#else..#endif is more readable than #ifndef..#else..#endif.
>
> > diff --git a/arch/riscv/include/asm/misaligned_access_speed.h b/arch/riscv/include/asm/misaligned_access_speed.h
> > new file mode 100644
> > index 000000000000..81df2aa6fa6b
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/misaligned_access_speed.h
>
> This new header file isn't included from anywhere.
>
I thought I deleted that...
> > diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
> > index f71910718053..8be7f17da9ab 100644
> > --- a/arch/riscv/kernel/Makefile
> > +++ b/arch/riscv/kernel/Makefile
> > @@ -62,6 +62,9 @@ obj-y += tests/
> > obj-$(CONFIG_MMU) += vdso.o vdso/
> >
> > obj-$(CONFIG_RISCV_MISALIGNED) += traps_misaligned.o
> > +ifneq ($(RISCV_EFFICIENT_UNALIGNED_ACCESS), y)
> > +obj-y += misaligned_access_speed.o
> > +endif
>
> CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
>
> > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> > index a7c56b41efd2..3f1a6edfdb08 100644
> > --- a/arch/riscv/kernel/sys_hwprobe.c
> > +++ b/arch/riscv/kernel/sys_hwprobe.c
> > @@ -149,6 +149,7 @@ static bool hwprobe_ext0_has(const struct cpumask *cpus, unsigned long ext)
> >
> > static u64 hwprobe_misaligned(const struct cpumask *cpus)
> > {
> > +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
> > int cpu;
> > u64 perf = -1ULL;
> >
> > @@ -168,6 +169,9 @@ static u64 hwprobe_misaligned(const struct cpumask *cpus)
> > return RISCV_HWPROBE_MISALIGNED_UNKNOWN;
> >
> > return perf;
> > +#else
> > + return RISCV_HWPROBE_MISALIGNED_FAST;
> > +#endif
>
> #ifdef..#else..#endif is more readable than #ifndef..#else..#endif.
>
> - Eric
Thanks for pointing these out, I will send a v3.
- Charlie
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WARNING: multiple messages have this Message-ID (diff)
From: Charlie Jenkins <charlie@rivosinc.com>
To: Eric Biggers <ebiggers@kernel.org>
Cc: "Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Jisheng Zhang" <jszhang@kernel.org>,
"Evan Green" <evan@rivosinc.com>,
"Clément Léger" <cleger@rivosinc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] riscv: Disable misaligned access probe when CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
Date: Fri, 2 Feb 2024 15:13:31 -0800 [thread overview]
Message-ID: <Zb13G6ESgxCa4vhG@ghost> (raw)
In-Reply-To: <20240202230101.GB2055@sol.localdomain>
On Fri, Feb 02, 2024 at 03:01:01PM -0800, Eric Biggers wrote:
> On Thu, Feb 01, 2024 at 03:30:46PM -0800, Charlie Jenkins wrote:
> > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> > index eb3ac304fc42..3a29d8e30e05 100644
> > --- a/arch/riscv/include/asm/cpufeature.h
> > +++ b/arch/riscv/include/asm/cpufeature.h
> > @@ -51,6 +51,7 @@ static inline bool check_unaligned_access_emulated(int cpu)
> > static inline void unaligned_emulation_finish(void) {}
> > #endif
> >
> > +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
>
> #ifdef..#else..#endif is more readable than #ifndef..#else..#endif.
>
> > diff --git a/arch/riscv/include/asm/misaligned_access_speed.h b/arch/riscv/include/asm/misaligned_access_speed.h
> > new file mode 100644
> > index 000000000000..81df2aa6fa6b
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/misaligned_access_speed.h
>
> This new header file isn't included from anywhere.
>
I thought I deleted that...
> > diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
> > index f71910718053..8be7f17da9ab 100644
> > --- a/arch/riscv/kernel/Makefile
> > +++ b/arch/riscv/kernel/Makefile
> > @@ -62,6 +62,9 @@ obj-y += tests/
> > obj-$(CONFIG_MMU) += vdso.o vdso/
> >
> > obj-$(CONFIG_RISCV_MISALIGNED) += traps_misaligned.o
> > +ifneq ($(RISCV_EFFICIENT_UNALIGNED_ACCESS), y)
> > +obj-y += misaligned_access_speed.o
> > +endif
>
> CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
>
> > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> > index a7c56b41efd2..3f1a6edfdb08 100644
> > --- a/arch/riscv/kernel/sys_hwprobe.c
> > +++ b/arch/riscv/kernel/sys_hwprobe.c
> > @@ -149,6 +149,7 @@ static bool hwprobe_ext0_has(const struct cpumask *cpus, unsigned long ext)
> >
> > static u64 hwprobe_misaligned(const struct cpumask *cpus)
> > {
> > +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
> > int cpu;
> > u64 perf = -1ULL;
> >
> > @@ -168,6 +169,9 @@ static u64 hwprobe_misaligned(const struct cpumask *cpus)
> > return RISCV_HWPROBE_MISALIGNED_UNKNOWN;
> >
> > return perf;
> > +#else
> > + return RISCV_HWPROBE_MISALIGNED_FAST;
> > +#endif
>
> #ifdef..#else..#endif is more readable than #ifndef..#else..#endif.
>
> - Eric
Thanks for pointing these out, I will send a v3.
- Charlie
next prev parent reply other threads:[~2024-02-02 23:13 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-01 23:30 [PATCH v2 0/2] riscv: Use CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS to set misaligned access speed Charlie Jenkins
2024-02-01 23:30 ` Charlie Jenkins
2024-02-01 23:30 ` [PATCH v2 1/2] riscv: lib: Introduce has_fast_misaligned_access function Charlie Jenkins
2024-02-01 23:30 ` Charlie Jenkins
2024-02-02 22:49 ` Eric Biggers
2024-02-02 22:49 ` Eric Biggers
2024-02-02 23:11 ` Charlie Jenkins
2024-02-02 23:11 ` Charlie Jenkins
2024-02-01 23:30 ` [PATCH v2 2/2] riscv: Disable misaligned access probe when CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS Charlie Jenkins
2024-02-01 23:30 ` Charlie Jenkins
2024-02-02 4:31 ` Elliot Berman
2024-02-02 4:31 ` Elliot Berman
2024-02-02 4:55 ` Charlie Jenkins
2024-02-02 4:55 ` Charlie Jenkins
2024-02-02 23:01 ` Eric Biggers
2024-02-02 23:01 ` Eric Biggers
2024-02-02 23:13 ` Charlie Jenkins [this message]
2024-02-02 23:13 ` Charlie Jenkins
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