* [PATCH 1/6] drm/i915/adlp: Add MST FEC BS jitter WA (Wa_14013163432)
2024-01-29 17:55 [PATCH 0/6] drm/i915/dp: Add jitter WAs for MST/FEC/DSC links Imre Deak
@ 2024-01-29 17:55 ` Imre Deak
2024-01-30 13:48 ` Nautiyal, Ankit K
2024-01-29 17:55 ` [PATCH 2/6] drm/i915/adlp: Add MST short HBlank WA (Wa_14014143976) Imre Deak
` (5 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Imre Deak @ 2024-01-29 17:55 UTC (permalink / raw)
To: intel-gfx
Add a workaround to fix BS (blank start) to BS jitter issues on MST
links when FEC is enabled. Neither Bspec requires this nor Windows
clears the WA when disabling the output - presumedly because
CHICKEN_MISC_3 gets reset after disabling the pipe/transcoder - so
follow suit.
Bspec: 50050, 55424
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 24 +++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 5fa25a5a36b55..22c1759f912db 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1106,6 +1106,28 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
intel_ddi_set_dp_msa(pipe_config, conn_state);
}
+static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ u32 clear = 0;
+ u32 set = 0;
+
+ if (!IS_ALDERLAKE_P(i915))
+ return;
+
+ if (!IS_DISPLAY_STEP(i915, STEP_D0, STEP_FOREVER))
+ return;
+
+ /* Wa_14013163432:adlp */
+ if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
+ set |= DP_MST_FEC_BS_JITTER_WA(crtc_state->cpu_transcoder);
+
+ if (!clear && !set)
+ return;
+
+ intel_de_rmw(i915, CHICKEN_MISC_3, clear, set);
+}
+
static void intel_mst_enable_dp(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config,
@@ -1134,6 +1156,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
}
+ enable_bs_jitter_was(pipe_config);
+
intel_ddi_enable_transcoder_func(encoder, pipe_config);
clear_act_sent(encoder, pipe_config);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 75bc08081fce9..67b7d02ea37bf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4555,6 +4555,9 @@
#define GLK_CL1_PWR_DOWN REG_BIT(11)
#define GLK_CL0_PWR_DOWN REG_BIT(10)
+#define CHICKEN_MISC_3 _MMIO(0x42088)
+#define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
+
#define CHICKEN_MISC_4 _MMIO(0x4208c)
#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 1/6] drm/i915/adlp: Add MST FEC BS jitter WA (Wa_14013163432)
2024-01-29 17:55 ` [PATCH 1/6] drm/i915/adlp: Add MST FEC BS jitter WA (Wa_14013163432) Imre Deak
@ 2024-01-30 13:48 ` Nautiyal, Ankit K
2024-01-30 14:05 ` Imre Deak
0 siblings, 1 reply; 17+ messages in thread
From: Nautiyal, Ankit K @ 2024-01-30 13:48 UTC (permalink / raw)
To: Imre Deak, intel-gfx
On 1/29/2024 11:25 PM, Imre Deak wrote:
> Add a workaround to fix BS (blank start) to BS jitter issues on MST
> links when FEC is enabled. Neither Bspec requires this nor Windows
> clears the WA when disabling the output - presumedly because
> CHICKEN_MISC_3 gets reset after disabling the pipe/transcoder - so
> follow suit.
>
> Bspec: 50050, 55424
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 24 +++++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 5fa25a5a36b55..22c1759f912db 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -1106,6 +1106,28 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
> intel_ddi_set_dp_msa(pipe_config, conn_state);
> }
>
> +static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + u32 clear = 0;
> + u32 set = 0;
> +
> + if (!IS_ALDERLAKE_P(i915))
> + return;
> +
> + if (!IS_DISPLAY_STEP(i915, STEP_D0, STEP_FOREVER))
> + return;
> +
> + /* Wa_14013163432:adlp */
> + if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
Is this for DP MST + UHBR and DP MST + FEC?
From Bspec it seems this is meant only for MST+ FEC case, unless I am
missing something.
> + set |= DP_MST_FEC_BS_JITTER_WA(crtc_state->cpu_transcoder);
> +
> + if (!clear && !set)
> + return;
> +
> + intel_de_rmw(i915, CHICKEN_MISC_3, clear, set);
> +}
> +
> static void intel_mst_enable_dp(struct intel_atomic_state *state,
> struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config,
> @@ -1134,6 +1156,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
> TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
> }
>
> + enable_bs_jitter_was(pipe_config);
> +
> intel_ddi_enable_transcoder_func(encoder, pipe_config);
>
> clear_act_sent(encoder, pipe_config);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 75bc08081fce9..67b7d02ea37bf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4555,6 +4555,9 @@
> #define GLK_CL1_PWR_DOWN REG_BIT(11)
> #define GLK_CL0_PWR_DOWN REG_BIT(10)
>
> +#define CHICKEN_MISC_3 _MMIO(0x42088)
> +#define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
Should we mention /* adlp */ here?
Regards,
Ankit
> +
> #define CHICKEN_MISC_4 _MMIO(0x4208c)
> #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
> #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 1/6] drm/i915/adlp: Add MST FEC BS jitter WA (Wa_14013163432)
2024-01-30 13:48 ` Nautiyal, Ankit K
@ 2024-01-30 14:05 ` Imre Deak
2024-01-31 5:05 ` Nautiyal, Ankit K
0 siblings, 1 reply; 17+ messages in thread
From: Imre Deak @ 2024-01-30 14:05 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-gfx
On Tue, Jan 30, 2024 at 07:18:25PM +0530, Nautiyal, Ankit K wrote:
>
> On 1/29/2024 11:25 PM, Imre Deak wrote:
> > Add a workaround to fix BS (blank start) to BS jitter issues on MST
> > links when FEC is enabled. Neither Bspec requires this nor Windows
> > clears the WA when disabling the output - presumedly because
> > CHICKEN_MISC_3 gets reset after disabling the pipe/transcoder - so
> > follow suit.
> >
> > Bspec: 50050, 55424
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 24 +++++++++++++++++++++
> > drivers/gpu/drm/i915/i915_reg.h | 3 +++
> > 2 files changed, 27 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 5fa25a5a36b55..22c1759f912db 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -1106,6 +1106,28 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
> > intel_ddi_set_dp_msa(pipe_config, conn_state);
> > }
> > +static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state)
> > +{
> > + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> > + u32 clear = 0;
> > + u32 set = 0;
> > +
> > + if (!IS_ALDERLAKE_P(i915))
> > + return;
> > +
> > + if (!IS_DISPLAY_STEP(i915, STEP_D0, STEP_FOREVER))
> > + return;
> > +
> > + /* Wa_14013163432:adlp */
> > + if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
>
> Is this for DP MST + UHBR and DP MST + FEC?
>
> From Bspec it seems this is meant only for MST+ FEC case, unless I am
> missing something.
You mean not meant for UHBR? The register description is clearer than
the modeset page, requiring it for both non-UHBR and UHBR. Windows also
enables it for both.
> > + set |= DP_MST_FEC_BS_JITTER_WA(crtc_state->cpu_transcoder);
> > +
> > + if (!clear && !set)
> > + return;
> > +
> > + intel_de_rmw(i915, CHICKEN_MISC_3, clear, set);
> > +}
> > +
> > static void intel_mst_enable_dp(struct intel_atomic_state *state,
> > struct intel_encoder *encoder,
> > const struct intel_crtc_state *pipe_config,
> > @@ -1134,6 +1156,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
> > TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
> > }
> > + enable_bs_jitter_was(pipe_config);
> > +
> > intel_ddi_enable_transcoder_func(encoder, pipe_config);
> > clear_act_sent(encoder, pipe_config);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 75bc08081fce9..67b7d02ea37bf 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4555,6 +4555,9 @@
> > #define GLK_CL1_PWR_DOWN REG_BIT(11)
> > #define GLK_CL0_PWR_DOWN REG_BIT(10)
> > +#define CHICKEN_MISC_3 _MMIO(0x42088)
> > +#define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
>
>
> Should we mention /* adlp */ here?
In the register description the flag is valid for other platforms too,
even though it's only enabled for ADLP/RPLP.
> Regards,
>
> Ankit
>
> > +
> > #define CHICKEN_MISC_4 _MMIO(0x4208c)
> > #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
> > #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 1/6] drm/i915/adlp: Add MST FEC BS jitter WA (Wa_14013163432)
2024-01-30 14:05 ` Imre Deak
@ 2024-01-31 5:05 ` Nautiyal, Ankit K
0 siblings, 0 replies; 17+ messages in thread
From: Nautiyal, Ankit K @ 2024-01-31 5:05 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
On 1/30/2024 7:35 PM, Imre Deak wrote:
> On Tue, Jan 30, 2024 at 07:18:25PM +0530, Nautiyal, Ankit K wrote:
>> On 1/29/2024 11:25 PM, Imre Deak wrote:
>>> Add a workaround to fix BS (blank start) to BS jitter issues on MST
>>> links when FEC is enabled. Neither Bspec requires this nor Windows
>>> clears the WA when disabling the output - presumedly because
>>> CHICKEN_MISC_3 gets reset after disabling the pipe/transcoder - so
>>> follow suit.
>>>
>>> Bspec: 50050, 55424
>>>
>>> Signed-off-by: Imre Deak <imre.deak@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_dp_mst.c | 24 +++++++++++++++++++++
>>> drivers/gpu/drm/i915/i915_reg.h | 3 +++
>>> 2 files changed, 27 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>>> index 5fa25a5a36b55..22c1759f912db 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
>>> @@ -1106,6 +1106,28 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
>>> intel_ddi_set_dp_msa(pipe_config, conn_state);
>>> }
>>> +static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state)
>>> +{
>>> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
>>> + u32 clear = 0;
>>> + u32 set = 0;
>>> +
>>> + if (!IS_ALDERLAKE_P(i915))
>>> + return;
>>> +
>>> + if (!IS_DISPLAY_STEP(i915, STEP_D0, STEP_FOREVER))
>>> + return;
>>> +
>>> + /* Wa_14013163432:adlp */
>>> + if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
>> Is this for DP MST + UHBR and DP MST + FEC?
>>
>> From Bspec it seems this is meant only for MST+ FEC case, unless I am
>> missing something.
> You mean not meant for UHBR? The register description is clearer than
> the modeset page, requiring it for both non-UHBR and UHBR. Windows also
> enables it for both.
>
>>> + set |= DP_MST_FEC_BS_JITTER_WA(crtc_state->cpu_transcoder);
>>> +
>>> + if (!clear && !set)
>>> + return;
>>> +
>>> + intel_de_rmw(i915, CHICKEN_MISC_3, clear, set);
>>> +}
>>> +
>>> static void intel_mst_enable_dp(struct intel_atomic_state *state,
>>> struct intel_encoder *encoder,
>>> const struct intel_crtc_state *pipe_config,
>>> @@ -1134,6 +1156,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
>>> TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
>>> }
>>> + enable_bs_jitter_was(pipe_config);
>>> +
>>> intel_ddi_enable_transcoder_func(encoder, pipe_config);
>>> clear_act_sent(encoder, pipe_config);
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index 75bc08081fce9..67b7d02ea37bf 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -4555,6 +4555,9 @@
>>> #define GLK_CL1_PWR_DOWN REG_BIT(11)
>>> #define GLK_CL0_PWR_DOWN REG_BIT(10)
>>> +#define CHICKEN_MISC_3 _MMIO(0x42088)
>>> +#define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
>>
>> Should we mention /* adlp */ here?
> In the register description the flag is valid for other platforms too,
> even though it's only enabled for ADLP/RPLP.
Yes indeed.
Patch looks good to me.
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
>> Regards,
>>
>> Ankit
>>
>>> +
>>> #define CHICKEN_MISC_4 _MMIO(0x4208c)
>>> #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
>>> #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/6] drm/i915/adlp: Add MST short HBlank WA (Wa_14014143976)
2024-01-29 17:55 [PATCH 0/6] drm/i915/dp: Add jitter WAs for MST/FEC/DSC links Imre Deak
2024-01-29 17:55 ` [PATCH 1/6] drm/i915/adlp: Add MST FEC BS jitter WA (Wa_14013163432) Imre Deak
@ 2024-01-29 17:55 ` Imre Deak
2024-01-31 5:15 ` Nautiyal, Ankit K
2024-01-29 17:55 ` [PATCH 3/6] drm/i915/adlp: Add DP MST DPT/DPTP alignment " Imre Deak
` (4 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Imre Deak @ 2024-01-29 17:55 UTC (permalink / raw)
To: intel-gfx
Add a workaround to fix BS jitter issues on MST links if the HBLANK
period is less than 1 MTP. The WA applies only to UHBR rates while on
non-UHBR the specification requires disabling it explicitly - presumedly
because the register's reset value has the WA enabled.
Bspec: 50050, 55424
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 22c1759f912db..23f3f7fab9d0b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1122,6 +1122,14 @@ static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state)
if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
set |= DP_MST_FEC_BS_JITTER_WA(crtc_state->cpu_transcoder);
+ /* Wa_14014143976:adlp */
+ if (IS_DISPLAY_STEP(i915, STEP_E0, STEP_FOREVER)) {
+ if (intel_dp_is_uhbr(crtc_state))
+ set |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
+ else if (crtc_state->fec_enable)
+ clear |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
+ }
+
if (!clear && !set)
return;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 67b7d02ea37bf..091edc1071e0e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4556,6 +4556,7 @@
#define GLK_CL0_PWR_DOWN REG_BIT(10)
#define CHICKEN_MISC_3 _MMIO(0x42088)
+#define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A)
#define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
#define CHICKEN_MISC_4 _MMIO(0x4208c)
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 2/6] drm/i915/adlp: Add MST short HBlank WA (Wa_14014143976)
2024-01-29 17:55 ` [PATCH 2/6] drm/i915/adlp: Add MST short HBlank WA (Wa_14014143976) Imre Deak
@ 2024-01-31 5:15 ` Nautiyal, Ankit K
0 siblings, 0 replies; 17+ messages in thread
From: Nautiyal, Ankit K @ 2024-01-31 5:15 UTC (permalink / raw)
To: Imre Deak, intel-gfx
On 1/29/2024 11:25 PM, Imre Deak wrote:
> Add a workaround to fix BS jitter issues on MST links if the HBLANK
> period is less than 1 MTP. The WA applies only to UHBR rates while on
> non-UHBR the specification requires disabling it explicitly - presumedly
> because the register's reset value has the WA enabled.
>
> Bspec: 50050, 55424
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
LGTM.
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 22c1759f912db..23f3f7fab9d0b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -1122,6 +1122,14 @@ static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state)
> if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
> set |= DP_MST_FEC_BS_JITTER_WA(crtc_state->cpu_transcoder);
>
> + /* Wa_14014143976:adlp */
> + if (IS_DISPLAY_STEP(i915, STEP_E0, STEP_FOREVER)) {
> + if (intel_dp_is_uhbr(crtc_state))
> + set |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
> + else if (crtc_state->fec_enable)
> + clear |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
> + }
> +
> if (!clear && !set)
> return;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 67b7d02ea37bf..091edc1071e0e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4556,6 +4556,7 @@
> #define GLK_CL0_PWR_DOWN REG_BIT(10)
>
> #define CHICKEN_MISC_3 _MMIO(0x42088)
> +#define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A)
> #define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
>
> #define CHICKEN_MISC_4 _MMIO(0x4208c)
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/6] drm/i915/adlp: Add DP MST DPT/DPTP alignment WA (Wa_14014143976)
2024-01-29 17:55 [PATCH 0/6] drm/i915/dp: Add jitter WAs for MST/FEC/DSC links Imre Deak
2024-01-29 17:55 ` [PATCH 1/6] drm/i915/adlp: Add MST FEC BS jitter WA (Wa_14013163432) Imre Deak
2024-01-29 17:55 ` [PATCH 2/6] drm/i915/adlp: Add MST short HBlank WA (Wa_14014143976) Imre Deak
@ 2024-01-29 17:55 ` Imre Deak
2024-01-31 5:27 ` Nautiyal, Ankit K
2024-01-29 17:55 ` [PATCH 4/6] drm/i915/adlp+: Add DSC early pixel count scaling WA (Wa_1409098942) Imre Deak
` (3 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Imre Deak @ 2024-01-29 17:55 UTC (permalink / raw)
To: intel-gfx
Add a workaround to fix BS-BS jitter issues on MST links, aligning
DPT/DPTP MTPs.
Bspec: 50050, 55424
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 23f3f7fab9d0b..26c838ac9e411 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -1128,6 +1128,9 @@ static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state)
set |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
else if (crtc_state->fec_enable)
clear |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
+
+ if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
+ set |= DP_MST_DPT_DPTP_ALIGN_WA(crtc_state->cpu_transcoder);
}
if (!clear && !set)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 091edc1071e0e..eecbdecb8ed40 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4556,6 +4556,7 @@
#define GLK_CL0_PWR_DOWN REG_BIT(10)
#define CHICKEN_MISC_3 _MMIO(0x42088)
+#define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A)
#define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A)
#define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 3/6] drm/i915/adlp: Add DP MST DPT/DPTP alignment WA (Wa_14014143976)
2024-01-29 17:55 ` [PATCH 3/6] drm/i915/adlp: Add DP MST DPT/DPTP alignment " Imre Deak
@ 2024-01-31 5:27 ` Nautiyal, Ankit K
0 siblings, 0 replies; 17+ messages in thread
From: Nautiyal, Ankit K @ 2024-01-31 5:27 UTC (permalink / raw)
To: Imre Deak, intel-gfx
On 1/29/2024 11:25 PM, Imre Deak wrote:
> Add a workaround to fix BS-BS jitter issues on MST links, aligning
> DPT/DPTP MTPs.
>
> Bspec: 50050, 55424
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
LGTM.
As an aside, with these WAs do we also need to re-visit the transcoder
Data M and N values.
There is a note too related to WA_14013163432 in intel_dp_mst_compute_m_n.
In any case this is,
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 23f3f7fab9d0b..26c838ac9e411 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -1128,6 +1128,9 @@ static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state)
> set |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
> else if (crtc_state->fec_enable)
> clear |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
> +
> + if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
> + set |= DP_MST_DPT_DPTP_ALIGN_WA(crtc_state->cpu_transcoder);
> }
>
> if (!clear && !set)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 091edc1071e0e..eecbdecb8ed40 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4556,6 +4556,7 @@
> #define GLK_CL0_PWR_DOWN REG_BIT(10)
>
> #define CHICKEN_MISC_3 _MMIO(0x42088)
> +#define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A)
> #define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A)
> #define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 4/6] drm/i915/adlp+: Add DSC early pixel count scaling WA (Wa_1409098942)
2024-01-29 17:55 [PATCH 0/6] drm/i915/dp: Add jitter WAs for MST/FEC/DSC links Imre Deak
` (2 preceding siblings ...)
2024-01-29 17:55 ` [PATCH 3/6] drm/i915/adlp: Add DP MST DPT/DPTP alignment " Imre Deak
@ 2024-01-29 17:55 ` Imre Deak
2024-01-31 5:41 ` Nautiyal, Ankit K
2024-01-29 17:55 ` [PATCH 5/6] drm/i915/mtl+: Disable DP/DSC SF insertion at EOL WA Imre Deak
` (2 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Imre Deak @ 2024-01-29 17:55 UTC (permalink / raw)
To: intel-gfx
Add a workaround to fix timing issues on links with DSC enabled -
presumedly related to the audio functionality.
Bspec requires enabling this workaround if audio is enabled on ADLP,
however Windows enables it whenever DSC is enabled ADLP onwards; follow
Windows.
Bspec: 50490, 55424
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a92e959c8ac7b..0f4cd634d7dce 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -435,6 +435,14 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
return;
}
+ /* Wa_1409098942: adlp+ */
+ if (DISPLAY_VER(dev_priv) >= 13 &&
+ new_crtc_state->dsc.compression_enable) {
+ val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
+ val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
+ TRANSCONF_PIXEL_COUNT_SCALING_X4);
+ }
+
intel_de_write(dev_priv, TRANSCONF(cpu_transcoder),
val | TRANSCONF_ENABLE);
intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
@@ -481,6 +489,11 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
if (!IS_I830(dev_priv))
val &= ~TRANSCONF_ENABLE;
+ /* Wa_1409098942: adlp+ */
+ if (DISPLAY_VER(dev_priv) >= 13 &&
+ old_crtc_state->dsc.compression_enable)
+ val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
+
intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
if (DISPLAY_VER(dev_priv) >= 12)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eecbdecb8ed40..b43d1145fa22f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2588,6 +2588,9 @@
#define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1)
#define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2)
#define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3)
+#define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0)
+#define TRANSCONF_PIXEL_COUNT_SCALING_X4 1
+
#define _PIPEASTAT 0x70024
#define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 4/6] drm/i915/adlp+: Add DSC early pixel count scaling WA (Wa_1409098942)
2024-01-29 17:55 ` [PATCH 4/6] drm/i915/adlp+: Add DSC early pixel count scaling WA (Wa_1409098942) Imre Deak
@ 2024-01-31 5:41 ` Nautiyal, Ankit K
0 siblings, 0 replies; 17+ messages in thread
From: Nautiyal, Ankit K @ 2024-01-31 5:41 UTC (permalink / raw)
To: Imre Deak, intel-gfx
On 1/29/2024 11:25 PM, Imre Deak wrote:
> Add a workaround to fix timing issues on links with DSC enabled -
> presumedly related to the audio functionality.
>
> Bspec requires enabling this workaround if audio is enabled on ADLP,
> however Windows enables it whenever DSC is enabled ADLP onwards; follow
> Windows.
>
> Bspec: 50490, 55424
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a92e959c8ac7b..0f4cd634d7dce 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -435,6 +435,14 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
> return;
> }
>
> + /* Wa_1409098942: adlp+ */
> + if (DISPLAY_VER(dev_priv) >= 13 &&
> + new_crtc_state->dsc.compression_enable) {
> + val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
> + val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
> + TRANSCONF_PIXEL_COUNT_SCALING_X4);
> + }
> +
> intel_de_write(dev_priv, TRANSCONF(cpu_transcoder),
> val | TRANSCONF_ENABLE);
> intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
> @@ -481,6 +489,11 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
> if (!IS_I830(dev_priv))
> val &= ~TRANSCONF_ENABLE;
>
> + /* Wa_1409098942: adlp+ */
Nit pick: extra space before platform, (not sure if it matters, tbh).
Patch looks good to me.
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> + if (DISPLAY_VER(dev_priv) >= 13 &&
> + old_crtc_state->dsc.compression_enable)
> + val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
> +
> intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
>
> if (DISPLAY_VER(dev_priv) >= 12)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eecbdecb8ed40..b43d1145fa22f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2588,6 +2588,9 @@
> #define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1)
> #define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2)
> #define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3)
> +#define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0)
> +#define TRANSCONF_PIXEL_COUNT_SCALING_X4 1
> +
> #define _PIPEASTAT 0x70024
> #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
> #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 5/6] drm/i915/mtl+: Disable DP/DSC SF insertion at EOL WA
2024-01-29 17:55 [PATCH 0/6] drm/i915/dp: Add jitter WAs for MST/FEC/DSC links Imre Deak
` (3 preceding siblings ...)
2024-01-29 17:55 ` [PATCH 4/6] drm/i915/adlp+: Add DSC early pixel count scaling WA (Wa_1409098942) Imre Deak
@ 2024-01-29 17:55 ` Imre Deak
2024-01-31 5:58 ` Nautiyal, Ankit K
2024-01-29 17:55 ` [PATCH 6/6] drm/i915/mtl: Add DP FEC BS jitter WA Imre Deak
2024-01-29 18:42 ` ✓ Fi.CI.BAT: success for drm/i915/dp: Add jitter WAs for MST/FEC/DSC links Patchwork
6 siblings, 1 reply; 17+ messages in thread
From: Imre Deak @ 2024-01-29 17:55 UTC (permalink / raw)
To: intel-gfx
Disable the workaround inserting an SF symbol between the last DSC EOC
symbol and the subsequent BS symbol. The WA is enabled by default -
based on the register's reset value - and Bspec requires disabling it
explicitly. Bspec doesn't provide an actual WA ID for this.
Bspec: 50054, 65448, 68849
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0f4cd634d7dce..e0b75aa18ae33 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -428,6 +428,15 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
0, PIPE_ARB_USE_PROG_SLOTS);
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA;
+ u32 set = 0;
+
+ intel_de_rmw(dev_priv,
+ hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
+ clear, set);
+ }
+
val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
if (val & TRANSCONF_ENABLE) {
/* we keep both pipes enabled on 830 */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b43d1145fa22f..9873daa16c6a1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4620,6 +4620,7 @@
#define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
#define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
+#define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)
#define DISP_ARB_CTL _MMIO(0x45000)
#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 5/6] drm/i915/mtl+: Disable DP/DSC SF insertion at EOL WA
2024-01-29 17:55 ` [PATCH 5/6] drm/i915/mtl+: Disable DP/DSC SF insertion at EOL WA Imre Deak
@ 2024-01-31 5:58 ` Nautiyal, Ankit K
0 siblings, 0 replies; 17+ messages in thread
From: Nautiyal, Ankit K @ 2024-01-31 5:58 UTC (permalink / raw)
To: Imre Deak, intel-gfx
LGTM.
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
On 1/29/2024 11:25 PM, Imre Deak wrote:
> Disable the workaround inserting an SF symbol between the last DSC EOC
> symbol and the subsequent BS symbol. The WA is enabled by default -
> based on the register's reset value - and Bspec requires disabling it
> explicitly. Bspec doesn't provide an actual WA ID for this.
>
> Bspec: 50054, 65448, 68849
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0f4cd634d7dce..e0b75aa18ae33 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -428,6 +428,15 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
> intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
> 0, PIPE_ARB_USE_PROG_SLOTS);
>
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA;
> + u32 set = 0;
> +
> + intel_de_rmw(dev_priv,
> + hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
> + clear, set);
> + }
> +
> val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
> if (val & TRANSCONF_ENABLE) {
> /* we keep both pipes enabled on 830 */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b43d1145fa22f..9873daa16c6a1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4620,6 +4620,7 @@
> #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
> #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
> #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
> +#define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)
>
> #define DISP_ARB_CTL _MMIO(0x45000)
> #define DISP_FBC_MEMORY_WAKE REG_BIT(31)
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 6/6] drm/i915/mtl: Add DP FEC BS jitter WA
2024-01-29 17:55 [PATCH 0/6] drm/i915/dp: Add jitter WAs for MST/FEC/DSC links Imre Deak
` (4 preceding siblings ...)
2024-01-29 17:55 ` [PATCH 5/6] drm/i915/mtl+: Disable DP/DSC SF insertion at EOL WA Imre Deak
@ 2024-01-29 17:55 ` Imre Deak
2024-01-31 6:04 ` Nautiyal, Ankit K
2024-01-29 18:42 ` ✓ Fi.CI.BAT: success for drm/i915/dp: Add jitter WAs for MST/FEC/DSC links Patchwork
6 siblings, 1 reply; 17+ messages in thread
From: Imre Deak @ 2024-01-29 17:55 UTC (permalink / raw)
To: intel-gfx
Add a workaround to fix BS (blank start) to BS jitter fixes on non-UHBR
MST/FEC and UHBR links. Bspec doesn't provide an actual WA ID for this.
Bspec: 65448, 50054
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e0b75aa18ae33..72a852cccd3f3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -432,6 +432,9 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA;
u32 set = 0;
+ if (DISPLAY_VER(dev_priv) == 14)
+ set |= DP_FEC_BS_JITTER_WA;
+
intel_de_rmw(dev_priv,
hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
clear, set);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9873daa16c6a1..d86e904ffe893 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4619,6 +4619,7 @@
#define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
#define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
#define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
+#define DP_FEC_BS_JITTER_WA REG_BIT(15)
#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
#define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 6/6] drm/i915/mtl: Add DP FEC BS jitter WA
2024-01-29 17:55 ` [PATCH 6/6] drm/i915/mtl: Add DP FEC BS jitter WA Imre Deak
@ 2024-01-31 6:04 ` Nautiyal, Ankit K
0 siblings, 0 replies; 17+ messages in thread
From: Nautiyal, Ankit K @ 2024-01-31 6:04 UTC (permalink / raw)
To: Imre Deak, intel-gfx
On 1/29/2024 11:25 PM, Imre Deak wrote:
> Add a workaround to fix BS (blank start) to BS jitter fixes on non-UHBR
> MST/FEC and UHBR links. Bspec doesn't provide an actual WA ID for this.
>
> Bspec: 65448, 50054
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 3 +++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index e0b75aa18ae33..72a852cccd3f3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -432,6 +432,9 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
> u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA;
> u32 set = 0;
>
> + if (DISPLAY_VER(dev_priv) == 14)
> + set |= DP_FEC_BS_JITTER_WA;
> +
> intel_de_rmw(dev_priv,
> hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
> clear, set);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9873daa16c6a1..d86e904ffe893 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4619,6 +4619,7 @@
> #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
> #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
> #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
> +#define DP_FEC_BS_JITTER_WA REG_BIT(15)
Was wondering if this is for MTL+, but it seems this is required only
for MTL.
Patch LGTM.
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
> #define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/dp: Add jitter WAs for MST/FEC/DSC links
2024-01-29 17:55 [PATCH 0/6] drm/i915/dp: Add jitter WAs for MST/FEC/DSC links Imre Deak
` (5 preceding siblings ...)
2024-01-29 17:55 ` [PATCH 6/6] drm/i915/mtl: Add DP FEC BS jitter WA Imre Deak
@ 2024-01-29 18:42 ` Patchwork
2024-04-10 16:30 ` Imre Deak
6 siblings, 1 reply; 17+ messages in thread
From: Patchwork @ 2024-01-29 18:42 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
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== Series Details ==
Series: drm/i915/dp: Add jitter WAs for MST/FEC/DSC links
URL : https://patchwork.freedesktop.org/series/129277/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14192 -> Patchwork_129277v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129277v1/index.html
Participating hosts (37 -> 35)
------------------------------
Missing (2): bat-mtlp-8 fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_129277v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_hangman@error-state-basic:
- bat-mtlp-6: [PASS][1] -> [ABORT][2] ([i915#9414])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14192/bat-mtlp-6/igt@i915_hangman@error-state-basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129277v1/bat-mtlp-6/igt@i915_hangman@error-state-basic.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [ABORT][3] ([i915#7911]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14192/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129277v1/fi-bsw-nick/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@hangcheck:
- {bat-adls-6}: [DMESG-WARN][5] ([i915#5591]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14192/bat-adls-6/igt@i915_selftest@live@hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129277v1/bat-adls-6/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#9414]: https://gitlab.freedesktop.org/drm/intel/issues/9414
Build changes
-------------
* Linux: CI_DRM_14192 -> Patchwork_129277v1
CI-20190529: 20190529
CI_DRM_14192: f4c0dac89bd3cd02a1afe5e7a91ed4bf8de4afc6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7698: af750f5e7eaad98d40d8c924eb5f05e99d3c668b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_129277v1: f4c0dac89bd3cd02a1afe5e7a91ed4bf8de4afc6 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
684e00785693 drm/i915/mtl: Add DP FEC BS jitter WA
4710e5a9e439 drm/i915/mtl+: Disable DP/DSC SF insertion at EOL WA
f5853ef36adf drm/i915/adlp+: Add DSC early pixel count scaling WA (Wa_1409098942)
58b3ea4c8782 drm/i915/adlp: Add DP MST DPT/DPTP alignment WA (Wa_14014143976)
a8501371285d drm/i915/adlp: Add MST short HBlank WA (Wa_14014143976)
b689adcd3028 drm/i915/adlp: Add MST FEC BS jitter WA (Wa_14013163432)
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129277v1/index.html
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^ permalink raw reply [flat|nested] 17+ messages in thread