From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: intel-gfx@lists.freedesktop.org, chaitanya.kumar.borah@intel.com,
uma.shankar@intel.com, ankit.k.nautiyal@intel.com,
dnyaneshwar.bhadane@intel.com
Subject: Re: [PATCH 1/2] drm/i915: Add SCLKGATE_DIS register definition
Date: Tue, 16 Apr 2024 15:54:44 +0300 [thread overview]
Message-ID: <Zh51FEfyQbl0mIbY@intel.com> (raw)
In-Reply-To: <20240416072733.624048-3-suraj.kandpal@intel.com>
On Tue, Apr 16, 2024 at 12:57:33PM +0530, Suraj Kandpal wrote:
> Add SCLKGATE_DIS register and it's register definition which
> will be used the next patch.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3f34efcd7d6c..beec91a2f493 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6250,6 +6250,10 @@ enum skl_power_gate {
> #define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
> #define SFUSE_STRAP_DDID_DETECTED (1 << 0)
>
> +/* SCLKGATE_DIS */
> +#define SCLKGATE_DIS _MMIO(0xc2014)
That address is SFUSE_STRAP
> +#define DPLS_GATING_DISABLE REG_BIT(29)
> +
> #define WM_MISC _MMIO(0x45260)
> #define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
>
> --
> 2.43.2
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2024-04-16 12:54 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-16 7:27 [PATCH 0/2] Disable DPLS Gating around PPS Suraj Kandpal
2024-04-16 7:27 ` [PATCH 1/2] drm/i915: Add SCLKGATE_DIS register definition Suraj Kandpal
2024-04-16 7:38 ` Jani Nikula
2024-04-16 7:40 ` Kandpal, Suraj
2024-04-16 12:54 ` Ville Syrjälä [this message]
2024-04-17 5:00 ` Kandpal, Suraj
2024-04-16 7:27 ` [PATCH 2/2] drm/i915/pps: Disable DPLS_GATING around pps sequence Suraj Kandpal
2024-04-16 7:41 ` Jani Nikula
2024-04-16 7:57 ` Bhadane, Dnyaneshwar
2024-04-16 8:15 ` ✗ Fi.CI.SPARSE: warning for Disable DPLS Gating around PPS Patchwork
2024-04-16 8:22 ` ✗ Fi.CI.BAT: failure " Patchwork
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