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From: Fabio Aiuto <fabio.aiuto@engicam.com>
To: Shawn Guo <shawnguo2@yeah.net>
Cc: Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Rob Herring <robh@kernel.org>, Conor Dooley <conor+dt@kernel.org>,
	devicetree@vger.kernel.org, imx@lists.linux.dev,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Matteo Lisi <matteo.lisi@engicam.com>,
	Mirko Ardinghi <mirko.ardinghi@engicam.com>
Subject: Re: [PATCH v3 3/3] arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
Date: Thu, 25 Apr 2024 10:08:14 +0200	[thread overview]
Message-ID: <ZioPbmPmIuKME7zl@engicam> (raw)
In-Reply-To: <ZioJ032d0ZgwKbli@dragon>

Dear Shawn,

Il Thu, Apr 25, 2024 at 03:44:19PM +0800, Shawn Guo ha scritto:
> On Fri, Apr 19, 2024 at 04:49:53PM +0200, Fabio Aiuto wrote:

<snip>

> > +	usdhc3_pwrseq: usdhc3-pwrseq {
> 
> Can we drop it, as it's unused?
> 
> > +		compatible = "mmc-pwrseq-simple";
> 
> It controls nothing, neither clock nor GPIO?

please see v4.

Thank you for your comments, will fix all issues in a v5
patchset.

kr, fabio

> 
> > +	};
> > +
> > +	wl_reg_on: regulator-wlregon {
> > +		compatible = "regulator-gpio";
> > +		regulator-name = "WL_REG_ON";
> > +		regulator-min-microvolt = <100000>;
> > +		regulator-max-microvolt = <3300000>;
> > +		states = <3300000 0x1>, <100000 0x0>;
> > +		gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
> > +		enable-active-high;
> > +		vin-supply = <&bt_reg_on>;
> > +	};
> > +};
> > +
> > +&cm33 {
> > +	mbox-names = "tx", "rx", "rxdb";
> > +	mboxes = <&mu1 0 1>,
> > +		 <&mu1 1 1>,
> > +		 <&mu1 3 1>;
> > +	memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
> > +			<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
> > +	status = "okay";
> > +};
> > +
> > +&flexcan1 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_flexcan1>;
> > +	fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
> > +	status = "okay";
> > +};
> > +
> > +&flexcan2 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_flexcan2>;
> > +	fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
> > +	status = "okay";
> > +};
> > +
> > +&lpi2c1 {
> > +	#address-cells = <1>;
> > +	#size-cells = <0>;
> > +	clock-frequency = <400000>;
> > +	pinctrl-names = "default", "sleep";
> > +	pinctrl-0 = <&pinctrl_lpi2c1>;
> > +	pinctrl-1 = <&pinctrl_lpi2c1>;
> > +	status = "okay";
> > +
> > +	pcf8523: rtc@68 {
> > +		compatible = "nxp,pcf8523";
> > +		reg = <0x68>;
> > +	};
> > +
> > +	sgtl5000: codec@a {
> 
> audio-codec for the node name.  And we should sort slave nodes in unit-address.
> 
> > +		compatible = "fsl,sgtl5000";
> > +		status = "okay";
> 
> 'compatible' first, 'reg' second, and 'status' last. 
> 
> > +		#sound-dai-cells = <0>;
> > +		reg = <0x0a>;
> > +		clocks = <&clk IMX93_CLK_SAI3_GATE>;
> > +		VDDA-supply = <&reg_3v3_avdd_sgtl>;
> > +		VDDIO-supply = <&reg_3v3_sgtl>;
> > +		VDDD-supply = <&reg_1v8_sgtl>;
> > +	};
> > +};
> > +
> > +&lpuart1 { /* console */
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_uart1>;
> > +	status = "okay";
> > +};
> > +
> > +&lpuart5 { /* RS485 */
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_uart5>;
> > +	status = "okay";
> > +};
> > +
> > +&lpuart8 { /* RS232 */
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_uart8>;
> > +	status = "okay";
> > +};
> > +
> > +&micfil {
> > +	#sound-dai-cells = <0>;
> > +	assigned-clocks = <&clk IMX93_CLK_PDM>;
> > +	assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> > +	assigned-clock-rates = <196608000>;
> > +	status = "okay";
> > +};
> > +
> > +&mu1 {
> > +	status = "okay";
> > +};
> > +
> > +&mu2 {
> > +	status = "okay";
> > +};
> > +
> > +&sai1 {
> > +	#sound-dai-cells = <0>;
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_sai1>;
> > +	assigned-clocks = <&clk IMX93_CLK_SAI1>;
> > +	assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> > +	assigned-clock-rates = <12288000>;
> > +	status = "okay";
> > +};
> > +
> > +&sai3 {
> > +	pinctrl-names = "default";
> > +	#sound-dai-cells = <0>;
> > +	pinctrl-0 = <&pinctrl_sai3>;
> 
> pinctrl-0 right after pinctrl-names.
> 
> > +	assigned-clocks = <&clk IMX93_CLK_SAI3>;
> > +	assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> > +	assigned-clock-rates = <24576000>;
> > +	fsl,sai-mclk-direction-output;
> > +	status = "okay";
> > +};
> > +
> > +&usdhc3 { /* WiFi */
> > +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > +	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
> > +	pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
> > +	pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
> > +	vmmc-supply = <&wl_reg_on>;
> > +	bus-width = <4>;
> > +	no-1-8-v;
> > +	non-removable;
> > +	max-frequency = <25000000>;
> > +	status = "okay";
> > +
> > +	#address-cells = <1>;
> > +	#size-cells = <0>;
> 
> Drop newline and move them before pinctrl-names.
> 
> > +
> > +	brcmf: bcrmf@1 {
> > +		reg = <1>;
> > +		compatible = "brcm,bcm4329-fmac";
> 
> Flip the order.
> 
> > +	};
> > +};
> > +
> > +&wdog3 {
> > +	status = "okay";
> > +};
> > +
> > +&iomuxc {
> > +
> 
> Drop newline.
> 
> > +	pinctrl_flexcan1: flexcan1grp {
> > +		fsl,pins = <
> > +			MX93_PAD_PDM_CLK__CAN1_TX		0x139e
> > +			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX	0x139e
> > +		>;
> > +	};
> > +
> > +	pinctrl_flexcan2: flexcan2grp {
> > +		fsl,pins = <
> > +			MX93_PAD_GPIO_IO25__CAN2_TX	0x139e
> > +			MX93_PAD_GPIO_IO27__CAN2_RX	0x139e
> 
> Try to vertically align hex values.
> 
> > +		>;
> > +	};
> > +
> > +	pinctrl_laird: lairdgrp {
> > +		fsl,pins = <
> > +			MX93_PAD_GPIO_IO22__GPIO2_IO22		0x31e // WL_REG_ON
> > +			MX93_PAD_GPIO_IO19__GPIO2_IO19		0x31e // BT_REG_ON
> 
> /* ... */ for comments.
> 
> Shawn
> 
> > +		>;
> > +	};
> > +
> > +	pinctrl_lpi2c1: lpi2c1grp {
> > +		fsl,pins = <
> > +			MX93_PAD_I2C1_SCL__LPI2C1_SCL		0x40000b9e
> > +			MX93_PAD_I2C1_SDA__LPI2C1_SDA		0x40000b9e
> > +		>;
> > +	};
> > +
> > +	pinctrl_sai1: sai1grp {
> > +		fsl,pins = <
> > +			MX93_PAD_SAI1_TXC__SAI1_TX_BCLK		0x31e
> > +			MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC	0x31e
> > +			MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00	0x31e
> > +			MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00	0x31e
> > +		>;
> > +	};
> > +
> > +	pinctrl_sai3: sai3grp {
> > +		fsl,pins = <
> > +			MX93_PAD_GPIO_IO26__SAI3_TX_SYNC	0x31e
> > +			MX93_PAD_GPIO_IO16__SAI3_TX_BCLK	0x31e
> > +			MX93_PAD_GPIO_IO17__SAI3_MCLK		0x31e
> > +			MX93_PAD_GPIO_IO21__SAI3_TX_DATA00	0x31e
> > +			MX93_PAD_GPIO_IO20__SAI3_RX_DATA00	0x31e
> > +		>;
> > +	};
> > +
> > +	pinctrl_uart1: uart1grp {
> > +		fsl,pins = <
> > +			MX93_PAD_UART1_RXD__LPUART1_RX		0x31e
> > +			MX93_PAD_UART1_TXD__LPUART1_TX		0x31e
> > +		>;
> > +	};
> > +
> > +	pinctrl_uart5: uart5grp {
> > +		fsl,pins = <
> > +			MX93_PAD_GPIO_IO01__LPUART5_RX		0x31e
> > +			MX93_PAD_GPIO_IO00__LPUART5_TX		0x31e
> > +			MX93_PAD_GPIO_IO02__LPUART5_CTS_B	0x31e
> > +			MX93_PAD_GPIO_IO03__LPUART5_RTS_B	0x31e
> > +		>;
> > +	};
> > +
> > +	pinctrl_uart8: uart8grp {
> > +		fsl,pins = <
> > +			MX93_PAD_GPIO_IO13__LPUART8_RX		0x31e
> > +			MX93_PAD_GPIO_IO12__LPUART8_TX		0x31e
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc3: usdhc3grp {
> > +		fsl,pins = <
> > +			MX93_PAD_SD3_CLK__USDHC3_CLK		0x17fe
> > +			MX93_PAD_SD3_CMD__USDHC3_CMD		0x13fe
> > +			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x13fe
> > +			MX93_PAD_SD3_DATA1__USDHC3_DATA1        0x13fe
> > +			MX93_PAD_SD3_DATA2__USDHC3_DATA2        0x13fe
> > +			MX93_PAD_SD3_DATA3__USDHC3_DATA3        0x13fe
> > +		>;
> > +	};
> > +};
> > -- 
> > 2.34.1
> > 
> 

WARNING: multiple messages have this Message-ID (diff)
From: Fabio Aiuto <fabio.aiuto@engicam.com>
To: Shawn Guo <shawnguo2@yeah.net>
Cc: Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Rob Herring <robh@kernel.org>, Conor Dooley <conor+dt@kernel.org>,
	devicetree@vger.kernel.org, imx@lists.linux.dev,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Matteo Lisi <matteo.lisi@engicam.com>,
	Mirko Ardinghi <mirko.ardinghi@engicam.com>
Subject: Re: [PATCH v3 3/3] arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
Date: Thu, 25 Apr 2024 10:08:14 +0200	[thread overview]
Message-ID: <ZioPbmPmIuKME7zl@engicam> (raw)
In-Reply-To: <ZioJ032d0ZgwKbli@dragon>

Dear Shawn,

Il Thu, Apr 25, 2024 at 03:44:19PM +0800, Shawn Guo ha scritto:
> On Fri, Apr 19, 2024 at 04:49:53PM +0200, Fabio Aiuto wrote:

<snip>

> > +	usdhc3_pwrseq: usdhc3-pwrseq {
> 
> Can we drop it, as it's unused?
> 
> > +		compatible = "mmc-pwrseq-simple";
> 
> It controls nothing, neither clock nor GPIO?

please see v4.

Thank you for your comments, will fix all issues in a v5
patchset.

kr, fabio

> 
> > +	};
> > +
> > +	wl_reg_on: regulator-wlregon {
> > +		compatible = "regulator-gpio";
> > +		regulator-name = "WL_REG_ON";
> > +		regulator-min-microvolt = <100000>;
> > +		regulator-max-microvolt = <3300000>;
> > +		states = <3300000 0x1>, <100000 0x0>;
> > +		gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
> > +		enable-active-high;
> > +		vin-supply = <&bt_reg_on>;
> > +	};
> > +};
> > +
> > +&cm33 {
> > +	mbox-names = "tx", "rx", "rxdb";
> > +	mboxes = <&mu1 0 1>,
> > +		 <&mu1 1 1>,
> > +		 <&mu1 3 1>;
> > +	memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
> > +			<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
> > +	status = "okay";
> > +};
> > +
> > +&flexcan1 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_flexcan1>;
> > +	fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
> > +	status = "okay";
> > +};
> > +
> > +&flexcan2 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_flexcan2>;
> > +	fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
> > +	status = "okay";
> > +};
> > +
> > +&lpi2c1 {
> > +	#address-cells = <1>;
> > +	#size-cells = <0>;
> > +	clock-frequency = <400000>;
> > +	pinctrl-names = "default", "sleep";
> > +	pinctrl-0 = <&pinctrl_lpi2c1>;
> > +	pinctrl-1 = <&pinctrl_lpi2c1>;
> > +	status = "okay";
> > +
> > +	pcf8523: rtc@68 {
> > +		compatible = "nxp,pcf8523";
> > +		reg = <0x68>;
> > +	};
> > +
> > +	sgtl5000: codec@a {
> 
> audio-codec for the node name.  And we should sort slave nodes in unit-address.
> 
> > +		compatible = "fsl,sgtl5000";
> > +		status = "okay";
> 
> 'compatible' first, 'reg' second, and 'status' last. 
> 
> > +		#sound-dai-cells = <0>;
> > +		reg = <0x0a>;
> > +		clocks = <&clk IMX93_CLK_SAI3_GATE>;
> > +		VDDA-supply = <&reg_3v3_avdd_sgtl>;
> > +		VDDIO-supply = <&reg_3v3_sgtl>;
> > +		VDDD-supply = <&reg_1v8_sgtl>;
> > +	};
> > +};
> > +
> > +&lpuart1 { /* console */
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_uart1>;
> > +	status = "okay";
> > +};
> > +
> > +&lpuart5 { /* RS485 */
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_uart5>;
> > +	status = "okay";
> > +};
> > +
> > +&lpuart8 { /* RS232 */
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_uart8>;
> > +	status = "okay";
> > +};
> > +
> > +&micfil {
> > +	#sound-dai-cells = <0>;
> > +	assigned-clocks = <&clk IMX93_CLK_PDM>;
> > +	assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> > +	assigned-clock-rates = <196608000>;
> > +	status = "okay";
> > +};
> > +
> > +&mu1 {
> > +	status = "okay";
> > +};
> > +
> > +&mu2 {
> > +	status = "okay";
> > +};
> > +
> > +&sai1 {
> > +	#sound-dai-cells = <0>;
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_sai1>;
> > +	assigned-clocks = <&clk IMX93_CLK_SAI1>;
> > +	assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> > +	assigned-clock-rates = <12288000>;
> > +	status = "okay";
> > +};
> > +
> > +&sai3 {
> > +	pinctrl-names = "default";
> > +	#sound-dai-cells = <0>;
> > +	pinctrl-0 = <&pinctrl_sai3>;
> 
> pinctrl-0 right after pinctrl-names.
> 
> > +	assigned-clocks = <&clk IMX93_CLK_SAI3>;
> > +	assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> > +	assigned-clock-rates = <24576000>;
> > +	fsl,sai-mclk-direction-output;
> > +	status = "okay";
> > +};
> > +
> > +&usdhc3 { /* WiFi */
> > +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > +	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
> > +	pinctrl-1 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
> > +	pinctrl-2 = <&pinctrl_usdhc3>, <&pinctrl_laird>;
> > +	vmmc-supply = <&wl_reg_on>;
> > +	bus-width = <4>;
> > +	no-1-8-v;
> > +	non-removable;
> > +	max-frequency = <25000000>;
> > +	status = "okay";
> > +
> > +	#address-cells = <1>;
> > +	#size-cells = <0>;
> 
> Drop newline and move them before pinctrl-names.
> 
> > +
> > +	brcmf: bcrmf@1 {
> > +		reg = <1>;
> > +		compatible = "brcm,bcm4329-fmac";
> 
> Flip the order.
> 
> > +	};
> > +};
> > +
> > +&wdog3 {
> > +	status = "okay";
> > +};
> > +
> > +&iomuxc {
> > +
> 
> Drop newline.
> 
> > +	pinctrl_flexcan1: flexcan1grp {
> > +		fsl,pins = <
> > +			MX93_PAD_PDM_CLK__CAN1_TX		0x139e
> > +			MX93_PAD_PDM_BIT_STREAM0__CAN1_RX	0x139e
> > +		>;
> > +	};
> > +
> > +	pinctrl_flexcan2: flexcan2grp {
> > +		fsl,pins = <
> > +			MX93_PAD_GPIO_IO25__CAN2_TX	0x139e
> > +			MX93_PAD_GPIO_IO27__CAN2_RX	0x139e
> 
> Try to vertically align hex values.
> 
> > +		>;
> > +	};
> > +
> > +	pinctrl_laird: lairdgrp {
> > +		fsl,pins = <
> > +			MX93_PAD_GPIO_IO22__GPIO2_IO22		0x31e // WL_REG_ON
> > +			MX93_PAD_GPIO_IO19__GPIO2_IO19		0x31e // BT_REG_ON
> 
> /* ... */ for comments.
> 
> Shawn
> 
> > +		>;
> > +	};
> > +
> > +	pinctrl_lpi2c1: lpi2c1grp {
> > +		fsl,pins = <
> > +			MX93_PAD_I2C1_SCL__LPI2C1_SCL		0x40000b9e
> > +			MX93_PAD_I2C1_SDA__LPI2C1_SDA		0x40000b9e
> > +		>;
> > +	};
> > +
> > +	pinctrl_sai1: sai1grp {
> > +		fsl,pins = <
> > +			MX93_PAD_SAI1_TXC__SAI1_TX_BCLK		0x31e
> > +			MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC	0x31e
> > +			MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00	0x31e
> > +			MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00	0x31e
> > +		>;
> > +	};
> > +
> > +	pinctrl_sai3: sai3grp {
> > +		fsl,pins = <
> > +			MX93_PAD_GPIO_IO26__SAI3_TX_SYNC	0x31e
> > +			MX93_PAD_GPIO_IO16__SAI3_TX_BCLK	0x31e
> > +			MX93_PAD_GPIO_IO17__SAI3_MCLK		0x31e
> > +			MX93_PAD_GPIO_IO21__SAI3_TX_DATA00	0x31e
> > +			MX93_PAD_GPIO_IO20__SAI3_RX_DATA00	0x31e
> > +		>;
> > +	};
> > +
> > +	pinctrl_uart1: uart1grp {
> > +		fsl,pins = <
> > +			MX93_PAD_UART1_RXD__LPUART1_RX		0x31e
> > +			MX93_PAD_UART1_TXD__LPUART1_TX		0x31e
> > +		>;
> > +	};
> > +
> > +	pinctrl_uart5: uart5grp {
> > +		fsl,pins = <
> > +			MX93_PAD_GPIO_IO01__LPUART5_RX		0x31e
> > +			MX93_PAD_GPIO_IO00__LPUART5_TX		0x31e
> > +			MX93_PAD_GPIO_IO02__LPUART5_CTS_B	0x31e
> > +			MX93_PAD_GPIO_IO03__LPUART5_RTS_B	0x31e
> > +		>;
> > +	};
> > +
> > +	pinctrl_uart8: uart8grp {
> > +		fsl,pins = <
> > +			MX93_PAD_GPIO_IO13__LPUART8_RX		0x31e
> > +			MX93_PAD_GPIO_IO12__LPUART8_TX		0x31e
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc3: usdhc3grp {
> > +		fsl,pins = <
> > +			MX93_PAD_SD3_CLK__USDHC3_CLK		0x17fe
> > +			MX93_PAD_SD3_CMD__USDHC3_CMD		0x13fe
> > +			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x13fe
> > +			MX93_PAD_SD3_DATA1__USDHC3_DATA1        0x13fe
> > +			MX93_PAD_SD3_DATA2__USDHC3_DATA2        0x13fe
> > +			MX93_PAD_SD3_DATA3__USDHC3_DATA3        0x13fe
> > +		>;
> > +	};
> > +};
> > -- 
> > 2.34.1
> > 
> 

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  reply	other threads:[~2024-04-25  8:11 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-19 14:49 [PATCH v3 0/3] arm64: dts: imx93: add i.Core MX93 EDIMM 2.0 board Fabio Aiuto
2024-04-19 14:49 ` Fabio Aiuto
2024-04-19 14:49 ` [PATCH v3 1/3] dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit Fabio Aiuto
2024-04-19 14:49   ` Fabio Aiuto
2024-04-19 14:49 ` [PATCH v3 2/3] arm64: dts: imx93: add Engicam i.Core MX93 SoM Fabio Aiuto
2024-04-19 14:49   ` Fabio Aiuto
2024-04-25  7:25   ` Shawn Guo
2024-04-25  7:25     ` Shawn Guo
2024-04-25  7:30     ` Fabio Aiuto
2024-04-25  7:30       ` Fabio Aiuto
2024-04-19 14:49 ` [PATCH v3 3/3] arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit Fabio Aiuto
2024-04-19 14:49   ` Fabio Aiuto
2024-04-25  7:44   ` Shawn Guo
2024-04-25  7:44     ` Shawn Guo
2024-04-25  8:08     ` Fabio Aiuto [this message]
2024-04-25  8:08       ` Fabio Aiuto

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