Re: [PATCH v2 00/14] PCI: dw-rockchip: Add endpoint mode support

From: Niklas Cassel <cassel@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: "Jingoo Han" <jingoohan1@gmail.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Arnd Bergmann" <arnd@arndb.de>,
	"Damien Le Moal" <dlemoal@kernel.org>,
	"Jon Lin" <jon.lin@rock-chips.com>,
	"Shawn Lin" <shawn.lin@rock-chips.com>,
	"Simon Xue" <xxm@rock-chips.com>,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v2 00/14] PCI: dw-rockchip: Add endpoint mode support
Date: Wed, 8 May 2024 01:48:53 +0200	[thread overview]
Message-ID: <Zjq95dc1odHpNRn7@ryzen.lan> (raw)
In-Reply-To: <20240504170537.GC4315@thinkpad>

Hello Mani,

On Sat, May 04, 2024 at 10:35:37PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Apr 30, 2024 at 02:00:57PM +0200, Niklas Cassel wrote:
> > Hello all,
> > 
> > This series adds PCIe endpoint mode support for the rockchip rk3588 and
> > rk3568 SoCs.
> > 
> > This series is based on: pci/next
> > (git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git)
> > 
> > This series has the following dependencies:
> > 1) https://lore.kernel.org/linux-pci/20240430-pci-epf-rework-v4-0-22832d0d456f@linaro.org/
> > The series in 1) has not been merged to pci/next yet.
> > 
> > 2) https://lore.kernel.org/linux-phy/20240412125818.17052-1-cassel@kernel.org/
> > The series in 2) has already been merged to phy/next.
> > 
> > Even though this series (the series in $subject) has a runtime dependency
> > on the changes that are currently queued in the PHY tree, there is no need
> > to coordinate between the PCI tree and the PHY tree (i.e. this series can
> > be merged via the PCI tree even for the coming merge window (v6.10-rc1)).
> > 
> > This is because there is no compile time dependency between the changes in
> > the PHY tree and this series. Likewise, the device tree overlays in this
> > series passes "make CHECK_DTBS=y" even without the changes in the PHY tree.
> > 
> > This series (including dependencies) can also be found in git:
> > https://github.com/floatious/linux/commits/rockchip-pcie-ep-v2
> > 
> > Testing done:
> > This series has been tested with two rock5b:s, one running in RC mode and
> > one running in EP mode. This series has also been tested with an Intel x86
> > host and rock5b running in EP mode.
> > 
> > BAR4 exposes the ATU Port Logic Structure and the DMA Port Logic Structure
> 
> Is this for configuring the EP from host? Just curious.

That is what I assume as well.
(As I cannot come up with any other reason why they have done this.)

> > pci_epf_test pci_epf_test.0: READ => Size: 1024 B, DMA: YES, Time: 0.000177625 s, Rate: 5764 KB/s
> > pci_epf_test pci_epf_test.0: READ => Size: 1025 B, DMA: YES, Time: 0.000171208 s, Rate: 5986 KB/s
> > pci_epf_test pci_epf_test.0: READ => Size: 1024000 B, DMA: YES, Time: 0.000701167 s, Rate: 1460422 KB/s
> > pci_epf_test pci_epf_test.0: READ => Size: 1024001 B, DMA: YES, Time: 0.000702625 s, Rate: 1457393 KB/s
> > 
> 
> Thanks a lot for sharing the pcitest results in the cover letter.

Thank you for the review!

Kind regards,
Niklas