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From: Andrea Parri <parri.andrea@gmail.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>, Will Deacon <will@kernel.org>,
	Waiman Long <longman@redhat.com>,
	Boqun Feng <boqun.feng@gmail.com>, Arnd Bergmann <arnd@arndb.de>,
	Leonardo Bras <leobras@redhat.com>, Guo Ren <guoren@kernel.org>,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org
Subject: Re: [PATCH 1/7] riscv: Implement cmpxchg32/64() using Zacas
Date: Tue, 28 May 2024 20:16:31 +0200	[thread overview]
Message-ID: <ZlYff9x12FICHoP0@andrea> (raw)
In-Reply-To: <20240528151052.313031-2-alexghiti@rivosinc.com>

> +	asm goto(ALTERNATIVE("nop", "j %[zacas]", 0,			\
> +			     RISCV_ISA_EXT_ZACAS, 1)			\
> +			: : : : zacas);					\
> +									\
>  	__asm__ __volatile__ (						\
>  		prepend							\
>  		"0:	lr" lr_sfx " %0, %2\n"				\
>  		"	bne  %0, %z3, 1f\n"				\
> -		"	sc" sc_sfx " %1, %z4, %2\n"			\
> +		"	sc" sc_cas_sfx " %1, %z4, %2\n"			\
>  		"	bnez %1, 0b\n"					\
>  		append							\
>  		"1:\n"							\
>  		: "=&r" (r), "=&r" (__rc), "+A" (*(p))			\
>  		: "rJ" (co o), "rJ" (n)					\
>  		: "memory");						\
> +	goto end;							\
> +									\
> +zacas:									\
> +	__asm__ __volatile__ (						\
> +		prepend							\
> +		"	amocas" sc_cas_sfx " %0, %z2, %1\n"		\
> +		append							\
> +		: "+&r" (r), "+A" (*(p))				\
> +		: "rJ" (n)						\
> +		: "memory");						\

With this, a cmpxchg32() will result in something like

  amocas.w.rl     a5,a4,(s1)
  fence           rw,rw

(cf. my remarks in patch #4); this will/should provide enough sync,
but you might want to try the alternative and currently more common
mapping for "fully-ordered AMO sequences", aka

  amocas.w.aqrl   a5,a4,(s1)

Similarly for cmpxchg64 and other sizes.

  Andrea

WARNING: multiple messages have this Message-ID (diff)
From: Andrea Parri <parri.andrea@gmail.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>, Will Deacon <will@kernel.org>,
	Waiman Long <longman@redhat.com>,
	Boqun Feng <boqun.feng@gmail.com>, Arnd Bergmann <arnd@arndb.de>,
	Leonardo Bras <leobras@redhat.com>, Guo Ren <guoren@kernel.org>,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org
Subject: Re: [PATCH 1/7] riscv: Implement cmpxchg32/64() using Zacas
Date: Tue, 28 May 2024 20:16:31 +0200	[thread overview]
Message-ID: <ZlYff9x12FICHoP0@andrea> (raw)
In-Reply-To: <20240528151052.313031-2-alexghiti@rivosinc.com>

> +	asm goto(ALTERNATIVE("nop", "j %[zacas]", 0,			\
> +			     RISCV_ISA_EXT_ZACAS, 1)			\
> +			: : : : zacas);					\
> +									\
>  	__asm__ __volatile__ (						\
>  		prepend							\
>  		"0:	lr" lr_sfx " %0, %2\n"				\
>  		"	bne  %0, %z3, 1f\n"				\
> -		"	sc" sc_sfx " %1, %z4, %2\n"			\
> +		"	sc" sc_cas_sfx " %1, %z4, %2\n"			\
>  		"	bnez %1, 0b\n"					\
>  		append							\
>  		"1:\n"							\
>  		: "=&r" (r), "=&r" (__rc), "+A" (*(p))			\
>  		: "rJ" (co o), "rJ" (n)					\
>  		: "memory");						\
> +	goto end;							\
> +									\
> +zacas:									\
> +	__asm__ __volatile__ (						\
> +		prepend							\
> +		"	amocas" sc_cas_sfx " %0, %z2, %1\n"		\
> +		append							\
> +		: "+&r" (r), "+A" (*(p))				\
> +		: "rJ" (n)						\
> +		: "memory");						\

With this, a cmpxchg32() will result in something like

  amocas.w.rl     a5,a4,(s1)
  fence           rw,rw

(cf. my remarks in patch #4); this will/should provide enough sync,
but you might want to try the alternative and currently more common
mapping for "fully-ordered AMO sequences", aka

  amocas.w.aqrl   a5,a4,(s1)

Similarly for cmpxchg64 and other sizes.

  Andrea

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linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2024-05-28 18:16 UTC|newest]

Thread overview: 88+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-28 15:10 [PATCH 0/7] Zacas/Zabha support and qspinlocks Alexandre Ghiti
2024-05-28 15:10 ` Alexandre Ghiti
2024-05-28 15:10 ` [PATCH 1/7] riscv: Implement cmpxchg32/64() using Zacas Alexandre Ghiti
2024-05-28 15:10   ` Alexandre Ghiti
2024-05-28 15:34   ` Conor Dooley
2024-05-28 15:34     ` Conor Dooley
2024-05-29 12:20     ` Alexandre Ghiti
2024-05-29 12:20       ` Alexandre Ghiti
2024-05-30 14:43       ` Conor Dooley
2024-05-30 14:43         ` Conor Dooley
2024-05-28 18:16   ` Andrea Parri [this message]
2024-05-28 18:16     ` Andrea Parri
2024-05-28 15:10 ` [PATCH 2/7] riscv: Implement cmpxchg8/16() using Zabha Alexandre Ghiti
2024-05-28 15:10   ` Alexandre Ghiti
2024-05-28 19:31   ` Nathan Chancellor
2024-05-28 19:31     ` Nathan Chancellor
2024-05-29 12:49     ` Alexandre Ghiti
2024-05-29 12:49       ` Alexandre Ghiti
2024-05-29 15:57       ` Nathan Chancellor
2024-05-29 15:57         ` Nathan Chancellor
2024-06-03 15:31         ` Alexandre Ghiti
2024-06-03 15:31           ` Alexandre Ghiti
2024-05-28 23:54   ` Andrea Parri
2024-05-28 23:54     ` Andrea Parri
2024-05-29 12:29     ` Alexandre Ghiti
2024-05-29 12:29       ` Alexandre Ghiti
2024-05-29 12:55       ` Alexandre Ghiti
2024-05-29 12:55         ` Alexandre Ghiti
2024-05-28 15:10 ` [PATCH 3/7] riscv: Implement arch_cmpxchg128() using Zacas Alexandre Ghiti
2024-05-28 15:10   ` Alexandre Ghiti
2024-05-28 15:10 ` [PATCH 4/7] riscv: Implement xchg8/16() using Zabha Alexandre Ghiti
2024-05-28 15:10   ` Alexandre Ghiti
2024-05-28 15:22   ` Conor Dooley
2024-05-28 15:22     ` Conor Dooley
2024-05-29  6:15     ` Alexandre Ghiti
2024-05-29  6:15       ` Alexandre Ghiti
2024-05-28 18:00   ` Andrea Parri
2024-05-28 18:00     ` Andrea Parri
2024-05-29  8:04     ` Alexandre Ghiti
2024-05-29  8:04       ` Alexandre Ghiti
2024-05-28 15:10 ` [PATCH 5/7] asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock Alexandre Ghiti
2024-05-28 15:10   ` Alexandre Ghiti
2024-05-28 15:10 ` [PATCH 6/7] asm-generic: ticket-lock: Add separate ticket-lock.h Alexandre Ghiti
2024-05-28 15:10   ` Alexandre Ghiti
2024-05-28 15:10 ` [PATCH 7/7] riscv: Add qspinlock support based on Zabha extension Alexandre Ghiti
2024-05-28 15:10   ` Alexandre Ghiti
2024-05-29  0:55   ` Andrea Parri
2024-05-29  0:55     ` Andrea Parri
2024-05-31 13:37     ` Alexandre Ghiti
2024-05-31 13:37       ` Alexandre Ghiti
2024-05-31 15:52       ` Andrea Parri
2024-05-31 15:52         ` Andrea Parri
2024-06-01  6:18         ` Guo Ren
2024-06-01  6:18           ` Guo Ren
2024-06-03  0:41           ` Andrea Parri
2024-06-03  0:41             ` Andrea Parri
2024-05-29  9:23   ` Guo Ren
2024-05-29  9:23     ` Guo Ren
2024-05-29 13:03     ` Alexandre Ghiti
2024-05-29 13:03       ` Alexandre Ghiti
2024-05-30  1:54       ` Guo Ren
2024-05-30  1:54         ` Guo Ren
2024-05-30  5:30         ` Alexandre Ghiti
2024-05-30  5:30           ` Alexandre Ghiti
2024-05-31  1:57           ` Guo Ren
2024-05-31  1:57             ` Guo Ren
2024-05-31  6:22             ` Alexandre Ghiti
2024-05-31  6:22               ` Alexandre Ghiti
2024-05-31  6:42               ` Guo Ren
2024-05-31  6:42                 ` Guo Ren
2024-06-03  9:21                 ` Alexandre Ghiti
2024-06-03  9:21                   ` Alexandre Ghiti
2024-06-03 11:11                   ` Guo Ren
2024-06-03 11:11                     ` Guo Ren
2024-05-31 13:10       ` Guo Ren
2024-05-31 13:10         ` Guo Ren
2024-06-03  9:49         ` Alexandre Ghiti
2024-06-03  9:49           ` Alexandre Ghiti
2024-06-03 11:28           ` Guo Ren
2024-06-03 11:28             ` Guo Ren
2024-06-03 11:34             ` Alexandre Ghiti
2024-06-03 11:34               ` Alexandre Ghiti
2024-06-03 11:44               ` Guo Ren
2024-06-03 11:44                 ` Guo Ren
2024-06-03 11:49                 ` Alexandre Ghiti
2024-06-03 11:49                   ` Alexandre Ghiti
2024-06-03 11:57                   ` Guo Ren
2024-06-03 11:57                     ` Guo Ren

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