[GIT PULL] u-boot-riscv/master

[Leo Liang <ycliang@andestech.com>]

Hi Tom,

The following changes since commit 46ff00bea5dd2dd247d5e2fdadbf5dcf8653cd9a:

  Merge tag 'tpm-master-27052024' of https://source.denx.de/u-boot/custodians/u-boot-tpm (2024-05-27 08:56:02 -0600)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git 

for you to fetch changes up to 1d29c718b7ba09807f8060796d9c21772e3c1b52:

  andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND (2024-05-30 16:01:13 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/20920
----------------------------------------------------------------

- board: fix support for icicle
- board: support Star64 board
- andes: minor fixes
- riscv: deprecate cache enablement in start.S

----------------------------------------------------------------
Conor Dooley (2):
      board: microchip: icicle: correct type for node offset
      board: microchip: icicle: make both ethernets optional

H Bell (2):
      board: starfive: support Pine64 Star64 board
      board: starfive: support Pine64 Star64 board

Leo Yu-Chi Liang (3):
      andes: l2 cache driver: fixes typos and cctl status
      riscv: remove cache enablement in start.S
      andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND

 arch/riscv/cpu/andes/cache.c                      |   4 +-
 arch/riscv/cpu/start.S                            |   4 -
 arch/riscv/include/asm/arch-andes/csr.h           |   2 +-
 board/microchip/mpfs_icicle/mpfs_icicle.c         |  25 +--
 board/starfive/visionfive2/spl.c                  |  89 ++++++++++
 board/starfive/visionfive2/starfive_visionfive2.c |   4 +
 doc/board/starfive/index.rst                      |   1 +
 doc/board/starfive/pine64_star64.rst              | 201 ++++++++++++++++++++++
 drivers/cache/cache-andes-l2.c                    |   8 +-
 9 files changed, 310 insertions(+), 28 deletions(-)
 create mode 100644 doc/board/starfive/pine64_star64.rst

Best regards,
Leo